100397QI - Fairchild Semiconductor

January 1992

Revised August 2000

100397 Quad Differential ECL/TTL Translating Transc eiver with Latch

100397

Quad Differe nt ial ECL/TTL Translating Transceiver

with Latch

General Description

The 100397 is a quad latched transceiver designed to con-

vert TTL logic levels to differential F100K ECL logic levels

and vice ver sa. T his de vi ce was desig ned wit h the capa bi l-

ity of driving a differential 25Ω ECL load with cutoff capabil-

ity, and will sink a 64 mA TTL load. The 100397 is ideal f or

mixed technology applications utilizing either an ECL or

TTL backplane.

The direction of translation is set by the direction control

pin (DIR). The D IR pin on the 100397 accepts F 100K E CL

logic levels . An ECL LOW on DIR sets u p the ECL pi ns as

inputs and TTL pins as outputs. An E CL HIGH on DIR sets

up the TTL pins as inputs and ECL pins as outputs.

A LOW on the o utput en able inp ut pi n (OE) holds the E CL

output in a cut-off state and the TTL outputs at a high

impedance level. A HIGH on the latch enable input (LE)

latches the data at both inputs even though only one output

is enabled at the time. A LOW on LE makes the latch trans-

parent.

The cut-off state is designed to be more negative than a

normal ECL LOW level. This allows the output emitterfol-

lowers to turn off when the termination supply is −2.0V, pre-

senting a high impedance to the data bus. This high

impedance reduces termination power and prevents loss of

low state noise margin when several loads share the bus.

The 100397 is designed with FAST TTL output buffers,

featurin g optima l DC drive an d capabl e of quickly cha rging

and discharging highly capacitive loads. All inputs have

50 KΩ pull-down resistors.

Features

■Differential ECL input/output structure

■64 mA FAST TTL outputs

■25Ω differential ECL outputs with cut-off

■Bi-directional translation

■2000V ESD protection

■Latched outputs

■3-STATE outputs

■Voltage compensated operating range = −4.2V to −5.7V

Ordering Code:

Devices also available in Ta pe and Reel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

FAST is a register ed t radem ark of F airchild Semicon ductor Corporation.

Order Number Package Number Package Description

100397PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100397QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100397QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

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100397

Logic Symbol

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Pin Descriptions

All pins function at 100K ECL levels except for T0–T3.

Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Don't Care

Z = High Impedance

Note 1: ECL inpu t t o T T L output mo de.

Note 2: TTL input to ECL output mode.

Note 3: Retains data present before LE set HIGH.

Note 4: Latch is tran s parent .

Pin Names Description

E0–E3ECL Data I/O

E0–E3Complementary ECL Data I/O

T0–T3TTL Data I/O

OE Output Enable Input (ECL Levels)

LE Latch Enable Input (ECL Levels)

DIR Direction Control Input (ECL levels)

GNDECL ECL Ground

GNDECLO ECL Output Ground

GNDS ECL Ground-to-Substrate

VEE ECL Quiescent Power Supply

VEED ECL Dynamic Power Supply

GNDTTL TTL Quiescent Groun d

GNDTTLD TTL Dynami c Grou nd

VTTL TTL Quiescent Power Supply

VTTLD TTL Dynamic Pow er Supply

LE DIR OE ECL TTL Notes

Port Port

000LOWZ

(Cut-Off)

0 0 1 Input Output (Note 1)(Note 4)

010LOWZ

(Cut-Off)

0 1 1 Output Input (Note 2)(Note 4)

1 0 0 Input Z (Note 1)(Note 3)

1 0 1 Latched X (Note 1)(Note 3)

1 1 0 LOW Input (Note 2)(Note 3)

(Cut-Off)

1 1 1 Latched X (Note 2)(Note 3)

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100397

Functional Diagram

Note: LE, D I R , an d OE use EC L logic lev els

Detail

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100397

Absolute Maximum Ratings(Note 5) Recommended Operating

Conditions

Note 5: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 6: ESD te s ti ng c onforms t o M I L-STD-8 83, Meth od 3015.

Note 7: Eith er v oltage lim it or c urrent limit is sufficien t to prot ect inputs .

Commercial Version

TTL-to-ECL DC Electrical Characteristics (Note 8)

VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V

Note 8: The specified limits represe nt the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

Storage Temperature (TSTG)−65°C to +150°C

Maximum Ju nction Temper atur e

(TJ)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

VTTL Pin Potential to Ground Pin −0.5V to +6.0V

ECL Input Voltage (DC) VEE to +0.5V

ECL Output Current

(DC Output HIGH) −50 mA

TTL Input Voltage (Note 7) −0.5V to +7.0V

TTL Input Current (Note 7) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State

3-STATE Output −0.5V to +5.5V

Current Applied to TTL

Output in LOW State (Max) twice the Rated IOL (mA)

ESD (Note 6) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

ECL Supply Voltage (VEE)−5.7V to −4.2V

TTL Supply Voltage (VTTL)+4.5V to +5.5V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH(Max) or VIL(Min)

VOL Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to − 2V

Cutoff Voltage OE and LE Low, DIR High

−2000 −1950 mV VIN = VIH(Max) or VIL(Min),

Loading with 50Ω to −2V

VOHC Output HIGH Voltage −1035 mV

Corner Point High VIN = VIH(Min) or VIL(Max)

VOLC Output LOW Voltage −1610 mV Loading with 50Ω to −2V

Corner Point Low

VIH Input HIGH Voltage 2.0 5.0 V Over VTTL, VEE, TC Range

VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Range

IIH Input HIGH Current 5.0 µAV

IN = +2.7V

IBVIT Input HIGH Current 0.5 mA VIN = 5.5V

Breakdown (I/O)

IIL Input LOW Current −1.0 mA VIN = +0.5V

VFCD Input Clamp −1.2 V IIN = −18 mA

Diode Voltage

IEE VEE Supply Current −99 −50 LE Low, OE and DIR HIGH

Inputs Open

IEEZ VEE Supply Current −159 −90 LE and OE Low, Dir HIGH

Inputs Open

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100397

Commercial Version (Continu ed)

ECL-to-TTL DC Electrical Characteri stics (Note 9)

VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V

Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are cho-

sen to guarante e operation under “worst case” conditions.

DIP and PCC TTL-to-ECL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage 2.7 3.1 V IOH = −3 mA, VTTL = 4.75V

2.4 2.9 V IOH = −3 mA, VTTL = 4.50V

VOL Output LOW Voltage 0.3 0.5 V IOL = 24 mA, VTTL = 4.50V

VIH Input HIGH V olta ge −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1475 mV Guaranteed LOW Signal for All Inputs

VDIFF Input Voltage Differential 150 mV Required for Full Output Swing

VCM Common Mode Voltage GNDECL − 2.0 GNDECL − 0.5 V

IIH Input HIGH Current

E0–E3, E0–E3240 µAV

IN = VIH(Max)

OE, LE, DIR 35

ICEX Output HIGH 50 µAV

OUT = VTTL

Leakage Current

IZZ Bus Drainage Test 500 µAV

OUT = 5.25V

VTTL = 0.0V

IIL Input LOW Current 0.50 µAV

IN = VIL(Min)

IOZHT 3-STATE Curre nt 70 µAV

OUT = +2.7V

Output High

IOZLT 3-ST ATE Curre nt −650 µAV

OUT = +0.5V

Output Low

IOS Output Short-Circuit −100 −225 mA VOUT = 0.0V, VTTL = +5.5V

Current

ITTL VTTL Supply Current 39 mA TTL Outputs LOW

27 mA TTL Outputs HIGH

39 mA TTL Outputs in 3-STATE

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

MinMaxMinMaxMinMax

fMAX Maximum Clock Frequency 180 180 180 MHz

tPLH Tn to En, En0.9 2.1 0.8 2.2 0.7 2.5 ns Figures 1, 3

tPHL (Transparent)

tPLH LE to En, En1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3

tPHL

tPZH OE to En, En2.5 4.5 2.5 4.5 2.5 4.6 ns Figures 1, 3

(Cutoff to HIGH)

tPHZ OE to En, En2.1 3.8 2.3 4.0 2.5 4.5 ns Figures 1, 3

(HIGH to Cutoff)

tPHZ DIR to En, En2.0 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3

(HIGH to Cutoff)

tSTn to LE 0.8 0.8 0.8 ns Figures 1, 3

tHTn to LE 0.6 0.6 0.6 ns Figures 1, 3

tTLH Transition Time 0.8 2.8 0.8 2.8 0.8 2.8 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

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100397

Commercial Version (Continued)

DIP and PCC ECL-to-TTL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF

Industrial Version

TTL-to-ECL DC Electrical Characteristics (Note 10)

VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V

Note 10: The specified lim it s represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 75 75 75 MHz

tPLH En, En to Tn1.7 4.9 1.7 5.1 1.8 5.8 ns Figures 2, 4

tPHL (Transparent)

tPLH LE to Tn2.2 4.0 2.2 4.0 2.3 4.1 ns Figures 2, 4

tPHL 3.3 5.2 3.4 5.4 3.8 6.1

tPZH OE to Tn3.2 5.6 3.3 5.7 3.6 6.3 ns Figures 2, 5

tPZL (Enable Time) 4.9 8.3 5.1 8.5 5.6 9.2

tPHZ OE to Tn3.6 8.6 3.5 8.3 3.5 7.5 ns Figures 2 , 5

tPLZ (Disable Time) 3.4 6.9 3.5 6.7 3.6 6.7

tPHZ DIR to Tn3.5 8.1 3.5 8.1 3.5 7.6 ns Figures 2, 6

tPLZ (Disable Time) 3.4 6.8 3.4 6.7 3.6 6.7

tSEn, En to LE 0.6 0.6 0.6 ns Figures 2, 4

tHEn, En to LE 0.7 0.7 0.7 ns Figures 2, 4

tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1085 −955 −870 mV VIN = VIH(Max) or VIL(Min)

VOL Output LOW Voltage −1830 −1705 −1575 mV Loading with 50Ω to −2V

Cutoff Voltage OE and LE LOW, DIR HIGH

−2000 −1900 mV VIN= VIH(Max) or VIL(Min),

Loading with 50Ω to −2V

VOHC Output HIGH Voltage −1095 mV

Corner Point HIGH VIN = VIH(Min) or VIL(Max)

VOLC Output LOW Voltage −1565 mV Loading with 50Ω to −2V

Corner Point LOW

VIH Input HIGH Voltage 2.0 5.0 V Over VTTL, VEE, TC Range

VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Range

IIH Input HIGH Current 5.0 µAV

IN = +2.7V

IBVIT Input HIGH Current 0.5 mA VIN = 5.5V

Breakdown (I/O)

IIL Input LOW Current −1.0 mA VIN = +0.5V

VFCD Input Clamp −1.2 V IIN = −18 mA

Diode Voltage

IEE VEE Supply Current −99 −40 LE Low, OE and DIR HIGH

Inputs Open

IEEZ VEE Supply Current −159 −90 LE and OE LOW, Dir HIGH

Inputs Open

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100397

Industri al Version (Continu ed)

ECL-to-TTL DC Electrical Characteri stics (Note 11)

VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V

Note 11: The specified lim its repr es ent the “worst case” value for the par ame ter. Since these v alues norm ally occ ur at the te mpe ratur e extrem es , additi ona l

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are cho-

sen to guarante e operation under “worst case” conditions.

PCC TTL-to-ECL AC Electrica l Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage 2.7 3.1 V IOH = −3 mA, VTTL = 4.75V

2.4 2.9 V IOH = −3 mA, VTTL = 4.50V

VOL Output LOW Voltage 0.3 0.5 V IOL = 24 mA, VTTL = 4.50V

VIH Input HIGH V olta ge −1170 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1480 mV Guaranteed LOW Signal for All Inputs

VDIFF Input Voltage Differential 150 mV Required for Full Output Swing

VCM Common Mode Voltage GNDECL − 2.0 GNDECL − 0.5 V

IIH Input HIGH Current VIN = VIH(Max)

E0–E3, E0–E3300 µA

OE, LE, DIR 35

ICEX Output HIGH 50 µAV

OUT = VTTL

Leakage Current

IZZ Bus Drainage Test 500 µAV

OUT = 5.25V

VTTL = 0.0V

IIL Input LOW Current 0.50 µAV

IN = VIL(Min)

IOZHT 3-STATE Curre nt 70 µAV

OUT = +2.7V

Output HIGH

IOZLT 3-ST ATE Curre nt −650 µAVOUT = +0.5V

Output LOW

IOS Output Short-Circuit Current −100 −225 mA VOUT = 0.0V, VTTL = +5.5V

ITTL VTTL Supply Current 39 mA TTL Outputs LOW

27 mA TTL Outputs HIGH

39 mA TTL Outputs in 3-STATE

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

fMAX Maximum Clock Frequency 180 180 180 MHz

tPLH Tn to En, En0.9 2.4 0.8 2.2 0.7 2.5 ns Figures 1, 3

tPHL (Transparent)

tPLH LE to En, En1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3

tPHL

tPZH OE to En, En1.9 3.8 2.5 4.5 2.5 4.6 ns Figures 1, 3

(Cutoff to HIGH)

tPHZ OE to En, En2.5 4.7 2.3 4.0 2.5 4.5 ns Figures 1, 3

(HIGH to Cutoff)

tPHZ DIR to En, En1.8 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3

(HIGH to Cutoff)

tSTn to LE 0.8 0.8 0.8 ns Figures 1, 3

tHTn to LE 0.6 0.6 0.6 ns Figures 1, 3

tTLH Transition Time 0.8 2.8 0.8 2.8 0.8 2.8 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

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100397

Industrial Version (Continued)

PCC ECL-to-TTL AC Electrical Charact eristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 75 75 75 MHz

tPLH En, En to Tn1.7 4.9 1.7 5.1 1.8 5.8 ns Figures 2, 4

tPHL (Transparent)

tPLH LE to Tn2.2 4.3 2.2 4.0 2.3 4.1 ns Figures 2, 4

tPHL 3.3 5.2 3.4 5.4 3.8 6.1

tPZH OE to Tn3.1 5.6 3.3 5.7 3.6 6.3 ns Figures 2, 5

tPZL (Enable Time) 4.8 8.3 5.1 8.5 5.6 9.2

tPHZ OE to Tn3.5 9.2 3.5 8.3 3.5 7.5 ns Figures 2 , 5

tPLZ (Disable Time) 3.2 7.3 3.5 6.7 3.6 6.7

tPHZ DIR to Tn3.5 8.8 3.5 8.1 3.5 7.6 ns Figures 2, 6

tPLZ (Disable Time) 3.2 7.2 3.4 6.7 3.6 6.7

tSEn, En to LE 0.6 0.6 0.6 ns Figures 2, 4

tHEn, En to LE 0.7 0.7 0.7 ns Figures 2, 4

tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4

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100397

Test Circuitry (TTL-to-ECL)

Notes:

Rt = 50Ω terminat ion. W hen an in put o r ou tpu t is bein g m oni tored by a sc ope, Rt is s uppl ied by the sc ope’s 50Ω resistan ce. W hen an input or ou tput is n ot

being monitore d, and external 50Ω resistance must be applied to serve as Rt.

TTL and EC L force s ignals are brough t to t he DUT via 50Ω coax lines.

VTTL is decoupled to ground wit h 0. 1 µF to ground, VEE is decou pled to ground with 0. 01 µF and GND is connected to ground.

For ECL input pins, the equivalent force/sense circuitry is optional.

FIGURE 1. TTL-to-ECL AC Test Circuit

Switching Waveforms (TTL-to-ECL)

FIGURE 2. TTL to ECL Transition—Propagation Delay and Transiti on Times

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100397

Test Circuitry (ECL-to- TTL)

Notes:

Rt = 50Ω term ina tion. W hen an input or ou tput is b eing m o nito red by a s cope , Rt is supplied by the scope’s 50Ω resistanc e. Wh en an inp ut or outp ut is no t

being m onito red, and ex te rnal 50Ω resistance must be applied to serve as Rt.

The TTL 3-STATE pull up switch is connected to +7V onl y fo r ZL and LZ tests.

TTL and ECL fo rc e s ignals are brought t o the DUT v ia 50Ω coax lines.

VTTL is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF a nd GND is co nnected to g r ound.

FIGURE 3. ECL-to-TTL AC Test Circuit

Note:

DIR is LOW, and OE is HI GH

FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times

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100397

Test Circuitry (ECL-to-TTL) (Continued)

Note:

DIR is LOW, LE is HIGH

FIGURE 5. ECL-to-TTL Transition, OE to TTL Output,

Enable and Disable Times

Note:

OE is HIGH, LE is HIGH

FIGURE 6. ECL-to-TTL T ransition, DIR to TTL Output,

Disable Time

Applications

FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100397 ECL–TTL Latched Translator

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100397

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100397 Quad Differential ECL/TTL Translating Transceiver with Latch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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