2000 Microchip Technology Inc. Advance Information DS30325A-page 1
PIC16F7X
Devices Included in this Data Sheet:
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Progr am M em ory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Pinout compatible to the PIC16C73B/74B/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Eight level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Pow er-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscilla tor f or reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low p ower, high spe ed CMO S FLASH technology
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Processor read access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Industri al tem pera ture range
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Di agram
Peripheral Features:
• Timer0: 8-bit timer/coun ter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be increm ent ed duri ng SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM mo dules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C (Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD , WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
•PIC16F73
•PIC16F74 •PIC16F76
•PIC16F77 RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F77/74
PDIP
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
PIC16F7X
DS30325A-page 2 Advance Information 2000 Microchip Technology Inc.
Pin Diagra ms
PIC16F76/73
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9PIC16F77
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F77
37
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
PLCC
QFP
DIP, SOIC, SSOP
PIC16F74
PIC16F74
2000 Microchip Technology Inc. Advance Information DS30325A-page 3
PIC16F7X
Key Features
PICmicro™ Mid-Range Reference Manual
(DS33023) PIC16F73 PIC16F74 PIC16F76 PIC16F77
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR
(PWR T, OST) POR, BOR
(PW RT, OST) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST)
FLASH P rogram Memory
(14-bit words, 100 E/W cycles) 4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
Interrupts 11 12 11 12
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART
Parallel Communications — PSP —PSP
8-bit Analog-to-Digital Module 5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
PIC16F7X
DS30325A-page 4 Advance Information 2000 Microchip Technology Inc.
Table of Contents
1.0 Device Overview............................................................................................................................................................ 5
2.0 Memory O rganization .................................................................................................................................................. 11
3.0 I/O Ports.......... ..................... .......... ........... .......... ..................... ........... .......... ............................................................... 29
4.0 Reading Program Memory..... .. .... .... .... ....... .... .... .... ......... .. .... .... .... ....... .... .... .... ......... .. .... .... ........................................ 41
5.0 Timer0 Module............................................................................................................................................................. 45
6.0 Timer1 Module............................................................................................................................................................. 49
7.0 Timer2 Module............................................................................................................................................................. 53
8.0 Capture/Compare/PWM Modules..................... .. .... .. ......... .... .. .... ......... .. .... .. .... ......... .. .... .... .. ...................................... 55
9.0 Syn chronous Serial Port (SS P) Mo dule....................................................................................................................... 61
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)............................................. ...... ................... 73
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89
12.0 S p e cial Featur e s of th e CPU............... ........... ..................... ..................... .......... ......................................................... 95
13.0 Instruction Set Summary ........................................................................................................................................... 111
14.0 Development Support................................................................................................................................................ 119
15.0 Electrical Characteristics ........................................................................................................................................... 125
16.0 DC and AC Characteristics Graphs and Tables .......................... ......... .... .... .... .. ......... .... .... .. ......... ........................... 147
17.0 P a ck a g i n g In fo rmation............... .......... ..................... ........... .......... ..................... ........... ............................................ 149
Appendix A: Revision History............................................................... ...... .... .... ........... .... .... ......................................................... 157
Appendix B: Device Differences..................... .. .... .. ......... .. .... .. .... ....... .... .. .... .... .. ....... .... .... .. .... ....................................................... 157
Appendix C: Conversion Considerations ... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. .. .... ....... .. .... .. .. .... ....... .. .............................................. 157
Index .................................................................................................................................................................................................. 159
On-Line Support............. .... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. ................................................................. 165
Reader Response.............................................................................................................................................................................. 166
PIC16F7X Product Identification System. .......................................................................................................................................... 167
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2000 Microchip Technology Inc. Advance Information DS30325A-page 5
PIC16F7X
1.0 DEVICE OVERVIEW
This document contains device specific information.
Addition al in form ati on m ay be found in the PICm ic ro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip web site. The
Reference Manual should be considered a comple-
ment ary do cumen t to thi s dat a she et, and is hig hly re c-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are four devices (PIC16F73, PIC16F74,
PIC16 F76 an d PIC1 6F77) co vere d by thi s data she et.
The PI C16F76/73 d evices are availab le in 28 -pin p ack-
ages and the PIC16F77/74 devices are available in
40-pin packages. The 28-pin devices do not have a
Parallel Slave Port implemented.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28 -pin and 40-pin pino uts are liste d
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher ord er bits are from the STAT U S regi st er.
USART
CCP1,2 Synchronous
8-bit A/DTimer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF
RA2/AN2/
RA1/AN1
RA0/AN0
8
3
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Device Program
FLASH Dat a Memory
PIC16F73 4K 192 Bytes
PIC16F76 8K 368 Bytes
PIC16F7X
DS30325A-page 6 Advance Information 2000 Microchip Technology Inc.
FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI
RA5/AN4/SS
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1,2 Synchronous
8-bit A/DTimer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Device Program
FLASH Data Memory
PIC16F74 4K 192 Bytes
PIC16F77 8K 368 Bytes
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
2000 Microchip Technology Inc. Advance Information DS30325A-page 7
PIC16F7X
TABLE 1-1: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
Pin Name DIP
Pin#
SSOP
SOIC
Pin#
I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/ external clock source input.
OSC2/CLKOUT 10 10 O —Oscillator cr ystal output. Connect s to crystal or re so nator in Crys-
tal Oscillator mode. In RC mode, the OSC2 pin ou tputs CLKOUT
which has 1/4 the freq uen cy of OSC1, and denote s the ins tr uctio n
cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (RESET ) input or programming voltage inpu t or High
Voltage Test mode control. This pin is an activ e low RESET to th e
device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1.
RA2/AN2 4 4 I/O TTL RA2 can also be analog input2.
RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference vo ltage.
RA4/T0 CKI 6 6 I/O ST RA4 can als o be the c lock inpu t to the Timer0 module. Outp ut
is open drain type.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-dir ectional I/O port. PORTB can be softwar e
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt-on-change pin or Serial programming clock .
RB7 28 28 I/O TTL/ST(2) Interrupt-on-change pin or Serial programming data.
PORTC is a bi-directi onal I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillato r output or Timer1 clock
input.
RC1/T1OSI /CCP2 12 12 I/O ST RC1 can also be the T imer1 os cillator input or Capture2 input /
Compar e2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can als o be the Capture1 input/ Compa re1 outpu t/PWM1
output.
RC3/SCK/S CL 14 14 I/O ST RC3 can also be the s ynchronou s seri al clock inpu t/outp ut for
both SPI and I2C modes .
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
Data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USAR T Async hronous Tr ansmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchrono us Receive or
Synchronous Data.
VSS 8, 19 8, 19 P —Ground reference for logic and I/O pins.
VDD 20 20 P —Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T rigger input
Note 1: This buffer is a Schmitt Trigger input when configur ed as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Progr amming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F7X
DS30325A-page 8 Advance Information 2000 Microchip Technology Inc.
TABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
Pin N a me DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 14 15 31 O —Oscillator crystal outp ut. Connects to crystal or resonator in
Crystal Oscillator mode . In RC mode, O SC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input or
High Voltage Test mode control. This pin is an active low
RESET to the device.
PORTA is a bi - d i re c t i on al I/O po r t.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1.
RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2.
RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
voltage.
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the
synchr onous serial port .
PORT B is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be t he external i nterrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt-on-change pin.
RB5 38 42 15 I/O TTL Interrupt-on-change pin.
RB6 39 43 16 I/O TTL/ST(2) Interrupt-on-change pin or Serial programming clock.
RB7 40 44 17 I/O TTL/ST(2) Interrupt-on-change pin or Serial programming data.
PORTC is a b i- d i r ection a l I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input /Compare2 output/PWM2 output.
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/S CL 18 20 37 I/O ST RC3 c an a lso be the synchrono us ser ial cloc k input /output
for bot h SP I an d I 2C modes.
RC4/S D I/S D A 23 2 5 42 I/O ST RC4 can also be th e SP I D ata In (SPI mode) or
Data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T rigger input
Note 1: This buffer is a S chmit t Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when c onfigured in RC Oscillator mode and a CMOS input otherwise.
2000 Microchip Technology Inc. Advance Information DS30325A-page 9
PIC16F7X
PORTD is a bi-directional I/O port or parallel slave port when
interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-direct i onal I/O port.
RE0/RD/AN5 8925I/O
ST/TTL(3) RE 0 can also b e read cont rol for t he par allel slave port, or
analog input5.
RE1/WR/AN6 91026I/O
ST/TTL(3) RE 1 ca n a lso be write cont rol for t he p a ralle l slave por t, or
analog input6.
RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port,
or analog input7.
VSS 12,31 13,34 6,29 P —Ground ref erence for logic and I/O pins.
VDD 11,32 12,35 7,28 P —Positive supply for logic and I/O pins.
NC —1,17,28,
40 12,13,
33,34 —These pins are not inter nally connec ted. These pins should b e
left unconnected.
TABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
Pin N a me DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T rigger input
Note 1: This buffer is a S chmit t Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Progr amming mode.
3: This buffer is a Schmitt Trigger input when conf igured as general purpose I/O and a TTL inpu t when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F7X
DS30325A-page 10 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 11
PIC16F7X
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Prog ram Mem ory can be read i nternal ly by us er code
(see Section 4.0).
Addit ional informat ion on devi ce memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space . The P IC16 F77/ 76 d evic es ha ve 8K x 1 4 wor ds
of FLASH program memory and the PIC16F73/74
devic es have 4K x 14 . Acce ssin g a loc ati on abov e the
physically implemented address will cause a wrap-
around.
The RESET Vector is at 0000h an d the Interrupt Vector
is at 0004h.
FIGURE 2-1: PIC16F 77 /76 PROGRAM
MEMORY MAP AND STACK
FIGURE 2-2: PIC16F74/73 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
Page 2
Page 3
07FFh
0800h
0FFFh
1000h
17FFh
1800h
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
PIC16F7X
DS30325A-page 12 Advance Information 2000 Microchip Technology Inc.
2.2 Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The regist er file can be accesse d either dire ctly , or ind i-
rectly, through the File Select Register FSR.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
2000 Microchip Technology Inc. Advance Information DS30325A-page 13
PIC16F7X
FIGURE 2-3: PI C16F77 /76 REGIS TER F ILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Not e 1: These registers are not im ple me nte d on 28-pin devices.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
120h 1A0h
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
70h - 7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
General
Purpose
Register
General
Purpose
Register
TRISB
PORTB
96 Bytes 80 Bytes 80 Bytes 80 Bytes
16 Bytes 16 Bytes
PMDATA
PMADR PMCON1
PMDATH
PMADRH
File
Address
File
Address
File
Address
SSPADD
PIC16F7X
DS30325A-page 14 Advance Information 2000 Microchip Technology Inc.
FIGURE 2-4: PI C16F74 /73 REGIS TER F ILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
A0h - FFh
16Fh
170h
accesses
20h-7Fh
TRISB
PORTB
96 Bytes 96 Bytes
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
PMDATA
PMADR PMCON1
PMDATH
PMADRH
Unimplemented data memory locations, read as ’0’.
* Not a physical regis ter.
Note 1: These registers are not implemented on 28-pin devices.
120h 1A0h
File
Address
File
Address
File
Address
SSPADD
2000 Microchip Technology Inc. Advance Information DS30325A-page 15
PIC16F7X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS(2)
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 T i mer0 Module’s Register xxxx xxxx uuuu uuuu
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(4) STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — POR TA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/
DONE —ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplement ed read as '0', r = reserved.
Shaded loc ations are unimplemented, read as ‘0’.
Note 1: The upper byte of the pr ogram counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
conten ts are transferred to the upper byte of the pr ogram counter.
2: Other (non power-up) RES ET S inc l ude external RESET th rough MCLR and Wa tchdog Timer Reset.
3: Bits PS PI E and PSP I F are re se r v e d on the 28- p in devic e s; alw ay s ma i nta in th ese bits cle a r.
4: These registers can be addressed from any bank.
5: PORTD, POR TE, TRISD, and TRISE are not physic ally implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
PIC16F7X
DS30325A-page 16 Advance Information 2000 Microchip Technology Inc.
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_
REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h(4) STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx 000q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE —PORTE Dat a D irection Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh —Unimplemented — —
90h —Unimplemented — —
91h —Unimplemented — —
92h PR2 T imer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch —Unimplemented — —
9Dh —Unimplemented — —
9Eh —Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplement ed read as '0', r = reserved.
Shaded loc ations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RES ET S inc l ude external RESET th rough MCLR and Wa tchdog Timer Reset.
3: Bits PS PI E and PSP I F are re se r v e d on the 28- p in devic e s; alw ay s ma i nta in th ese bits cle a r.
4: These registers can be addressed from any bank.
5: PORTD, POR TE, TRISD, and T RISE are not physically implemented on the 28-pin devices , read as ‘0’.
6: This bit always reads as a ‘1’.
2000 Microchip Technology Inc. Advance Information DS30325A-page 17
PIC16F7X
Bank 2
100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
104h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h —Unimplemented — —
106h PORTB PORTB Dat a Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch PMDATA Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh PMADR Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH — — Data Register High Byte xxxx xxxx uuuu uuuu
10Fh PMADRH — — — Address Register High Byte xxxx xxxx uuuu uuuu
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_
REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
184h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch PMCON1 — (6) — — — — — — RD 1--- ---0 1--- ---0
18Dh —Unimplemented — —
18Eh —Reserved maintain clear 0000 0000 0000 0000
18Fh —Reserved maintain clear 0000 0000 0000 0000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplement ed read as '0', r = reserved.
Shaded loc ations are unimplemented, read as ‘0’.
Note 1: The upper byte of the pr ogram counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
conten ts are transferred to the upper byte of the pr ogram counter.
2: Other (non power-up) RES ET S inc l ude external RESET th rough MCLR and Wa tchdog Timer Reset.
3: Bits PS PI E and PSP I F are re se r v e d on the 28- p in devic e s; alw ay s ma i nta in th ese bits cle a r.
4: These registers can be addressed from any bank.
5: PORTD, POR TE, TRISD, and TRISE are not physic ally implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
PIC16F7X
DS30325A-page 18 Advance Information 2000 Microchip Technology Inc.
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of
the ALU, th e RESET s tatu s and the b ank sele ct bit s for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destinatio n for an instruction that affects
the Z, DC, or C bit s, then the writ e to these thre e bit s is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit . This le aves the STATUS regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, or DC bits from the STATUS register.
For o t her in s tru ct i o ns no t aff ec t in g an y s tat us b its, s ee
the "Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Regi ster Bank Select bit ( used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 by tes
bit 4 TO: Time-out bit
1 = After po wer-up, CLRWDT instruct ion, or SLEEP instruct ion
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instr ucti ons)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = B it i s set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 19
PIC16F7X
2.2.2.2 OPTION_REG Register
The OPTION_REG register is a readable and writable
register, which con tains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bi t
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Ass ign me nt bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value T MR0 Rate WDT Rate
PIC16F7X
DS30325A-page 20 Advance Information 2000 Microchip Technology Inc.
2.2.2.3 INTCO N Register
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt fl ag bits are set whe n an in terru pt
conditi on occ urs , re gardless of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB po rt change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TM R0 regis ter did no t overfl ow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 21
PIC16F7X
2.2.2.4 PIE1 Register
The PIE1 regi ster cont ains the indivi dual enable b its for
the peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converte r interru pt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USAR T rece iv e interru pt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USAR T trans mi t interr upt
0 = Disabl es the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interru pt
0 = Disabl es the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Matc h Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow inte rrupt
0 = Disables the TMR1 over flow interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clea r.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at PO R reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 22 Advance Information 2000 Microchip Technology Inc.
2.2.2.5 PIR1 Regis ter
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits a re c le ar pri or to en ab li ng an interrupt .
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a writ e operatio n has taken place (must be cleared in softwar e)
0 = No read or w rit e ha s occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not compl ete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP inter rupt condition has occur red, and must be cleared in so ftware befor e
returning f ro m th e In te rrupt Service R ou t in e. The condition s th at w ill set this bi t are:
SPI
A transmi ss i on/ r eception ha s take n pl ac e.
I2 C Slave
A transmi ss i on/ r eception ha s take n pl ac e.
I2 C Master
A transmi ss i on/ r eception ha s take n pl ac e.
The initiated START condition was completed by the SSP mod ule.
The initiated STOP condition was comp leted by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system ).
0 = No SSP interrup t condition has oc curred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Captur e M ode
1 = A TMR1 re gi st er capture occ ur red (must be cl e a r ed in so ftwar e)
0 = No TMR1 register capt ur e occurred
Compare Mode
1 = A TMR1 re gi st er compare match occur re d (m u st be cl eared in softw ar e)
0 = No TMR1 registe r compare match occurred
PWM Mode
Unus ed i n thi s m ode
bit 1 TMR2IF: TMR2 to PR2 M atch Interrup t Flag bi t
1 = TMR2 to PR2 m atch occurred (m ust be c le ar ed i n software)
0 = No TMR2 to PR2 match oc cu rr ed
bit 0 TMR1IF: TMR1 Overflow Interrupt F lag bit
1 = TMR1 regi st er overflowed (must be cleared i n software)
0 = TMR1 regi st er did not over f lo w
Note 1: PSPIF is reserved on 28-pi n dev i ces ; a lwa ys maintain this bit cle ar.
Legend:
R = Readable bit W = Writable bit U = Unimpleme nt ed bit, read as ‘0’
- n = Value at PO R reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 23
PIC16F7X
2.2.2.6 PIE2 Register
The PIE2 regi ster cont ains the indivi dual enable b its for
the CCP2 peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE
bit 7 bit 0
bit 7-1 Unimplemented: Read as ’0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 24 Advance Information 2000 Microchip Technology Inc.
2.2.2.7 PIR2 Regis ter
The PIR2 register contains the flag bits for the CCP2
interrupt.
.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interru pt fl ag bits are set whe n an in terru pt
conditi on occ urs , re gardless of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture Mo de
1 = A TMR1 regi ster capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 regi ster compare match occu rred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 25
PIC16F7X
2.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is un known on P OR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown- out has occurre d. The BOR st atus
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = B it i s set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 26 Advance Information 2000 Microchip Technology Inc.
2.3 PCL and PCLATH
The progra m counter (PC) is 13-bits wide. Th e low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bit s of the
PC will b e clea red. Fig ure 2-5 sho ws the tw o sit uation s
for the l oading of th e PC. The up per ex ample in the fi g-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lowe r ex am pl e i n th e fi g-
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The PIC 16F7X fami ly has a n 8-level deep x 1 3-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writ able. The PC i s PUSHed on to the st ack
when a CALL instruction is executed, or an interrupt
causes a bran ch . The st ac k is POPed in the ev en t of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The st ack operates as a circular buf fer . This means that
after the st ack h as be en PU SHed ei ght ti mes, the nin th
push ov erwrit es the v alue tha t was stor ed fro m the first
push. The tenth push overw ri tes the se cond push (and
so on).
2.4 Program Memory Paging
PIC16F7 X device s are cap abl e of add ressing a co ntin-
uous 8K word block of program memory . The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doi ng a CALL or GOTO instruction, the user mus t
ensure that the page select bits are programmed so
that the de sired prog ram memory p age is a ddressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not require d for the return instructions (whi ch POPs the
address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 o f the prog ram memory. This exa mple assu mes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
;in page 0 (000h-7FFh)
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instruc tions or the v ectoring to an interrupt
address.
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLS or GOTOS.
2000 Microchip Technology Inc. Advance Information DS30325A-page 27
PIC16F7X
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is no t a physica l register. Addressin g
the INDF register will cause indirect addressing.
Indirect addressing is poss ible by using the INDF reg-
ister. Any instruction using the INDF register actually
acces ses the register pointed to by the File Sele ct Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirec tly res ul t s in a no-operation (although statu s bits
may be affec ted). An ef fectiv e 9-bit add ress is o btaine d
by conc atenat ing the 8 -bit F SR regi ster and the IRP bit
(STATUS<7>), as show n in Figure 2-6.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
CONTINUE
: ;yes continue
FIGURE 2-6: DIRE CT/INDI RECT ADDRESSING
Note 1: For register file map detail see Figure 2-3.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16F7X
DS30325A-page 28 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 29
PIC16F7X
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O ports ma y b e f oun d in the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bi t (=1) will m ake t he co rrespon ding POR TA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the correspon ding POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t will write to the po rt latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, the va lue is modified and then written to the port
data l atch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger input and an open d rain o utput .
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, ev en when they are being us ed as ana lo g inp ut s .
The user mu st ensure the bit s in the TRISA regi ster are
maintained set, when using them as analog inputs.
EXAMPLE 3- 1: INITIALIZING PORTA
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 clock input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note 1: I/O pin has protection di odes to VSS only.
PIC16F7X
DS30325A-page 30 Advance Information 2000 Microchip Technology Inc.
TABLE 3-1: PORTA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input.
RA1/AN1 bit1 TTL Input/output or analog input.
RA2/AN2 bit2 TTL Input/output or analog input.
RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF.
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alu e on:
POR,
BOR
V alue on all
other
RESETS
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — POR TA Data Direc tio n Regis ter --11 1111 --11 1111
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
2000 Microchip Technology Inc. Advance Information DS30325A-page 31
PIC16F7X
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bi t (=1) will m ake the c orresponding POR TB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the co rresponding POR TB pin an output (i.e., put
the contents of the output latch on the selected pin).
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of POR TB’s pi ns, RB7:RB4, hav e an interrupt-o n-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interr upt in the foll owin g man ner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/IN T is an ext ernal i nterrupt input pin a nd is confi g-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 12.10.1.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pi ns
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RB7:RB6 in Serial Programming mode Q3
Q1
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
PIC16F7X
DS30325A-page 32 Advance Information 2000 Microchip Technology Inc.
TABLE 3-3: PORTB FUNCTIONS
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external inte rrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt-o n-change) . Inter nal soft ware pro grammable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt-o n-change) . Inter nal soft ware pro grammable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial program ming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial program ming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
06h, 106h P O RTB RB7 RB6 RB5 RB4 RB3 RB 2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRI SB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION _REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
2000 Microchip Technology Inc. Advance Information DS30325A-page 33
PIC16F7X
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corres ponding POR TC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make th e corresponding PO RTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORT C is multip lexed with s everal periphe ral function s
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bit s fo r each POR T C pin. Som e
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
dest ination shoul d be avoided. The user s hould refer to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
TABLE 3-5: PORTC FUNCTIONS
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Port/Peripheral Select(2)
Data Bus
WR
Port
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
Port
Peripheral
OE(3)
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select sign al selects between port dat a
and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
I/O
pin(1)
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Comp are1 ou tput/PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or
Synchrono us D at a.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
PIC16F7X
DS30325A-page 34 Advance Information 2000 Microchip Technology Inc.
3.4 PORTD and TRISD Registers
This section is not applicable to the PIC16F73 or
PIC16F76.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually confi gureable as an in put or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mod e, the input buffe rs
are TTL.
FIGURE 3-6: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
TABLE 3-7: PORTD FUNCTIONS
TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to Vdd and Vss.
QD
CK
QD
CK
EN
QD
EN
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output po rt pin or parallel slave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output po rt pin or parallel slave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output po rt pin or parallel slave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output po rt pin or parallel slave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output po rt pin or parallel slave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output po rt pin or parallel slave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output po rt pin or parallel slave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output po rt pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Va lue on a ll
other
RESETS
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
2000 Microchip Technology Inc. Advance Information DS30325A-page 35
PIC16F7X
3.5 PORTE and TRISE Register
This section is not applicable to the PIC16F73 or
PIC16F76.
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/C S/ A N7, w hic h are indi vi dua lly configureabl e
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMOD E (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
input s). Ensure ADCO N1 is configure d for digital I/O. In
this mode, the input buffers are TTL.
Register 3-1 shows the TRISE register , which also con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
select ed as an anal og input, thes e pins will re ad as ’0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 3-7: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs and read as ‘0’.
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to Vdd and Vss.
PIC16F7X
DS30325A-page 36 Advance Information 2000 Microchip Technology Inc.
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE —bit2 bit1 bit0
bit 7 bit 0
bit 7 Parallel Slave Port Status/Control Bits
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3 Unimplemented: Read as '0'
bit 2 PORTE Data Direction Bits
Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 37
PIC16F7X
TABLE 3-9: PORTE FUNCTIONS
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) Input /output port pin or read co ntrol input in Parall el Slave Port mode or
analog input:
RD
1 =Idle
0 = Read op erat ion . C on ten t s of PO R TD regist er output to PORT D I/O
pins (if chip selected).
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 =Idle
0 =Write operation. Value of PORTD I/O pins latched into PORTD
register (if chip selected).
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not selec t ed
0 = Device is selec t ed
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Dir ection Bits 0000 -111 0000 -111
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
PIC16F7X
DS30325A-page 38 Advance Information 2000 Microchip Technology Inc.
3.6 Parallel Slave Port
The Parallel Slave Port is not implemented on the
PIC16F73 or PIC16F76.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4> ) i s se t. I n Sl av e mode, it is asy nc hro nou sl y
readable and writa ble by the extern al world throu gh RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directl y int erfa ce to an 8-bi t mic rop roc es sor dat a
bus. The extern al mic roproc essor can read or w rite th e
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG3:PCFG0 (ADCON1<3:0>) must be
set to configure pins RE2:RE0 as digital I/O.
There are actually two 8-bit latches. One for data out-
put and one for data input. The user writes 8-bit data to
the POR TD da ta la tch and reads dat a from the port pin
latch (note that they have the same address). In this
mode, th e TRISD regi ster is ig nored, sin ce the external
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) statu s fl ag bi t (TR ISE<7 >) is set on the Q 4 cl oc k
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-9). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can onl y be cleared by readi ng the PO RTD input latc h.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buff er.
A read from t he PSP occurs when both the CS and R D
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-10) indicating that the PORTD latch is
waitin g to be read by the ext ernal bus. Whe n eithe r the
CS or RD pin be co me s hi gh ( lev el trigg ere d), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF an d O BF b it s are hel d
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the us er in fi rmware and th e
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7> ).
FIGURE 3-8: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
Data Bus
WR
Port
RD
RDx
QD
CK
EN
QD
EN
Port
pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR 1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
2000 Microchip Technology Inc. Advance Information DS30325A-page 39
PIC16F7X
FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 3-10: PAR ALLEL SLAVE PORT READ WAVEFORMS
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
08h PORTD Port data latch when written: Port pins when r ead xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —P ORTE Data Di re ction Bi ts 0000 -111 0000 -111
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
PIC16F7X
DS30325A-page 40 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 41
PIC16F7X
4.0 READING PROGRAM MEMORY
The FLASH Program Memory is readable during nor-
mal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calib ration param eters, serial numb ers, packe d 7-bit
ASCII, etc. Exe cuting a program m emory loc ation co n-
taining data that forms an invalid instruction results in
a NOP.
There are five SFRs used to read the program and
memory. These registers are:
•PMCON1
•PMDATA
•PMDATH
•PMADR
•PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading ca libration tables.
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two byte word,
which holds the 13-bit address of the FLASH location
being accessed. These devices can have up to 8K
words of program FLASH, with an address range from
0h to 3FFFh. The unused upper bits in both the
PMDATH and PMADRH registers are not implemented
and read as “0’s”.
4.1 PMADR
The addres s registers can addres s up to a maximum of
8K words of program FLASH.
When se lecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is writte n to the PMADR register. The upper
MSbits of PMADRH must always be clear.
4.2 PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cl eare d, onl y set, in softw a re. It is cl eare d in
hardware at the completion of the read operation.
REGISTER 4-1: PMCON1 REGISTER (ADDRESS 18Ch)
R-1 U-0 U-0 U-0 U-x U-0 U-0 R/S-0
— — — — — — — RD
bit 7 bit 0
bit 7 Reserved: Read as ‘1’
bit 6-1 Unimplemented: Read as '0'
bit 0 RD: Re ad Control bit
1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0 = Does not initiate a FLASH read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 42 Advance Information 2000 Microchip Technology Inc.
4.3 Rea ding the FLASH Progr am Memory
A program me mory location may be read by wri ting two
bytes of the address to the PMADR and PMADRH reg-
isters and then setting control bit RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
data is available in the PMDATA and PMDATH regis-
ters after the second NOP instruction. Therefore, it can
be read as two bytes in the following instructions. The
PMDATA and PMDATH registers will hold this value
until another read operation.
EXAMPLE 4-1: FLASH PROGRAM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVF ADDRH, W ;
MOVWF PMADRH ; MSByte of Program Address to read
MOVF ADDRL, W ;
MOVWF PMADR ; LSByte of Program Address to read
BSF STATUS, RP0 ; Bank 3
Required BSF PMCON1, RD ; EEPROM Read
Sequence
NOP ; memory is read in the next two cycles after BSF PMCON1,RD
NOP ;
BCF STATUS, RP0 ; Bank 2
MOVF PMDATA, W ; W = LSByte of Program PMDATA
MOVF PMDATH, W ; W = MSByte of Program PMDATA
2000 Microchip Technology Inc. Advance Information DS30325A-page 43
PIC16F7X
4.4 Operation During Code Protect
FLASH program memory has its own code protect
mechanism. External Read and Write operations are
disabled if this mechanism is enabled.
The microcontroller can read and execute instructions
out of the int ernal FLASH program memo ry, regardless
of the state of the code protect configuration bits.
TABLE 4-1: REGISTERS ASSOCIATED WITH PROGRAM FLASH
AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
10Dh PMADR Address Regis ter Low Byte xxxx xxxx uuuu uuuu
10Fh PMADRH ———Address Register High Byte xxxx xxxx uuuu uuuu
10Ch PMDATA Data Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH — — Data Register High Byte xxxx xxxx uuuu uuuu
18Ch PMCON1 —(1) ——————RD 1--- ---0 1--- ---0
Legend: x = unknow n, u = unchan ged, r = reserv ed, - = unimplemented read as ’0’. Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
PIC16F7X
DS30325A-page 44 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 45
PIC16F7X
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
•8-bit ti mer/counter
•Readable and writable
•8-bit software programmable prescaler
•Internal or external clock select
•Interrupt on overflow from FFh to 00h
•Edge select for external clock
Figure 5-1 i s a block diagram of th e Ti mer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery ins truction cycle (with ou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The prescaler is mutually exclusively shared between
the Timer0 modu le and t he Watchdo g T im er. The pres-
caler i s not readabl e or wr it able. Sectio n 5.3 det ails the
operation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the T imer0 mo dule Interrupt Ser-
vice Routine, before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (= FOSC/4)
SYNC
2
Cycles TMR 0 r e g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set Flag bit T0IF
on Overflow
8
PSA
T0CS
PRESCALER
PIC16F7X
DS30325A-page 46 Advance Information 2000 Microchip Technology Inc.
5.2 Using Timer0 with an External Clock
When no pr escal er is used, t he ex tern al clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI, with the internal phase clocks, is accom-
plishe d by sampling the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
nec es sa ry f or T 0 C KI t o be hig h f or at le as t 2Tos c (a nd
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3 Prescaler
There i s only one pres caler a vailable , whic h is mutu ally
exclus ively shar ed between th e T imer0 mod ule and the
Watchdog Timer. A prescaler assignment for the
T i mer0 m odule m eans that t here i s no presc aler fo r the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler . When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0 when the prescaler is
assign ed to T imer0 , will clear th e prescaler
count but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clo c k (CLKOU T)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = B it i s set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
Note: To avoid an unintended device RESET, the instruction sequence shown in the
PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed
when ch anging the pres caler assign ment from T imer0 to the WDT. This sequen ce must
be followed even if the WDT is disabled.
2000 Microchip Technology Inc. Advance Information DS30325A-page 47
PIC16F7X
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
01h,101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
PIC16F7X
DS30325A-page 48 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 49
PIC16F7X
6.0 TIMER1 MODULE
The Timer1 module is a 16 -bi t tim er/c ou nter cons is tin g
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and roll s over to 0000h. The TMR1 Interrupt, if enable d,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1 IE (PIE1<0> ).
Timer1 can operate in one of two modes:
•As a timer
•As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external cloc k input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR 1 ON (T1C O N<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off (The oscill ator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Sync hro ni zat ion Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer 1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 50 Advance Information 2000 Microchip Technology Inc.
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
6.2 Timer1 Counter Opera tio n
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. Af ter Timer1
is enab led in Coun ter mode, the module must fi rst have
a falling edge before the counter begins to increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
6.3 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mod e, the timer incr ement s on every risin g edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCE N is se t, or on pi n RC0/ T1OSO/T 1CKI , when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripp le counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The
prescaler however, will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Q Clock
T1OSCEN
Enable
Oscillator(1)
Fosc/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
Set Flag bit
TMR1IF on
Overflow TMR1
(2)
2000 Microchip Technology Inc. Advance Information DS30325A-page 51
PIC16F7X
6.4 Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYN C (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read /write the timer (Section 6.4.1).
In Asynchronous Counter mode, Timer1 can not be
used as a time base for capture or compare operati ons.
6.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an ex ternal as ynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user shoul d keep i n mind that r eadi ng the 16-b it time r
in two 8-bit values itself, poses certain problems since
the timer may overflow between the reads.
For write s, it is re commend ed that the us er simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. Exam-
ples 1 2-2 an d 12-3 in the PICm icr o™ M id-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
6.5 Timer1 Oscillator
A crystal oscillator circu it is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t prov id e a so ftware time delay to en su re
proper oscillator start-up.
T ABLE 6-1: CAP ACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6 Resetting Ti mer1 using a CCP T rigger
Output
If the CCP 1 or CCP2 mo dule is config ured in C ompa re
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
T imer 1 must be co nfigured fo r either T i mer or Synch ro-
nized C ou nter m od e, to t a ke adv antage of this featur e.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the even t that a write to T imer1 coi ncides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of ope ration, the CCPRxH:C CPRx L regis -
ter pair effectively becomes the period register for
Timer1.
6.7 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H an d TMR1 L regist ers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 spe cial ev ent trig gers .
T1CON re gister is rese t to 00h on a Pow er-on Rese t or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
6.8 Timer1 Presc aler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Osc Type Fre q C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacita nce increases t he stability of
the oscillator , but also increases the start-up
time.
2: Since eac h reso nato r/crystal ha s its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0 >).
PIC16F7X
DS30325A-page 52 Advance Information 2000 Microchip Technology Inc.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer 1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 53
PIC16F7X
7.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
post scaler . It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be sh ut off by clearing con t rol bit T MR2O N
(T2CON<2>) to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
7.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
•a write to the TMR2 register
•a write to the T2CON register
•any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optiona lly uses it to generate shift
clock.
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets Fla g
TMR2 reg
Output(1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
to
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Sele ct bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Re adable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at PO R reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 54 Advance Information 2000 Microchip Technology Inc.
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TM R2 Timer2 Mo dul e ’s Register 0000 0000 0000 0000
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Peri o d Regi ster 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 55
PIC16F7X
8.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
•16-bit Capture re gister
•16-bit Compare register
•PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operatio n, with th e except ion being the operation of the
specia l event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is describe d with respec t to CCP1. CCP2 opera tes the
same as CCP1, except where noted.
8.1 CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
8.2 CCP2 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) a nd in Ap plicatio n Note 594 , “Using
the CCP Modules” (DS00594).
TABLE 8-1: CCP MODE - TIMER
RESOURCES REQUIRED
TABLE 8-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base.
Capture Compare The compare should be configured for the special event trigger, which clears TMR1.
Compare Compare The compare(s) should be configured for the special event trigger , which clears TMR1.
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM Capture None.
PWM Compare None.
PIC16F7X
DS30325A-page 56 Advance Information 2000 Microchip Technology Inc.
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 CCPxX:CCPxY: PWM Least Sign ificant bit s
Capture Mode:
Unused
Compare Mode:
Unused
PWM Mode:
These bi ts are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate so ftware interrupt on match (CCPxIF bit is set,
CCPx pin is unaffected)
1011 = Compare mode, trig ger sp ecial event (C CPxIF bit is set, CCPx pin i s unaffected);
CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion
(if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 57
PIC16F7X
8.3 Capt ure Mo de
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of th e TMR1 r egister wh en an event occurs
on pin RC2/CCP1. An event is define d as one of the fol-
lowing and is configured by CCPxCON<3:0>:
•Every falling edge
•Every rising edge
•Every 4th rising edge
•Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made , the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
8.3.1 CCP PIN CONFIGURATION
In Capt ure m od e, th e R C2/CCP1 pin sh oul d be config-
ured as an inpu t by setti ng the TRISC<2> bit.
FIGURE 8-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
8.3.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.3.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in ope rati ng mod e.
8.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP modu le is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not gen era te the “false” interrupt.
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture co ndition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’sCCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
PIC16F7X
DS30325A-page 58 Advance Information 2000 Microchip Technology Inc.
8.4 Compare Mode
In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is
constantly compared against the TMR1 register pair
value. Whe n a match occu rs, the RC2/CCP1 pin is:
•Driven high
•Driven low
•Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
8.4.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clea ring the TRISC<2> bit.
8.4.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.4.3 SOFTWARE INTERRUPT MODE
When Generate Sof tware Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.4.4 SPECIAL EVENT TRIGGER
In this mod e, an intern al ha rdwar e trigg er is gene rated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 re gister to
effe ctively be a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 regis ter pair and starts an A/D conversion (if the
A/D module is en abled).
8.5 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a ste p-by-step proc edure on how to set up the CCP
module for PWM operation, see Section 8.5.3.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: Clearing the CCP1CON register will force
the RC2/CCP1 co mpare outp ut latch to the
default low level. This is not the PORTC
I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0 >).
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Time r,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
2000 Microchip Technology Inc. Advance Information DS30325A-page 59
PIC16F7X
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4: PWM OUTPUT
8.5.1 PWM PERIOD
The PWM p eriod i s spec ified by writi ng to th e PR2 re g-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on t he next inc rement cycle:
•TMR2 is cl eare d
•The CCP1 pin is set (exception: if PWM duty
cycl e = 0%, the CCP1 pin will not be set)
•The PWM dut y cycle is latched from CCPR1L i nto
CCPR1H
8.5.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1 L c ontai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescal er, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
8.5.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register .
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale v alue and enable T imer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
Note: The Timer2 post s caler (s ee Se cti on 8.3) i s
not used in the determination of the PWM
frequenc y . T he posts caler could b e used to
have a servo update rate at a different fre-
quency than the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
TMR2
RESET TMR2
RESET
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )bits
=
Resolution
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
PIC16F7X
DS30325A-page 60 Advance Information 2000 Microchip Technology Inc.
TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Da t a Direc tion Register 1111 1111 1111 1111
0Eh TMR1L Holding registe r for the Leas t Sign ificant Byte of th e 16- bit TMR 1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Signif icant By te of the 16- bit TMR 1 regis ter xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Comp are /PWM register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Comp are/PWM r egister1 ( MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Comp are/PWM regis ter2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
Addres s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Dat a Dir ect ion Regi ster 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer 2 mod ule’s period register 1111 1111 1111 1111
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Comp ar e/PWM registe r1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Co mp are/PWM r egiste r1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Cap ture/Co mp are/PWM regis te r2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compar e/PWM registe r2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 61
PIC16F7X
9.0 SYNCHRONOUS SERIAL PORT
(SSP) MODULE
9.1 SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play d riv ers, A/D converters, et c. The SSP module can
operate in one of two modes:
•Serial Peripheral Interface (SPI)
•Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
tion on the SSP module can be found in the PICmicro™
Mid-Range MCU Family Reference Manual
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I2C Multi-Master Environment.”
9.2 SPI Mode
This section contains register definitions and opera-
tional characteristics of the SPI module. Additional
information on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual (DS33023A).
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
•Serial Data Out (SDO) RC5/SDO
•Serial Data In (SDI) RC4/SDI/SDA
•Serial Clock (SCK) RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
•Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
•Master mode (SCK is the clo c k output)
•Slave mode (SCK is the cloc k input)
•Clock Polarity (Idle state of SCK)
•Clock edge (output data on rising/falling edge of
SCK)
•Clock Rate (Master mode only)
•Slave Select mode (Slave mode only)
PIC16F7X
DS30325A-page 62 Advance Information 2000 Microchip Technology Inc.
REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT ST ATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: SPI Data Input Sample Phase
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire®)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2 C mode:
This bit must be maintained cl ear
bit 6 CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode:
CKP = 0
1 = Data transmitted on rising edge of SCK (Microwire® alternate)
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmi tted on falling edge of SCK (Microwire® default)
0 = Data transmi tted on rising edge of SCK
I2 C mode:
This bit must be maintained cl ear
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: STOP bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the START bit is detected last.
SSPEN is cleared.
1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0 = STOP bit was not detected last
bit 3 S: START bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last.
SSPEN is cleared.
1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0 = START bit was not detected last
bit 2 R/W: Read/Write bit Information (I2C mode onl y )
This bit hold s the R/W bi t informat ion follo wing the las t addres s match . This bit is only valid from
the address match to the next START bit, STOP bit, or ACK bit.
1 = Read
0 = Write
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 63
PIC16F7X
REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow c a n only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
is a "don’t care" in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microw ire® default)
0 = Idle state for clock is a low level (Microwire® alternate)
In I2 C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bi t addres s
0111 = I2C Slave mode, 10-b it addre ss
1011 = I2C firmware c ontrolled Master mode (slave idle)
1110 = I2C Slave mo de, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 64 Advance Information 2000 Microchip Technology Inc.
FIGURE 9-1: SSP BLOCK DIAGRAM
(SPI MODE) To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. Th is config ures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
•SDI must have TRISC<4> set
•SDO must have TRISC<5> cleared
•SCK (Master mode) must have TRISC<3>
cleared
•SCK (Slave mode) must have TRISC<3> set
•SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
.
Read Write
Internal
Data Bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Note 1: When the SPI is in Slave mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control m ust be
enabled.
2000 Microchip Technology Inc. Advance Information DS30325A-page 65
PIC16F7X
FIGURE 9-2: SPI MODE TIMING, MASTER MODE
FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0,
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDI (SMP = 1)
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
bit7
bit7 bit0
bit0
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS (optional)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS
PIC16F7X
DS30325A-page 66 Advance Information 2000 Microchip Technology Inc.
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh.
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 67
PIC16F7X
9.3 SSP I2 C Operatio n
The SSP module in I2C mode, fully imp lements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facil-
itate firmware implementations of the master functions.
The SSP module implements the st andard mode speci-
fications as well as 7-bit and 10-bit addres sing.
T wo pins are used for da ta transfer . These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/S DA pin, which i s the data ( SDA). T he user mu st
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP mod ule fun ctions a re enabl ed by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 9-5: SSP BLOCK DIAGRAM
(I2C MODE)
The SSP module has five registers for I2C operation.
These are the:
•SSP Control Register (SSPCON)
•SSP Status Register (SSPSTAT)
•Serial Receive/Transmit Buffer (SSPBUF)
•SSP Shift Register (SSPSR) - N ot di rec tl y ac c essi ble
•SSP Address Register (SSPADD)
The SSPCON register al lows control of the I 2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I2C Slave mode (7-bit address)
•I2C Slave mode (10-bit address)
•I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
•I2C Slave mo de (10-bit address) , with START and
STOP bit interrupts enabled to support firmware
Master mode
•I2C START and STOP bit interrupts enabled to
support firmware Master mode, Slave is idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provide d external ly to the SCL and SD A pins for proper
operation of the I2C module.
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023A).
9.3.1 SLAVE MODE
In Slave mod e, the SCL and SDA pin s must be config-
ured as input s (TRISC<4 :3> set). The SSP module will
override the input state with the output data when
required (slave -tran smit ter).
When an a ddress is matc he d, or the d ata transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF reg is ter wi th th e re ceive d valu e
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSP CON<6>) was s et
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user so ft ware d id no t pr operly c lear th e ove rflow cond i-
tion. Flag bit BF is cleare d by reading the SSPBUF re g-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per ope rati on. The high and low ti me s o f th e
I2C specification, as well as the requirements of the
SSP module, are shown in timing pa rameter #100 and
parameter #101.
Read Write
SSPSR reg
Match Detect
SSPADD reg
START and
STOP b i t D e tect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, RESET
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/ LSb
SDA
PIC16F7X
DS30325A-page 68 Advance Information 2000 Microchip Technology Inc.
9.3.1.1 Addressing
Once the SSP module has been enabled, it waits for a
START conditi on to occu r. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addres ses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is genera ted if e nabled ) - on the fallin g
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this i s a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the s la ve d ev ice w ill rece iv e the sec-
ond address byte. For a 10-bit address, the first byte
would e qua l ‘1111 0 A9 A8 0’, whe re A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5. Upd ate t he SSPADD register wi th the firs t (hig h)
byte of a ddre ss , if match releases SC L li ne, thi s
will clea r bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received SSPSR → SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2000 Microchip Technology Inc. Advance Information DS30325A-page 69
PIC16F7X
9.3.1.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dress is loa ded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or b it SSPOV (SSPCON<6>) is set. This is an error
conditi on due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. F lag bit SSPIF (PIR1<3>) mu st be cle ared in so ft-
ware. The SSPSTAT register is used to determine the
status of the by te.
FIGURE 9-6: I2C W AVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
PIC16F7X
DS30325A-page 70 Advance Information 2000 Microchip Technology Inc.
9.3.1.3 Transmission
When the R/W bit o f the in coming add ress byt e is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter . The n, pin RC3/SCK/SCL shou ld be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL p in p rior t o as se rting another clock pu ls e. Th e
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a s lav e-t rans mi tte r, the ACK puls e from the mast er-
receiver is latched on the rising edge of the ni nth SCL
input pulse. If the SDA line was high (not ACK), then
the dat a tran sfer is com plete. When th e ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) an d the slave then moni tors for another occur-
rence of th e START bit. If the SDA l ine was l ow (AC K),
the transm it data must be load ed into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR 1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/W = 1Receiving Address
123456789 123456789 P
Cleared in softwa re
SSPBUF is written in software From SSP Interru pt
Service Routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
2000 Microchip Technology Inc. Advance Information DS30325A-page 71
PIC16F7X
9.3.2 MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleare d from a RESET or when th e
SSP module is dis abled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I2C bus may be taken when the P
bit is set, o r the bus is id le and both the S and P bits are
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by cleari ng the c orresp onding TRISC<4 :3> bit(s ).
The output level is always low, irrespective of the
value(s ) i n PO R T C <4:3 >. So w h en tran sm itti ng da t a, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit mus t hav e th e TRISC <4> bit c lea red (o ut-
put). The same scenario is true for the SCL line with the
TRISC<3> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I2C modu le.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
•START condition
•STOP condition
•Data tran sfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
Slave ac tive. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
9.3.3 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions, allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idl e an d
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
•Address Transfer
•Data Transfer
When the slav e log ic is enab led, th e sla ve co ntinue s to
receive . If arbitrati on was l ost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Ser ial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
93h S SPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP(2) CKE(2) D/A PSR/WUA BF 0000 0000 0000 0000
87h TRISC PO RTC Data Direction register 1111 1111 1111 1111
Legend: x = unknow n, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I2C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
2: Maintain these bits clear in I2C mode.
PIC16F7X
DS30325A-page 72 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 73
PIC16F7X
10.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O mo dules . (USA RT is als o kno wn as a S erial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with periph eral devices, such as CRT ter-
minals and perso nal comp uters, or it can be confi gured
as a half duplex syn chr ono us s y ste m that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
•Asynchronous (full duplex)
•Synchronous - Master (half duplex)
•Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC —BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (C lock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enab le bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as '0'
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 74 Advance Information 2000 Microchip Technology Inc.
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x
SPEN RX9 SREN CREN —FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Seri al Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care
bit 4 CREN: Cont inuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 Unimplemented: Read as '0'
bit 2 FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
Can be parity bit (parity to be calculated by firmware)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = B it i s set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 75
PIC16F7X
10.1 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for diff eren t US ART modes which on ly a ppl y
in Master mode (internal clock).
Given the desired b aud rate an d Fosc, the n earest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1 )) eq uat ion c an reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1 SAMPLING
The dat a on the RC7/RX/D T pin is sa mpled three time s
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 10-1: BAUD RATE FORMULA
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1
(Asynchron ous ) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = F OSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
99h SPBRG Baud Rate Ge nera tor R egi ste r 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
PIC16F7X
DS30325A-page 76 Advance Information 2000 Microchip Technology Inc.
-
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL)
0.3 - - - - - - - - -
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.5 31 1.7 2 1 5 19.231 0.1 6 12 1 9.5 31 1.7 2 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz F OSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
0.3 0.300 0 207 0.301 0.33 185
1.2 1.202 0.17 51 1.216 1.33 46
2.4 2.404 0.17 25 2.432 1.33 22
9.6 8.929 6.99 6 9.322 2.90 5
19.2 20.833 8.51 2 18.643 2.90 2
28.8 31.250 8.51 1 - - -
33.6 - - - - - -
57.6 62.500 8.51 0 55.930 2.90 0
HIGH 0.244 - 255 0.218 - 255
LOW 62.500 - 0 55.930 - 0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD %
ERROR
SPBRG
VALUE
(DECIMAL)
0.3---------
1.2---------
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
VALUE
(DECIMAL) KBAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
0.3 - - - - - -
1.2 1.202 0.17 207 1.203 0.25 185
2.4 2.404 0.17 103 2.406 0.25 92
9.6 9.615 0.16 25 9.727 1.32 22
19.2 19.231 0.16 12 18.643 2.90 11
28.8 27.798 3.55 8 27.965 2.90 7
33.6 35.714 6.29 6 31.960 4.88 6
57.6 62.500 8.51 3 55.930 2.90 3
HIGH 0.977 - 255 0.874 - 255
LOW 250.000 - 0 273.722 - 0
2000 Microchip Technology Inc. Advance Information DS30325A-page 77
PIC16F7X
10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to de rive st and ard baud rate freque n-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same d at a for ma t an d baud rate. The bau d ra te gen er-
ator produces a clock either x16 or x64 of the bit shift
rate, depe nding on bit BRGH (TXSTA<2>). Parity is not
supporte d by the hard ware, but can be imple mente d in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
•Baud Rate Ge nera tor
•Sampling Circuit
•Asynchronous Transmitter
•Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. T he hea rt of t he trans mitte r is the t ransmit
(serial) shi ft register (TSR). The shif t register obta ins its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), th e T XREG r egist er is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enab le bi t TXI E and ca nno t be cl eare d in soft -
ware. It will re set only wh en ne w dat a is loa ded i nto the
TXREG register . While flag bit TXIF indicates the st atus
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a re ad onl y bit, which i s se t whe n the TSR registe r i s
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d a nd will reset th e
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resu lt in an immediate tra nsfer of the dat a to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is s et when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• • •
PIC16F7X
DS30325A-page 78 Advance Information 2000 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Transmission:
1. Initi ali ze th e SPBRG re gis te r for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 10.1)
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set en able bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 B i t 1 Bi t 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Word 1 STOP Bit
Word 1
Transmit Shi ft R e g
START Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Sh i ft C lock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
START Bit STOP Bit START Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
2000 Microchip Technology Inc. Advance Information DS30325A-page 79
PIC16F7X
10.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on th e RC 7/RX/D T p in an d dri ve s
the data recovery block. The data recovery block is
actuall y a h igh sp ee d s hifter operating at x16 times th e
baud rate , whereas the main receive serial shif ter oper-
ates at the bit rate, or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setti ng bit CRE N (RCSTA<4>).
The heart of the receive r is the receive (s erial) shif t reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is tra nsferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR 1<5 >) i s se t. Th e ac tua l in ter ru pt c an be enab led /
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hard ware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still f ull, the overrun error bit OE RR (RCSTA<1>) wil l be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. O verrun bit OERR h as to be cle ared in sof twar e.
This is done by resetting the receive logic (CREN is
cleared and then s et). If bit O ERR is s et, tran sfers from
the RSR register to the RCREG register are inhibited
and no further data will be received, therefore, it is
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as cle ar. Bit FERR and the 9th re cei ve bit a re
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values , the refo re, it is essent ial for the us er to re ad the
RCSTA register before reading RCREG register, in
order not to lose the old FERR and RX9D inform ation .
FIGURE 10-4: USA RT RECEIVE BLOCK DIAGRAM
FIGURE 10-5: ASY NCHR ONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
STOP START
(8) 710
RX9
• • •
FOSC
÷64
÷16
or
START
bit bit7/8
bit1bit0 bit7/8 bit0STOP
bit
START
bit START
bit
bit7/8 STOP
bit
RX (pin)
reg
Rcv Buffer reg
Rcv Shift
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
WORD 1
RCREG WORD 2
RCREG
STOP
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
PIC16F7X
DS30325A-page 80 Advance Information 2000 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Reception:
1. Initi ali ze th e SPBRG re gis te r for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Fl ag b it RC IF wi ll b e set when reception is com-
plete an d an interru pt will be generate d if enabl e
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bi t CREN.
10. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 81
PIC16F7X
FIGURE 10-6: USA RT RECEIVE BLOCK DIAGRAM
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
x64 B aud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE
Data Bus
8
STOP START
(8) 710
RX9
• • •
8
FOSC
÷64
÷16
or
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCRE G USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG B aud Rate Generat or Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
PIC16F7X
DS30325A-page 82 Advance Information 2000 Microchip Technology Inc.
10.3 USART Synchronous Master Mode
In Sync hronous Ma ster mode, the data is transmi tted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode ind icates t hat the pr ocessor transmit s the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. T he hea rt of the tr ansmi tter is the tr ansmit
(serial) shi ft register (TSR). The shift reg ister obta ins its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
softw are. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set o nly when ne w dat a i s loaded into the
TXREG register . While flag bit TXIF indicates the status
of th e T XR EG r egi st e r, anot h er b it T RMT (T XS TA< 1> )
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
availa ble to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first dat a bit will be shif ted out on the next avail able
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-7). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-8). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shif t cl ock imm ediate ly. Norma lly, when transmis sion i s
first started, the TSR register is empty, so a transfer to
the TXREG reg is ter wi ll re sult in an immedia te tra ns fer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d a nd will reset th e
transmitter. The DT and CK pins will revert to hi-
impeda nce. If ei ther bit C REN or bi t SREN is set durin g
a transmis sion , the transm issi on is abor ted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the p ins. In ord er
to reset the tran sm itte r, the user has to cle ar bi t TXEN.
If bit SREN is set (t o interrupt an on-goin g trans mission
and r eceive a single wo rd), then af ter the single w ord is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-
imp edance r ecei ve mode to tran smit an d start dr iving .
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initi ali ze the SPBRG re gister for the appropria te
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loadin g data to the TXREG
register.
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
2000 Microchip Technology Inc. Advance Information DS30325A-page 83
PIC16F7X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-7: SY NCHRONOUS TRANSMISS ION
FIGURE 10-8: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR,
BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
bit 0 bit 1 bit 7
Word 1
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Inte rru pt Flag )
TRMT
TXEN bit ’1’ ’1’
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
Word 2
TRMT bit
Write Word1 Write Word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
PIC16F7X
DS30325A-page 84 Advance Information 2000 Microchip Technology Inc.
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>),
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bi t CREN is s et, the reception is con-
tinuous until CRE N is cleared. If both bits are set, CR EN
takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset w hen the RCREG reg-
ister has been read an d is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin shift-
ing into the RSR register. On the clocking of the last bit
of the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) is set. The word in
the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essentia l to clear bit OE RR if it is set.
The ninth receive bit is buffered the same way as the
receive data. Reading the RCREG regist er will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCST A register before reading RCREG,
in order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initi ali ze the SPBRG re gister for the appropria te
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous rece ption set bit CREN.
7. In terrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
2000 Microchip Technology Inc. Advance Information DS30325A-page 85
PIC16F7X
FIGURE 10-9: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write t o
bit SREN
SREN b i t
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
Q3Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4Q2 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1Q2 Q3Q4Q1Q2 Q3Q4 Q1Q2Q3 Q4
’0’
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
’0’
Q1Q2Q3Q4
PIC16F7X
DS30325A-page 86 Advance Information 2000 Microchip Technology Inc.
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
mode, in the fact that the shift clock is su pplied exter-
nally at the RC6/TX/CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in SLEEP mode. Slave
mode is entered by clearing bit CSRC (TXSTA<7>).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When the first word has been shif ted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1. En able the sync hronous s lave serial p ort by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit tra nsmis si on is des ire d, then set bi t TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tar t transmission by loading dat a to the TXREG
register.
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mod e.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enabl e bit RCIE bit is set, the inte rrupt generate d
will wake the chi p from SLEEP. If the global i nter rupt i s
enabled , the program w ill br anch to the int errupt v ector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Fl ag b it RC IF wi ll b e set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
2000 Microchip Technology Inc. Advance Information DS30325A-page 87
PIC16F7X
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Address N ame Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on :
POR,
BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
PIC16F7X
DS30325A-page 88 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 89
PIC16F7X
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The 8-bit analog-to-digital (A/D) converter module has
five inputs for the PIC16F73/76 and eight for the
PIC16F74/77.
The A/D allo ws co nversion of an analog inp ut si gna l to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD), or the
voltage level on the RA3/AN3/VREF pin.
The A/D converter has a unique feature of being able
to opera te while th e device i s in SLEEP mod e. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The A/D module has three registers. These registers
are: •A/D Result Register (ADRES)
•A/D Control Register 0 (ADCON0)
•A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference),
or as digital I/O.
Addition al information on usi ng the A/D module can b e
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023) and in Application Note,
AN546.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3 CHS2:CHS0: Analog Channel Selec t bit s
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2 GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automaticall y cleared by hardware when
the A/D conversion is complete)
bit 1 Unimplemented: Read as '0'
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
DS30325A-page 90 Advance Information 2000 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7-3 Unimplemented: Read as '0'
bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits
Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
A = Analog input
D = Digital I/O
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000 AAAAAAAAVDD
001 AAAAVREF AAARA3
010 AAAAADDDV
DD
011 AAAAVREF DDDRA3
100 AADDADDDVDD
101 AADDVREF DDDRA3
11x DDDDDDDDV
DD
2000 Microchip Technology Inc. Advance Information DS30325A-page 91
PIC16F7X
The following steps should be followed for doing an
A/D conversion:
1. Co nfigure the A/D mod ule:
•Configure analog pins / voltage reference /
and digital I/O (ADCON1)
•Select A/D input channel (ADCON0)
•Select A/D conversion clock (ADCON0)
•Turn on A/D modul e (ADCON0)
2. Configure A /D i nterrupt (if desi red) :
•Clear ADIF bit
•Set ADIE bit
•Set PEIE bit
•Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
•Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
•Polling for the GO/DONE bit to be cleared
(interrupts disabled)
OR
•Waiting for the A/D interrupt
6. Read A/D result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 11-1: A/D BLOCK DIAGRAM
(Input Voltage)
VIN
VREF
(Reference
Voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100 or
001 or
011 or
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on PIC16F73/76.
11x
PIC16F7X
DS30325A-page 92 Advance Information 2000 Microchip Technology Inc.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 1 1-2. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 11-2. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log source s is 10 kΩ. After the analo g input channel is
selected (changed), the acquisition must pass before
the conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A). In general, h owever , g iven a ma x
of 10kΩ and at a temp erature of 100 °C, TACQ will be no
more than 16µsec.
FIGURE 11-2: ANALOG INPUT MODEL
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC Capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnec t resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS1:ADCS0 Max.
2TOSC 00 1.25 MHz
8TOSC 01 5 MHz
32TOSC 10 20 MHz
RC(1 , 2, 3) 11 (Note 1)
Note 1: The R C source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conv ersion clock source is only
recommended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
2000 Microchip Technology Inc. Advance Information DS30325A-page 93
PIC16F7X
11.2 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•2TOSC
•8TOSC
•32TOSC
•Internal R C oscil lat or (2-6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
11.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversio n (or th e last v alue wri tten to the AD RES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatic ally started on
the selected channel. The GO/DONE bit can then be
set to start the conversion.
11.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switchin g noise fro m the conv ersion. Whe n the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If t he A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clo ck s ource is anothe r cloc k option (not
RC), a SLEEP instruction will cause the present conver-
sion t o be aborted and the A /D m odule to b e turn ed of f,
though the ADON bit will remain set.
Turning of f the A/D pl ac es the A/D mo du le in it s low es t
current consumption state.
11.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progres s is aborted. All A/D inp ut pins are confi gured
as analog inputs.
The ADRES register will contain unknown data after a
Power-on Reset.
11.7 Use of the CCP Trigger
An A/D convers ion can be st arted by th e “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
gram med as 1011 an d th at th e A/D m od ule is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, s tarting t he A/D conversi on,
and the Timer1 counter will be reset to zero. Timer1 is
reset to autom atical ly rep eat th e A/D ac quisitio n perio d
with min imal so ftware ov erhead (mov ing the ADR ES to
the desired location). The appropriate analog input
channel must b e selecte d and the mi nimum ac quisitio n
done before the “special event trigger” sets the
GO/DONE bit (start s a conversi on).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configu r ed inp ut w i ll not af fect the conv er-
sion accuracy.
2: Analog l evels on any p in that is defined a s
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of t he devic es spe cifica-
tion.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
PIC16F7X
DS30325A-page 94 Advance Information 2000 Microchip Technology Inc.
TABLE 11-2: SUMMARY OF A/D REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 0000 00-0
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
09h PORTE(2) — — — — —RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE(2) IBF OBF IBOV PSPMODE —PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2: These registers are reserved on the PIC16F73/76.
2000 Microchip Technology Inc. Advance Information DS30325A-page 95
PIC16F7X
12.0 SPECIAL FEATURES OF THE
CPU
These d evices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protec ti on. T hes e a r e:
•Oscillato r Selection
•RESET
- Power-on Re set (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
•Interrupts
•Watchdog Timer (WDT)
•SLEEP
•Code Protection
•ID Locations
•In-Circuit Serial Programming
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is des igned to keep the part in
RESET while the power supply stabilizes. With these
two tim ers on -ch ip, mo st applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-u p from SLEEP
through ex ternal RESET, W atchdog T im er W ake-up, or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select various options.
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
12.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
PIC16F7X
DS30325A-page 96 Advance Information 2000 Microchip Technology Inc.
REGISTER 12-1: CONFIGURATION WORD
— — — — — — — BODEN —CP0 PWRTE WDTE F0SC1 F0SC0
Register: CONFIG
Address 2007h
Erased V alue: 3FFFh
bit13 bit0
bit 13-7: Unimpl emen ted : Read as ‘1’
bit 6: BODEN: Brown-out Reset Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 5: Unimplemented: Read as ‘1’
bit 4 CP0: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All memory locations code protected
bit 3: PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
2000 Microchip Technology Inc. Advance Information DS30325A-page 97
PIC16F7X
12.2 Oscillator Configurations
12.2.1 OS CILLATOR TYPES
The PIC16F7X can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•LP Low Power Crystal
•XT Crystal/Resonator
•HS High Speed Crystal/Resonator
•RC Resistor/Capacitor
12.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16F7 X oscillator design require s the use of a paral-
lel cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source to drive the OSC1/CLKIN pin
(Figure 12-2). See Table 15-1 for valid external clock
frequencies.
FIGURE 12-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 12-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
TABLE 12-1: CERAMIC RESONATORS
Note 1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
logic
PIC16F7X
RS(2)
internal
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These valu es are for design guidan ce only .
See notes at bottom of page.
Reson ators U sed :
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murat a Erie CSA 8.00 MT ± 0.5%
16.0 MHz Murata Erie CS A16. 00MX ± 0.5%
All resonators used did not have built-in capacitors.
OSC1
OSC2
Open
Clock from
ext. system PIC16F7X
PIC16F7X
DS30325A-page 98 Advance Information 2000 Microchip Technology Inc.
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR 12.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additiona l cos t sav in gs . The RC osc il lat or
frequenc y i s a fu nc tio n of the supply voltag e, th e resis-
tor (REXT) and c apacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
vari ati on d ue to to ler anc e of e xte rn al R and C c ompo -
nents used. Figure 12-3 shows how the R/C co mbina-
tion is connected to the PIC16F7X.
FIGURE 12-3: RC OSCILLATOR MODE
Osc Type Crystal
Freq Cap. Range
C1
Cap.
Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These valu es are for design guidance only .
See notes at bottom of page.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
OSC2/CLKOUT
CEXT
REXT
PIC16F7X
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
2000 Microchip Technology Inc. Advance Information DS30325A-page 99
PIC16F7X
12.3 RESET
The PIC16F7X differentiates between various kinds of
RESET:
•Power-on Reset (POR)
•MCLR Reset during normal operation
•MCLR Reset during SLEEP
•WDT Reset (during normal operation)
•WDT Wake-up (during SLEEP)
•Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any othe r RESET. Most other reg isters are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions, a s indica ted in Table 12-4. These bit s are us ed in
software to determine the nature of the RESET. See
Table 12-6 for a full description of RESET states of all
registers.
A simplifie d block diagram of the on-chip RESET ci rcuit
is sh own i n Figure 12-4 .
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
RESET
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PIC16F7X
DS30325A-page 100 Advance Information 2000 Microchip Technology Inc.
12.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pi n direct ly
(or through a resistor) to VDD. Thi s will elim ina te ex ter-
nal RC c ompon ent s usua lly ne eded to c reate a Po wer-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, fre quency, tempera ture ,...) must be met to en su re
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note, AN007, “Power-up Trouble Shoot-
ing”, (DS00007).
12.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWR T’s time de lay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
The pow er-up time dela y will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
12.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
12.7 Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(param et er #35, about 100µS), the brown- out s itu atio n
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (param eter #33, a bout 72mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess wi ll res tart wh en VDD rises above VBOR, with the
Power-up Timer Reset. The Power-up Timer is always
enabled w hen the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
12.8 Time-out Sequence
On power-up , the time-o ut seque nce is as follows: The
PWRT delay starts (if enabled) when a POR Reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bring ing MCLR high will begin execution imme-
diately . This is useful for testing purposes or to synchro-
nize more than one PIC16F7X device operating in
parallel.
Table 12-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 12-6
shows the RESET conditions for all the registers.
12.9 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see
if bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BO R bit is unpred ict able and ther efore, not
valid at any time.
Bit1 is POR (Power-on Reset S tatus bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
2000 Microchip Technology Inc. Advance Information DS30325A-page 101
PIC16F7X
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Configu rat ion Power-up Brown-out Wake-up fro m
SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms —72 ms —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out R ese t
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during no rmal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
PIC16F7X
DS30325A-page 102 Advance Information 2000 Microchip Technology Inc.
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Registe r Devices Power-on Reset,
Brown-out Reset MCLR Reset,
WDT Reset Wake-up via WDT or
Interrupt
W 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
INDF 73 74 76 77 N/A N/A N/A
TMR0 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 73747677 0000h 0000h PC + 1(2)
STATUS 73 74 76 77 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 73747677 --0x 0000 --0u 0000 --uu uuuu
PORTB 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 73 74 76 77 ---- -xxx ---- -uuu ---- -uuu
PCLATH 73 74 76 77 ---0 0000 ---0 0000 ---u uuuu
INTCON 73 74 76 77 0000 000x 0000 000u uuuu uuuu(1)
PIR1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu(1)
73 74 76 77 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u(1)
TMR1L 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 73747677 --00 0000 --uu uuuu --uu uuuu
TMR2 73 74 76 77 0000 0000 0000 0000 uuuu uuuu
T2CON 73747677 -000 0000 -000 0000 -uuu uuuu
SSPBUF 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu
CCPR1L 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 73 74 76 77 --00 0000 --00 0000 --uu uuuu
RCSTA 73 74 76 77 0000 -00x 0000 -00x uuuu -uuu
TXREG 73747677 0000 0000 0000 0000 uuuu uuuu
RCREG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu
CCPR2L 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu
ADRES 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 73 74 76 77 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 73 74 76 77 1111 1111 1111 1111 uuuu uuuu
TRISA 73747677 --11 1111 --11 1111 --uu uuuu
TRISB 73747677 1111 1111 1111 1111 uuuu uuuu
TRISC 73747677 1111 1111 1111 1111 uuuu uuuu
TRISD 73 74 76 77 1111 1111 1111 1111 uuuu uuuu
TRISE 73 74 76 77 0000 -111 0000 -111 uuuu -uuu
PIE1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu
73 74 76 77 0000 0000 0000 0000 uuuu uuuu
PIE2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u
Legend: u = unchanged, x = unknown, - = unimpl em ent ed b it, re ad a s ’0’, q = val ue depends on condition,
r = reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET value for specific condition.
2000 Microchip Technology Inc. Advance Information DS30325A-page 103
PIC16F7X
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
PCON 73 74 76 77 ---- --qq ---- --uu ---- --uu
PR2 73747677 1111 1111 1111 1111 1111 1111
SSPSTAT 73 74 76 77 --00 0000 --00 0000 --uu uuuu
SSPADD 73747677 0000 0000 0000 0000 uuuu uuuu
TXSTA 73747677 0000 -010 0000 -010 uuuu -uuu
SPBRG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu
ADCON1 73 74 76 77 ---- -000 ---- -000 ---- -uuu
PMDATA 73 74 76 77 0--- 0000 0--- 0000 u--- uuuu
PMADR 73747677 xxxx xxxx uuuu uuuu uuuu uuuu
PMDATH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PMADRH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu
PMCON1 73 74 76 77 1--- ---0 1--- ---0 1--- ---u
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Registe r Devices Power-on Reset,
Brown-out Reset MCLR Reset,
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimpl em ent ed b it, re ad a s ’0’, q = val ue depends on condition,
r = reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET v alue for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16F7X
DS30325A-page 104 Advance Information 2000 Microchip Technology Inc.
FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-O UT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
2000 Microchip Technology Inc. Advance Information DS30325A-page 105
PIC16F7X
12.10 Interrupts
The PIC 16F7X fami ly has u p to 12 so urces of interrupt.
The interru pt control register (INTCON) reco rds individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts, or disables (if
cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an
interrupt’s flag bit and mask bit are s et, the int errupt wil l
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, th e RB port change interrupt
and the TMR 0 over flo w interru pt f lag s are co nt a ine d in
the INTCON register.
The peri phe ral interrupt flags are c on tained in the Spe-
cial Function Registers, PIR1 and PIR2. The corre-
sponding interrupt enable bits are contained in Special
Functio n Regis te r s, PIE1 an d PIE2, an d the perip hera l
interrupt enable bit is contained in Special Function
Register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed o nto the stack a nd the PC is loade d
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one o r tw o cy c le ins tructions. Indi vi dua l
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or the GIE bit.
FIGURE 12-9: INTE RRUP T LOGIC
Note: Indiv idual interrupt fl ag bits are s et, regard-
les s of the status of thei r correspondi ng
mask bit or the GIE bit.
PSPIF
PSPIE ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
CCP2IE
CCP2IF
The following table shows which devices have which interrupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16F76/73 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes
PIC16F77/74 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16F7X
DS30325A-page 106 Advance Information 2000 Microchip Technology Inc.
12.10.1 INT INTERRUPT
External interrupt on the RB0/INT p in is edg e triggere d,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or fall ing , if th e IN TEDG bit i s cl ea r. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routin e before re-enablin g this interrupt. The INT in ter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interr upt enabl e bit GIE dec ides w hether or no t the pro-
cesso r branche s to the in terrupt ve ctor followin g wake-
up. See Section 12.13 for details on SLEEP mode.
12.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
12.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. T y pically, use rs may wish to save key re g-
isters during an interrupt (i.e., W register and STATUS
register). This w il l hav e to be i mp lemen ted in software.
For the PIC16F73/74 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the sa me offse t from the bank bas e addres s
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEM P, are only define d
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F76/77 devices, temporary holding registers
W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
:
:(ISR) ;Insert user code here
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
2000 Microchip Technology Inc. Advance Information DS30325A-page 107
PIC16F7X
12.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nent s. T his RC oscilla tor is s ep arate from the R C osci l-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog T imer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-u p) . T he TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
.
FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The CLRWDT and SLEEP instructi on s cl ear
the WDT and the pos tscaler, if ass ign ed to
the WDT, and prevent it from timing out
and generat ing a device RESET condi tion.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the presca le r coun t w ill be cle are d, but the
presc al er ass ig nme nt is not changed.
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
8
Addr e s s N a m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) —CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
PIC16F7X
DS30325A-page 108 Advance Information 2000 Microchip Technology Inc.
12.13 P o wer-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keep s runni ng, the PD bi t ( STATUS<3>) is c lea red , th e
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitr y is dr awing cu rrent from th e I/O pi n, powe r-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid s witchi ng curre nts caus ed by fl oating input s. Th e
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execut ion and cause a "w ak e-up ". T he TO and PD bit s
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
The follo wing periph eral interrupt s can wake the device
from SLEEP:
1. PSP read or write (PIC16F74/77 only).
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
Other per ipherals cann ot generate interrup ts since d ur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruc tion is being e xecuted, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up thro ugh an interrupt event, the corres pon din g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
ins tructi on after t he SLEEP instruction. If the GIE bit is
set (enabled) , the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt addres s (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:
•If the interrupt occurs before the execution of a
SLEEP instr uct ion , the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
pos tscaler will not be cleared, the TO bit will not
be set and PD bits will not be cle are d.
•If the interrupt occurs during or after the exec u-
tion of a SLEEP instruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
pos tscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
2000 Microchip Technology Inc. Advance Information DS30325A-page 109
PIC16F7X
FIGURE 12-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Lat ency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
PIC16F7X
DS30325A-page 110 Advance Information 2000 Microchip Technology Inc.
12.14 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.15 ID Locations
Four memory locatio ns (2000h - 200 3h) are designated
as ID locations, where the user c an stor e checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
12.16 In-C irc uit Seri al Progr ammin g
PIC16F7X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with tw o lines for cl ock and data and thre e
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS302 77).
2000 Microchip Technology Inc. Advance Information DS30325A-page 111
PIC16F7X
13.0 INSTRUCTION SET SUMMARY
Each PIC1 6F7X instructio n is a 14-bit word divid ed into
an O PCODE, wh ich spec ifies th e instru ction ty pe and
one or more operands, which further specify the oper-
ation of the instruction. The PIC16F7X instruction set
summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one , the result is pl aced
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
design ator which selec t s the number of the bi t a f fected
by the oper ation, w hile ’f’ represents th e add res s of th e
file in which the bit is located.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basi c categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram coun ter is changed as a result of an instruction.
In thi s cas e, t he ex ec u ti o n tak es tw o in s tru ct i o n cy cl es
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osc illator frequency of 4 M Hz, th e normal i nstructio n
executi on tim e is 1 µs. If a con dition al tes t is tr ue or th e
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 13-2 lists the instructions recognized by the
MPASM assembler.
Figur e 13-1 shows the ge neral fo rmats th at the instruc -
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual, (D S33023).
Field Description
fRegister file addr ess (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care location (= 0 or 1)
The assembler will generate code with x = 0.
It is the recom mende d form of use for comp at-
ibility with all Microchip softw are tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Ti me-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16F7X products, do not use the
OPTION and TRIS instr ucti ons.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (liter a l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F7X
DS30325A-page 112 Advance Information 2000 Microchip Technology Inc.
TABLE 13-2: PIC16F7X INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Tim er
Go to address
Inclusive OR literal with W
Move litera l to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
2000 Microchip Technology Inc. Advance Information DS30325A-page 113
PIC16F7X
13.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the e ight bit litera l ’k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Descript ion: Add th e contents of th e W register
with regi ster ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regist er. If 'd ' is 1, the re sult
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is cleared.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
PIC16F7X
DS30325A-page 114 Advance Information 2000 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Descript ion: If bit ’b’ in register ’f’ is ’0’, the next
instructi on is exec uted .
If bit ’b’ is ’1’, then the next instruc-
tion is dis ca r de d a nd a NOP is exe-
cuted in stead making thi s a 2TCY
instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Descript ion: If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is execut ed instead, ma king
this a 2TCY instru ction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC) + 1 → TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine . First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate addre ss i s loaded int o PC bits
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a two cycle instruction.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Description: The contents of register ’f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is se t.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
2000 Microchip Technology Inc. Advance Information DS30325A-page 115
PIC16F7X
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W . If ’d’ is 1, the
result is stored back in register ’f’.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affected: Z
Description: Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: Non e
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead
making it a 2TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The eleven bit immediate value is
loaded into PC bi ts <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W regis ter. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
incremen ted. If ’d’ is 0, the resu lt is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is execute d i ns tea d m ak ing
it a 2TCY instruction.
PIC16F7X
DS30325A-page 116 Advance Information 2000 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination )
Status Affected: Z
Description: The contents of register f are
moved t o a destination depen dant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destinat ion is fi le regi ster f itse lf. d
= 1 is useful to test a file register
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Descripti on : Move data from W reg is ter t o re g-
ister 'f'.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
2000 Microchip Technology Inc. Advance Information DS30325A-page 117
PIC16F7X
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Description: The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed a nd the t op of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ ar e
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are
rotated o ne bit to the right through
the C arry Flag. If ’d’ is 0 , the res ult
is place d in the W re gister. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
SLEEP
Syntax: [ label ]SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Descripti on: The power-down status bit , PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The proc essor is put i nto SLEEP
mode with the os cillator stopped.
Register fC
Register fC
PIC16F7X
DS30325A-page 118 Advance Information 2000 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Desc ript ion : The W register is su btra cte d (2’s
complement method) from the
eight bit literal 'k'. The result is
placed i n the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register 'f'. If ' d' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the re sult is placed in
register 'f'.
XORLW Exclusive OR Literal with W
Syntax: [label] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
2000 Microchip Technology Inc. Advance Information DS30325A-page 119
PIC16F7X
14.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hard ware and soft ware devel opment tools:
•Integrated Development Environment
- MPLAB® IDE Software
•Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
•Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- ICEPIC™
•In-Circuit Debugger
- MPLAB-ICD for PIC16F87X
•Device Programmers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-L ev el Protot ype
Programmer
•Low-Cost Demonstration Boards
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
-K
EELOQ
14.1 MPLAB Integrated Developmen t
Environme n t Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows-based applica-
tion whic h contains:
•Multiple functionality
-editor
- simulator
- programmer (sold sep arately )
- emulat or (sold separately)
•A full featu red editor
•A project manager
•Customizable tool bar and key mapping
•A status bar
•On-line help
MPLA B allows you to:
•Edit your s ource files (either assembly or ‘C’)
•One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct info rma tio n)
•Debug us ing :
- source files
- absolu te listing file
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abi l-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
14.2 MPASM Assembler
MPASM is a full featured universal macro assembler
for all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be used as a st andal one appl icatio n on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which c ontains source li nes and gen-
erated machine code, and a COD file for MPLAB
debugging.
MPASM features include:
•MPASM and MPLINK are integrated into MPLAB
projects.
•MPASM allows us er define d macros to be crea ted
for streamlined assembly.
•MPASM allows c ond iti ona l as sembly for multi p ur-
pose source files.
•MP ASM directives allow complete control over the
assembly p rocess.
14.3 MPLAB- C17 and MPLAB- C18
C Compilers
The MPLAB- C17 and MP LAB-C18 Code De velop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le r s.
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16F7X
DS30325A-page 120 Advance Information 2000 Microchip Technology Inc.
14.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
object s from assembl y or C sourc e file s alon g wi th pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK feat ures incl ude:
•MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
•MPLINK allows all memory are as to be d efined as
sections to provide link-time flexibility.
MPLIB features incl ud e:
•MPLIB ma ke s l in kin g e as ier because single librar-
ies can be included instead of many smaller files.
•MPLIB he lps ke ep code maint aina ble by groupi ng
related modules together.
•MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
14.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug c ode outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
14.6 MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product developm ent engineer
with a complete microcontroller design tool set for
PICmicro micro control le rs (MCUs). Software contr ol of
MPLAB-ICE is provided by the MPLAB Integrated
Devel op ment Env iron me nt (IDE ), whi ch al lo ws edi tin g,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive
development tools. The PC platform and Microsoft®
Windows 3.x/95/98 environment were chosen to best
make these features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
14.7 ICEPIC
ICEPIC is a low-cost in-circuit emulation s olution f or the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, a nd PIC16 CXXX f amilies of 8-bi t one-t ime-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of interchange-
able personality modules or daughter boards. The
emulato r is cap able of em ulating withou t targe t applica-
tion circuitry being present.
14.8 MPLAB-ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This featu re, along with Microchip ’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Developm en t Environment. This enabl es a desi gn er to
develop and debug sou rce code by watchin g variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
2000 Microchip Technology Inc. Advance Information DS30325A-page 121
PIC16F7X
14.9 PRO MATE II Universal Programmer
The P RO MATE II Univer sal Pr ogramm er is a f ull-f ea-
tured programmer capable of operating in stand-alone
mode as w el l as PC -h ost ed m od e. PRO M ATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for ma xi mum r e li abi lity. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket asse mbly to suppo rt var ious pac kage ty pes. In
stan d-al on e m od e the PR O M ATE II can re ad, v erif y or
program PICmicro devices. It can also set code-protect
bits in this mode.
14.10 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
progra mmer si mpl e and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
14.11 PICDEM-1 Low-Cost PICmicr o
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downlo a d t h e
firmware to the emulator for testing. Additional proto-
type area is av ailable for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
14.12 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or P I CS TA R T- Pl u s , a n d ea s i l y te s t f i r mw a r e .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 boa rd to te st firmware. Additiona l p roto typ e
area has been provided to the user for adding addi-
tional ha rdware and connecti ng it to the m icrocontr oller
socket(s). Some of the features inc lude a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage o f the I2C bu s and sep arate h eaders for c onnec-
tion to an LCD module and a keypad.
14.13 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers w ith a LCD Mod ule. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additi onal p rototyp e are a has bee n provide d to
the user fo r addin g hardwa re and con necti ng it to th e
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a key pa d. A lso p rovide d on the PICD EM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is c apable of displayi ng time, tempera ture
and day o f the we ek. The PICDEM -3 pr ovides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A
simple serial interface allows the user to construct a
hardware demultiplexer for the LCD signals.
PIC16F7X
DS30325A-page 122 Advance Information 2000 Microchip Technology Inc.
14.14 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
stra tes the c apabiliti es of seve ral Micro chip mic rocon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is inc luded to run ba sic demo p rograms, wh ich are sup-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the user ma y erase it and prog ram it with
the other sample programs using the PRO MATE II or
PICSTAR T Plus d evice p rogrammers and e asily d ebug
and t est the sample code. In addi tion, PICDEM-17 su p-
ports down-loadi ng of programs to a nd executing out of
external FLASH memory on board. The PICDEM-17 is
also usabl e with the MPLAB -ICE or PICMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Se cure Dat a Product s. The HCS e val-
uation kit includes an LCD display to show changing
codes, a decoder to decode transm issions, and a pro-
gramming interface to program test transmitters.
2000 Microchip Technology Inc. Advance Information DS30325A-page 123
PIC16F7X
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Software Tools
MPLAB® Integrated
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB® C17 Compiler
á
á
MPLAB® C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB®-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
ICEPIC‰ Low-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB®-ICD In-Circuit
Debugger
á
*
á
*
á
Programmers
PICSTART‚Plus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE‚ II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards and Eval Kits
PICDEM-1
á
á
á
†
á
á
PICDEM-2
á
†
á
†
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® Evaluation Kit
á
KEELOQ Transp on der Kit
á
microID™ Programmer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB®-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16F7X
DS30325A-page 124 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 125
PIC16F7X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) .........................................-0.3V to (VDD + 0.3V)
Volta ge on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Volta ge on MC LR with respect to VSS (Note 2)...............................................................................................0 to +13.5V
Voltage on RA4 with respect to Vss...................................................................................................................0 to +12V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum curr ent out of VSS pin ...........................................................................................................................300 mA
Maximum curr ent i nto VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum curr ent sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) .............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: V oltage spikes below VSS at the MCL R pin, inducing currents greater than 80 mA, may cause la tch-up. Thus,
a seri es re sisto r of 50-10 0Ω shou ld be used wh en appl ying a “low” level to the MCLR p in, rather than pulling
this pin directly to VSS.
3: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F7X
DS30325A-page 126 Advance Information 2000 Microchip Technology Inc.
FIGURE 15-1: PIC16F7X VOLTAGE-FREQUENCY GRAPH
FIGURE 15-2: PIC16LF7X VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
20 MHz
5.0 V
3.5 V
3.0 V
2.5 V
16 MHz
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10MHz.
2000 Microchip Technology Inc. Advance Information DS30325A-page 127
PIC16F7X
15.1 DC Characteristics
PIC16LF73/74/76/77
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial
PIC16F73/74/76/77
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Sym Characteristic Min Typ†Max Units Conditions
D001 VDD Supply Voltage
PIC16LF7X 2.0 - 5.5 V All osc configurations (DC - 10 MHz)
D001
D001A PIC16F7X 4.0
VBOR*-
-5.5
5.5 V
VAll configurations
BOR enabled (Note 7)
D002* VDR RAM Dat a Retention
Voltage (Note 1) -1.5-V
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
-V
SS - V See section on Power-on Reset fo r details
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 - - V/ms See section on Power-on Reset for details
D005 VBOR Brown-out Reset Voltage 3.65 4.0 4.35 V BODEN bit in configuration word enabled
D010 IDD Supply Current (Note 2, 5)
D010A
PIC16LF7X -
-
0.6
20
2.0
35
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010
D013
PIC16F7X -
-
1.6
7
4
15
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc con figu r ati on
FOSC = 20 MHz, VDD = 5.5V
D015* DIBOR Brown-out Reset Current
(Note 6) - 85 200 µA BOR enabled VDD = 5.0V
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly cu rrent is mainly a fu nc tio n of the operating voltage and frequ en cy. Other fac to r s s uch as I/O pi n
loading and switching rate, oscillator ty pe, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave , from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current th rough REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: T i mer1 os cill ator (when enable d) a dds approx imate ly 20 µA to the s pecifi catio n. This value is from c haracte r-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when th is peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F7X
DS30325A-page 128 Advance Information 2000 Microchip Technology Inc.
D020 IPD Power-down Current (Note 3, 5)
D021 PIC16LF7X -
-7.5
0.9 30
5µA
µAVDD = 3.0V, WDT enabl ed, -40°C to +85°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D020
D021 PIC16F7X -
-10.5
1.5 42
19 µA
µAVDD = 4.0V, WDT enabl ed, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
D023* DIBOR Brown-out Reset Current
(Note 6) - 85 200 µA BOR enabled VDD = 5.0V
PIC16LF73/74/76/77
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial
PIC16F73/74/76/77
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Sym Characteristic Min Typ†Max Units Conditions
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly cu rrent is mainly a fu nc tio n of the operating voltage and frequ en cy. Other fac to r s s uch as I/O pi n
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in acti ve operation mode are:
OSC1 = external square wave , from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current th rough REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: T i mer1 os cill ator (when ena bled) a dds ap proximat ely 20 µA to th e specifi catio n. This value is from characte r-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2000 Microchip Technology Inc. Advance Information DS30325A-page 129
PIC16F7X
15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial)
PIC16LF73/74/76/77 (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial and
Operat ing vo ltage VDD range as described i n D C s pe c Se ct ion 15.1
and Section 15.2.
Param
No. Sym Characteristic Min Typ†Max Units Conditions
VIL Input Low Voltage
I/O ports
D030 with TTL buffer VSS - 0.15VDD V For entire VDD range
D030A VSS -0.8VV4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS -0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS -0.2VDD V
D033 OSC1 (in XT and LP mode) VSS -0.3VV(Note 1)
OSC1 (in HS mode) VSS -0.3VDD V(Note 1)
Ports RC3 and RC4
D034 with Schmitt Trigger buffer VSS -0.3VDD V For entire VDD range
VIH Input High Voltage
I/O ports -
D040 with TTL buffer 2.0 - VDD V4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (in XT and LP mode) 1.6V - VDD V(Note 1)
OSC1 (in HS mode) 0.7VDD -VDD V(Note 1)
D043 OSC1 (in RC mode) 0.9VDD -VDD V
Ports RC3 and RC4
D044 with Schmitt Trigger buffer 0.7VDD -VDD V For entire VDD range
D070 IPURB PORTB Weak Pull-up Current 50 250 400 µAVDD = 5V, VPIN = VSS
IIL Input Leakage Current (Notes 2, 3)
D060 I/O ports - - ± 1 µAVss ≤ VPIN ≤ VDD, Pin at
hi-impedance
D061 MCLR, RA4/T0CKI - - ±5 µAVss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5 µAVss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
VOL Output Low Voltage
D080 I/O ports - - 0. 6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
VOH Output High Voltage
D090 I/O ports (Note 3) VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D150* VOD Open-Drain High Voltage --12VRA4 pin
Legend: * These para me ters are chara cte rized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tes ted .
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leak age c urre nt on the MCLR pin is s tron gly d ependent on the ap pl ied v oltage leve l. Th e s pe ci fied l ev els
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16F7X
DS30325A-page 130 Advance Information 2000 Microchip Technology Inc.
Capa citive Loading Sp ecs on Output Pins
D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when
external cl oc k is used to dri ve O SC 1
D101 CIO All I/O pins and OSC2
(in RC mode) - - 50 pF
D102 CBSCL, SDA in I2C mode --400pF
Program FLASH Memory
D130 EPEndurance - - 100 E/W 25°C at 5V
D131 VPR VDD for read 2.0 - 5.5 V
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial and
Operat ing vo ltage VDD range as described i n D C s pe c Se ct ion 15.1
and Section 15.2.
Param
No. Sym Characteristic Min Typ†Max Units Conditions
Legend: * These para me ters are chara cte riz ed but not tested .
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tes ted .
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leak age c urre nt on the MCLR pin is s tron gly d ependent on the ap pl ied v oltage leve l. Th e s pe ci fied l ev els
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc. Advance Information DS30325A-page 131
PIC16F7X
15.3 Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
FIGURE 15-3: LOA D CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercas e letters and t heir meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA ou tput access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
Load condition 1 Load condition 2
PIC16F7X
DS30325A-page 132 Advance Information 2000 Microchip Technology Inc.
FIGURE 15-4: EXTERNAL CLOCK TIMING
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENT S
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
FOSC External CLKIN Frequency
(Note 1) DC —1 MHz XT osc mode
DC —20 MHz HS osc mode
DC —32 kHz LP osc mode
Oscillator Frequency
(Note 1) DC —4 MHz RC osc mode
0.1 —4MHzXT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1TOSC External CLKIN Period
(Note 1) 1000 ——ns XT osc mode
50 ——ns HS osc mode
5——ms LP osc mode
Oscillator Period
(Note 1) 250 ——ns RC osc mode
250 —10,000 ns XT osc mode
50 —250 ns HS osc mode
5——ms LP osc mode
2TCY Instruction Cycle Time
(Note 1) 200 TCY DC ns TCY = 4/FOSC
3TosL,
TosH External Clock in (OSC1) High
or Low Time 500 ——ns XT oscillator
2.5 ——ms LP oscillator
15 ——ns HS oscillator
4TosR,
TosF External Clock in (OSC1) Rise
or Fall Time — —25 ns X T oscillator
— —50 ns LP oscillator
—— 15 ns HS oscillator
Legend: †Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four tim es the inpu t osc il lat or tim e ba se perio d. All spe ci fie d va lue s are
based o n cha racteri zation da ta for that par ticula r os cillato r ty pe und er st andar d opera tin g conditi ons w ith th e
device exec uting code. Ex ceedi ng thes e sp ecifie d lim its may resul t in a n uns tabl e osc illat or oper atio n and /or
higher tha n expecte d current co nsumptio n. All devi ces are tested t o operate at "min." val ues with an ex ternal
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is
"DC" (no clock) for all devices.
2000 Microchip Technology Inc. Advance Information DS30325A-page 133
PIC16F7X
FIGURE 15-5: CLKOUT AND I/O TIMING
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 15- 3 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new value
Param
No. Sym Characteristic Min Typ†Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ —75 200 ns (Note 1)
11* TosH2ckH OSC1↑ to CLKOUT↑ —75 200 ns (Note 1)
12* TckR CLKOUT rise time —35 100 ns (Note 1)
13* TckF CLKOUT fall time —35 100 ns (Note 1)
14* TckL2ioV CLKOUT ↓ to Port out valid ——0.5TCY + 20 ns (Note 1)
15* TioV2ckH Port in valid before CLKOUT ↑ T
OSC + 200 ——ns (Note 1)
16* TckH2ioI Port in hold after CLKOUT ↑ 0——ns (Note 1)
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid —100 255 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F) 100 ——ns
Extended (LF) 200 ——ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 ——ns
20* TioR Port output rise time Standard (F)—10 40 ns
Extended (LF)——145 ns
21* TioF Port output fall time Standard (F)—10 40 ns
Extended (LF)——145 ns
22††* Tinp INT pin high or low time Tcy ——ns
23††* Trbp R B 7:R B4 change INT high or low time Tcy ——ns
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
PIC16F7X
DS30325A-page 134 Advance Information 2000 Microchip Technology Inc.
FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIM ING
FIGURE 15-7: BROWN-OUT RESET TIMING
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 15-3 for load conditions.
VDD VBOR
35
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 ——µsVDD = 5V, -40°C to +85°C
31* Twdt Watchdog Timer Time-out Period
(No Prescaler) 71833msV
DD = 5V, -40°C to +85°C
32 Tost Oscillation St art-up Timer Period —1024 TOSC ——TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset ——2.1 µs
35 TBOR Brown-out Reset Pulse Width 100 ——µsVDD ≤ VBOR (D005)
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2000 Microchip Technology Inc. Advance Information DS30325A-page 135
PIC16F7X
FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Note: Refer to Figure 15-3 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 o r
TMR1
Param
No. Sym Characteristic Min Typ†Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 ——ns Must also meet
parameter 42
With Prescaler 10 ——ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 ——ns Must also meet
parameter 42
With Prescaler 10 ——ns
42* Tt0P T0C KI Period No Prescaler TCY + 40 ——ns
With Prescaler Greater of:
20 or TCY + 40
N
——ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous , Pres caler = 1 0.5TCY + 20 ——ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8 Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
46* Tt1L T1CKI Low Time Synchronous , Prescaler = 1 0.5TCY + 20 ——ns Mus t also meet
parameter 47
Synchronous,
Prescaler = 2,4,8 Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
47* Tt1P T1CKI input period Synchronous Standard(F) Greater of:
30 OR TCY + 40
N
——ns N = prescale value
(1, 2, 4, 8)
Extended(LF) Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard(F)60——ns
Extended(LF) 100 ——ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKE Z tmr1 Delay from external clock edge to timer increment 2Tosc —7Tosc —
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
PIC16F7X
DS30325A-page 136 Advance Information 2000 Microchip Technology Inc.
FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 15-3 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
Param
No. Sym Characteristic Min Typ†Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 ——ns
With Prescal er Standard(F)10——ns
Extended(LF)20——ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 ——ns
With Prescal er Standard(F)10——ns
Extended(LF)20——ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N——ns N = prescale
value (1,4 or 16)
53* TccR CCP1 and CCP2 output rise time Standard(F)—10 25 ns
Extended(LF)—25 50 ns
54* TccF CCP1 and CCP2 output fall time Standard(F)—10 25 ns
Extended(LF)—25 45 ns
Legend: * These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2000 Microchip Technology Inc. Advance Information DS30325A-page 137
PIC16F7X
FIGURE 15-10: PARALLEL SLAVE PORT TIMING (PIC16F74/77 DEVICES ONLY)
TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F74/77 DEVICES ONLY)
Note: Refer to Figure 15-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
62 TdtV2w r H D a ta in v a l i d befor e W R↑ or CS↑ (setup time) 20
25 —
——
—ns
ns Extended
Range Only
63* TwrH2dtI WR↑ or CS↑ to data in invalid (hold time) Standard(F)20——ns
Extended(LF)35——ns
64 TrdL2dtV RD↓ and CS↓ to data out valid —
——
—80
90 ns
ns Extended
Range Only
65 TrdH2dtI RD↑ or CS↓ to data out invalid 10 —30 ns
Legend: * These parame ters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
PIC16F7X
DS30325A-page 138 Advance Information 2000 Microchip Technology Inc.
FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 15-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 15-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 15-3 for load conditions.
2000 Microchip Technology Inc. Advance Information DS30325A-page 139
PIC16F7X
FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT 6 - - - -1 LSb IN
83
Note: Refer to Figure 15-3 for load c onditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BIT6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
Note: Refer to Figure 15-3 for load conditions.
PIC16F7X
DS30325A-page 140 Advance Information 2000 Microchip Technology Inc.
TABLE 15-7: SPI MODE REQUIREM ENTS
FIGURE 15-15 : I2C BUS START/STOP BITS TIMING
Param
No. Sym Characteristic Min Typ†Max Units Conditions
70* TssL2scH,
TssL2scL SS↓ to SCK ↓ or SCK↑ input TCY ——ns
71* TscH SCK input high time (Slave mode) TCY + 20 ——ns
72* TscL S CK input low time (Slave mode) TCY + 20 ——ns
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ——ns
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ——ns
75* TdoR SDO data output rise time Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
76* TdoF SDO data output fall time —10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 —50 ns
78* TscR SCK output rise time (Master mode) Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
79* TscF S CK output fall time (Master mode) —10 25 ns
80* TscH2doV,
TscL2doV SDO data output valid after SCK
edge Standard(F)
Extended(LF)—
——
—50
145 ns
ns
81* TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY ——ns
82* TssL2doV SDO data output valid after SS↓ edge ——50 ns
83* TscH2ssH,
TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 ——ns
Legend: * These paramete rs are charact erized but not tested.
†Dat a in "Typ" column is at 5V, 25°C unl ess otherwi se sta ted. These paramet ers are for design guidance on ly and ar e not test ed.
Note: Refer to Figure 15-3 for load conditions.
91
92
93
SCL
SDA
START
Condition STOP
Condition
90
2000 Microchip Technology Inc. Advance Information DS30325A-page 141
PIC16F7X
TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 15-16 : I2C BUS DATA TIMING
Param
No. Sym Characteristic Min Typ Max Units Conditions
90* TSU:STA START condition 100 kHz mode 4700 —— ns Only relevant for Repeated
START condition
Setup time 400 kHz mode 600 ——
91* THD:STA START condition 100 kHz mode 4000 —— ns After this period the first clock
pulse is generated
Hold ti me 400 kHz mode 600 ——
92* TSU:STO STOP condition 100 kHz mode 4700 —— ns
Setup time 400 kHz mode 600 ——
93 THD:STO STOP condition 100 kHz mode 4000 —— ns
Hold ti me 400 kHz mode 600 ——
* These parameters are characterized but not tested.
Note: Refer to Figure 15-3 for load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16F7X
DS30325A-page 142 Advance Information 2000 Microchip Technology Inc.
TABLE 15-9: I2C BUS DAT A REQUIREMENTS
Param.
No. Sym Characteristic Min Max Units Conditions
100* THIGH Clock high time 100 kHz mode 4.0 —µs Device must ope rate at a
minimum of 1.5 MHz
400 kHz mode 0.6 —µs De vi ce mu st ope rate at a
minimum of 10 MHz
SSP Module 1.5TCY —
101* TLOW Clock low time 100 kHz mode 4.7 —µs De vi ce mu st ope rate at a
minimum of 1.5 MHz
400 kHz mode 1.3 —µs De vi ce mu st ope rate at a
minimum of 10 MHz
SSP Module 1.5TCY —
102* TRSDA and SCL rise
time 100 kHz mode —1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10-400 pF
103* TFSDA and SCL fall
time 100 kHz mode —300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10-400 pF
90* TSU:STA START condition
setup time 100 kHz mode 4.7 —µs Only relevant for Repeated
START condition
400 kHz mode 0.6 —µs
91* THD:STA START condition
hold time 100 kHz mode 4.0 —µs After this period the first
clock pulse is generated
400 kHz mode 0.6 —µs
106* THD:DAT Data input hold time 100 kHz mode 0 —ns
400 kHz mode 0 0.9 µs
107* TSU:DAT Data input setup
time 100 kHz mode 250 —ns (Note 2)
400 kHz mode 100 —ns
92* TSU:STO STOP condition
setup time 100 kHz mode 4.7 —µs
400 kHz mode 0.6 —µs
109* TAA Out put val id from
clock 100 kHz mode —3500 ns (Note 1)
400 kHz mode ——ns
110* TBUF Bus free time 100 kHz mode 4.7 —µs Time the b us must be free
before a new transmission
can start
400 kHz mode 1.3 —µs
Cb Bus capacitive loading — 400 pF
* These pa rameters are characterized but not tested.
Not e 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I2C-bus device can be used in a standard mode (100 kHz) I2C bus system, but the
requirement Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LO W pe riod of th e SC L s ig nal . If s uch a d ev ic e do es s tre tch the LO W pe riod of th e SC L sig nal , it
must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL li ne is released.
2000 Microchip Technology Inc. Advance Information DS30325A-page 143
PIC16F7X
FIGURE 15-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 15-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 15-11: US ART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 15-3 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
Pin
Pin
120
Param
No. Sym Characteristic Min Typ†Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Standard(F)——80 ns
Extended(LF)——100 ns
121 Tckrf Clock out rise time and fall time
(Master mode) Standard(F)——45 ns
Extended(LF)——50 ns
122 Tdtrf Data out rise time and fall time Standard(F)——45 ns
Extended(LF)——50 ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 15-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 ——ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 ——ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
PIC16F7X
DS30325A-page 144 Advance Information 2000 Microchip Technology Inc.
TABLE 15-12: A/D CONVERTER CHARACTERISTICS: PIC16F7X (INDUSTRIAL)
PIC16LF7X (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ†Max Units Conditions
A01 NRResolution PIC16F7X ——8 bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LF7X ——8 bits bit VREF = VDD = 2.0V
A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Dif fere nti al lin eari ty error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error ——< ± 1 L Sb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offs et error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 —Monotonicity (Note 3) —guaranteed ——VSS ≤ VAIN ≤ VREF
A20 VREF Reference vo lt ag e 2.0V —VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 —VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source ——10.0 kΩ
A40 IAD A/D conversion
current (VDD)PIC16F7X —180 —µA Average current con-
sumption when A/D is
on (Note 1).
PIC16LF7X —90 —µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to V AIN to charge
CHOLD, see
Section 12.1.
During A/D Conversion
cycle.
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2000 Microchip Technology Inc. Advance Information DS30325A-page 145
PIC16F7X
FIGURE 15-19: A/D CONVE RSION TIMING
TABLE 15-13: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2)(1)
7 6543210
Note 1: If the A /D clock source is s elected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
134
Param
No. Sym Characteristic Min Typ†Max Units Conditions
130 TAD A/D clock period PIC16F7X 1.6 ——µsTOSC based, VREF ≥ 3.0V
PIC16LF7X 2.0 ——µsT
OSC based ,
2.0V ≤ VREF ≤ 5.5V
PIC16F7X 2.0 4.0 6.0 µs A/D RC mode
PIC16LF7X 3.0 6.0 9.0 µs A/D RC mode
131 TCNV Conversion time (not including S/H
time) (Note 1) 9—9TAD
132 TACQ Acquisition time 5* ——µs The minimum time is the
amplifier settling time. This
may be used i f the “new”
input voltage has not
changed by m ore tha n 1 LSb
(i.e., 20.0 mV @ 5.1 2V) from
the last sampled voltage (as
stated on CHOLD).
134 TGO Q4 to A/D clock start —TOSC/2 ——If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D cl ock
sta rts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time 1.5 §— —TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycl e.
2: See Section 12.1 for min. conditions.
PIC16F7X
DS30325A-page 146 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 147
PIC16F7X
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are out-
side specified operating range (i.e., out side specified
VDD rang e). This is for information only and devices
are ensured to operate properly only within the speci-
fied range.
The dat a pres ented in thi s section is a st atistical su m-
mary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ repre-
sent s the mean of the distribution at 25°C. ’Max’ or ’Min’
represents (mean + 3σ) or (mean - 3σ), respectively,
where σ is st a nda rd de via tion over the whole tempera-
ture range.
Graphs and Tables not available at this time.
PIC16F7X
DS30325A-page 148 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 149
PIC16F7X
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
28-Lead SO IC
YYWWNNN
Example
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
0017HAT
PIC16F77-I/SP
XXXXXXXXXXXXXXXXXXXX 0010SAA
PIC16F76-I/SO
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full M icroch ip p art numb er canno t be mark ed on one line, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, and traceability code. For
marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For
QTP devices, any special marking adders are included in QTP price.
28-Lead SSOP
YYWWNNN
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
0010SBP
PIC16F73-I/SS
PIC16F7X
DS30325A-page 150 Advance Information 2000 Microchip Technology Inc.
Package Marking Information (Cont’d)
XXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP Example
44-Lead TQFP
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
Example
44-Lead PLCC Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
PIC16F77-I/P
0012SAA
I/PT
0011HAT
PIC16F77-
0003SAT
PIC16F77-I/L
2000 Microchip Technology Inc. Advance Information DS30325A-page 151
PIC16F7X
17.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing §0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125
A2
Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimens ion D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254 mm ) per s ide.
§ Significant Characteristic
PIC16F7X
DS30325A-page 152 Advance Information 2000 Microchip Technology Inc.
17.3 28-Lead Plastic Small Outline (SO) –Wide, 300 mil (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
2000 Microchip Technology Inc. Advance Information DS30325A-page 153
PIC16F7X
17.4 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10501050Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
φ
Foot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOve ra ll Length 5.385.255.11.212.207.201
E1
Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff §1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
β
c
φ
α
A2
A1
A
β
§ Significant Characteristic
PIC16F7X
DS30325A-page 154 Advance Information 2000 Microchip Technology Inc.
17.5 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing §0.560.460.36.022.018.014BLower Lea d Width 1.781.270.76.070.050.030B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
β
eB
E
α
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
2000 Microchip Technology Inc. Advance Information DS30325A-page 155
PIC16F7X
17.6 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dim ension Limit s MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff §A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
§ Significant Characteristic
PIC16F7X
DS30325A-page 156 Advance Information 2000 Microchip Technology Inc.
17.7 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45°CH1 x 45°
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008
c
Lead Thickness
1111n1Pins per Side
16.0015.7514.99.630.620.590D2Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024A3Side 1 Chamfer Height 0.51.020A1Standoff §A2Molded Package Thickness 4.574.394.19.180.173.165AOverall Height
1.27.050
p
Pitch 4444
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
β
A2
c
E2
2
D
D1
n
#leads=n1
E
E1
1
α
p
A3
A
35°
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
§ Significant Characteristic
2000 Microchip Technology Inc. Advance Information DS30325A-page 157
PIC16F7X
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE DIFFERENCES
The differences bet ween the devi ces in th is dat a she et
are listed in Table B-1.
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions
of de vices to the one s listed in this dat a sheet are liste d
in Table C-1.
Version Date Revision Desc ri ption
A 2000 This is a new data sheet. However, these devices are similar to the PIC16C7X
devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X
devices (DS30292).
TABLE B-1: DEVICE DIFFERENCES
Difference PIC16F76/73 PIC16F77/74
A/D 5 channels, 8-bits 8 channels, 8-bits
Parallel Slave Port no yes
Package s 28-pi n PDIP, 28-pin SOIC, 28-pin SSO P 40-pin PDIP, 44-p in TQFP, 44-pin PLCC
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16C7X PIC16F87X PIC16F7X
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 11 or 12
Communication PSP, USART, SSP (SPI,
I2C Slave) PSP, USART, SSP (SPI,
I2C Master/Slave) PSP, USART, SSP (SPI,
I2C Slave)
Frequency 20 MHz 20 MHz 20 MHz
A/D 8-bit 10-bit 8-bit
CCP 2 2 2
Program Memory 4K, 8K EPROM 4K, 8K FLASH
(1,000 E/W cycles) 4K, 8K FLASH
(100 E/W cycles)
RAM 192, 368 by tes 192, 368 bytes 192, 368 bytes
EEPROM Data None 128, 256 bytes None
Other —In-Circuit Debugger,
Low Voltage Program ming —
PIC16F7X
DS30325A-page 158 Advance Information 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. Advance Information DS30325A-page 159
PIC16F7X
INDEX
A
A/D ..................................................................................... 89
ADCON0 Register ......................................................89
ADCON1 Register ......................................................90
Analog Input Model Block Diagram ............................92
Analog Port Pins ......................................7, 8, 9, 37, 38
Analog-to-Digital Converter ........................................89
Block Diag ram ........ ..................... ..................... ..........91
Configuring Analog Port Pins .....................................93
Configuring the Interrupt ............................................91
Configuring the Module ..............................................91
Conversio n Clo ck .......................................................93
Conversions ...............................................................93
Converter Characteristics ........................................144
Effects of a RESET ....................................................93
Faster Conversion - Lower Resolution Tradeoff ........93
Internal Sampling Switch (Rss) Impedance .. .............92
Operation During SLEEP ...........................................93
Sampling Requirements ............................ .. ....... .. .. ....92
Source Impedance .................................... ......... .... ....92
Timing Dia g r a m .............. ........... ..................... ..........145
Using the CCP Trigger ...............................................93
Absolute Maximum Ratings .............................................125
ACK ..............................................................................67, 69
ADRES Register ..........................................................15, 89
Analog Port Pins. See A/D
Application Notes
AN552 (Implementing Wake-up on Key Strokes Using
PIC16F7X) ................................................................. 31
AN556 (Table Reading Using PIC16CXX ..................26
AN578 (Use of the SSP Module in the I2C Multi-Master
Environment) ..............................................................61
Architecture
PIC16F73/PIC16F76 Block Diagram ...........................5
PIC16F74/PIC16F77 Block Diagram ...........................6
Assembler
MPASM Assembler ..................................................119
B
Banking, Data Memory ......................................................12
BF ................................................................................62, 67
Block Diagrams
A/D .............................................................................91
Analog Input Model ....................................................92
Capture ...................................................................... 57
Compare ....................................................................58
I2C Mode ....................................................................67
PWM ..........................................................................58
SSP in I2C Mode ........................................................67
SSP in SPI Mode .......................................................64
Timer0/WDT Prescaler ..............................................45
Timer2 ........................................................................53
USART Recei ve ................... ..................... .................79
USART Transmit .............. ..................... ........... ..........77
BOR. See Brown-out Reset
BRGH bit ............................................................................75
Brown-out Reset (BOR) ...............................95, 99, 101, 102
Buffe r Full Status b it, BF ........ ........... ..................... .......... ..62
C
Capture/Compare/PWM
Capture
Block Diag ram ............... ..................... ...............57
CCP1CON Registe r ................ ...........................56
CCP1IF .............................................................. 57
Mode ................................................................. 57
Prescaler ........................................................... 57
CCP Timer Resou rce s ................................... ............ 55
Compare
Block Diag ram .............. ..................... ................ 58
Mode ................................................................. 58
Software Interrupt Mode .................................. .. 58
Special Event Trigger ........................................ 58
Special Trigger Output of CCP1 ........................ 58
Special Trigger Output of CCP2 ........................ 58
Interaction of Two CCP Modules . .............................. 55
Section ....................................................................... 55
Special Event Trigger and A/D Conversions ............. 58
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagr a m .............. .......... ........... .............. 58
PWM Mode ............................................................ .... 58
CCP1CON ......................................................................... 17
CCP2CON ......................................................................... 17
CCPR1H Register .................................................. 15, 17, 55
CCPR1L Regist e r .... ..................... ..................... .......... 17, 55
CCPR2H Register ........................................................ 15, 17
CCPR2L Regist e r .... ..................... ..................... .......... 15, 17
CCPxM0 bit ........................................................................ 56
CCPxM1 bit ........................................................................ 56
CCPxM2 bit ........................................................................ 56
CCPxM3 bit ........................................................................ 56
CCPxX bit .......................................................................... 56
CCPxY bit .......................................................................... 56
CKE ................................................................................... 62
CKP ................................................................................... 63
Clock Polarity Select bit, CKP ............................................ 63
Code Examples
Call of a Subroutine in Page 1 from Page 0 .............. 26
Indirect Addressing .................................................... 27
Code Protection ......................................................... 95, 110
Computed GOTO ............................................................... 26
Configuration Bits .............................................................. 95
Conversi on Cons id e ratio n s ......... ..................... ................ 157
D
D/A ..................................................................................... 62
Data Memor y ............. .......... ........... ..................... .......... .... 12
Bank Select (RP1:RP0 Bits) ...................... .............. .. 12
General Purpose Registers ................................. ...... 12
Register File Map ...... ........... ..................... .......... 13, 14
Special Function Registers ........................................ 15
Data/Address bit, D/A ........................................................ 62
DC Characteristics ........................................................... 127
Development Support ...................................................... 119
Device Differences .............. ............................................. 157
Device Overview .................................................................. 5
Direct Add ressing ........................... .......... ..................... .... 27
E
Electrical Characteristics .... ............................................. 125
Errata ................................................................................... 4
Extern a l Cl o ck In put (R A4 / T 0 C KI ). See Timer0
External Interrupt Input (RB0/INT). See Interrupt Sources
PIC16F7X
DS30325A-page 160 Advance Information 2000 Microchip Technology Inc.
F
Firmware Instructions .......................................................111
FSR Register ....................................................15, 16, 17, 27
I
I/O Ports ....... ..................... ........... .......... ........... .......... .......29
I2CAddressing .................................................................68
Block Diag ram ........... ........... ..................... .................67
I2C Operation .............................................................67
Master Mode ..............................................................71
Mode ..........................................................................67
Mode Selection ..........................................................67
Multi-Master Mode .....................................................71
Reception ...................................................................69
Reception Tim i n g Diagra m ...... ..................................69
SCL and SDA pins . ....................................................67
Slave Mode ................................................................67
Transmis sion ..............................................................70
I2C (SSP Module)
Timing Diag ram, Data ................ ..............................141
Timing Diagram, Start/Stop Bits ...............................140
ID Locations ...............................................................95, 110
In-Circuit Serial Programming (ICSP) ........................95, 110
INDF ................................................................................... 17
INDF Register ........................................................15, 16, 27
Indirect Addressing ............................................................27
FSR Register .............................................................12
Instruction Format ............................................................111
Instruction Set ..................................................................111
ADDLW ....................................................................113
ADDWF .................................................................... 113
ANDLW ....................................................................113
ANDWF .................................................................... 113
BCF ..........................................................................113
BSF ..........................................................................113
BTFSC .....................................................................114
BTFSS .....................................................................114
CALL ........................................................................114
CLRF ........................................................................114
CLRW ......................................................................114
CLRWDT ..................................................................114
COMF ......................................................................115
DECF .......................................................................115
DECFSZ ...................................................................115
GOTO ......................................................................115
INCF .........................................................................115
INCFSZ ....................................................................115
IORLW .....................................................................116
IORWF .....................................................................116
MOVF .......................................................................116
MOVLW ...................................................................116
MOVWF ...................................................................116
NOP .........................................................................116
RETFIE ....................................................................117
RETLW ....................................................................117
RETURN ..................................................................117
RLF ..........................................................................117
RRF ..........................................................................117
SLEEP .....................................................................117
SUBLW ....................................................................118
SUBWF ....................................................................118
SWAPF ....................................................................118
XORLW .................................................................... 118
XORWF ....................................................................118
Summary Ta b l e ... .......... ........... ..................... ..........112
INT In t e rr u pt (RB0/INT ). See Interrupt Sources
INTCON ............................................................................. 17
INTCON Register ............................................................... 20
GIE Bi t ................. .......... ........... .......... ........... .......... .. 20
INTE Bit ......................................................... 20, 21, 22
INTF Bit ............ ........... .......... ..................... ........... .... 20
RBIF Bit ......................................................... 20, 21, 31
T0IE Bi t ................ ..................... .......... ........... .......... .. 20
Internal Sampling Switch (Rss) Impedance ....................... 92
Interrupt Sources ....................................................... 95, 105
Block Diag ram .......................... ..................... .......... 10 5
Interrupt on Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ...................................... 7, 8, 106
TMR0 Overflow ........................................................ 106
USART Receive/Transmit Co mplete ......................... 73
Interrupts
Synchronous Serial Port Interrupt .............................. 22
Interrupts, Co ntext Saving During .................................... 106
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ....................... 20, 105
Interrupt on Change (RB7:RB4) Enable (RBIE Bit) . 106
RB0/INT Enable (INTE Bit) ............................ 20, 21, 22
TMR0 Overflow Enable (T0IE Bit) ............................. 20
Interrupts, Flag Bits
Interrupt on Change (RB7:RB4) Flag (RBIF Bit) . 20, 21,
31, 106
RB0/INT Flag (INTF Bit) ............................................ 20
TMR0 Overflow Flag (T0IF Bit) ................................ 106
K
KeeLoq Evaluation and Programm ing Tools ................ 122
L
Loading of PC ......... ....... .... .. .. .. .... .. ....... .. .... .. .. .. ....... .... .. .. .. 26
M
Master Clear (MCLR) .......................................................7, 8
MCLR Reset, Normal Operation ............... . 99, 101, 102
MCLR Reset, SLEEP ................................. 99, 101, 102
Memory Organization
Data Memor y ............. .......... ........... ..................... ...... 12
Program Memory ....................................................... 11
MPLAB Integrated Development Environment Software . 119
O
OPCODE Field Desc r i p tions ............. .......... ..................... 111
OPTION ............................................................................. 17
OPTION_R EG Re g i ster ............... ..................... ........... ...... 19
INTEDG Bit ..... ........... .......... ........... .......... ........... ...... 19
PS2:PS0 Bits ............................................................. 19
PSA Bit ................................................................ 19, 20
RBPU Bit .......... ........... .......... ..................... ........... .... 19
T0CS Bit .................................................................... 19
T0SE Bit ....... ........... ..................... .......... ................... 19
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin .........................................................7, 8
Oscillato r Configurat ion ....... ........ ............. ............. ...... 95, 97
HS ...................................................................... 97, 101
LP ...................................................................... 97, 101
RC ............................................................... 97, 98, 101
XT ......................................................................97, 101
Oscillator, WDT ................................................................ 107
Output o f TMR2 ................... ..................... .......... ............... 53
2000 Microchip Technology Inc. Advance Information DS30325A-page 161
PIC16F7X
P
P .........................................................................................62
Packaging ........................................................................149
Pagin g , Pr o gram Memory .............. ........... .......... .........11, 26
Parallel Slave Port (PSP ) .........................................9, 34, 38
Block Diag ram ........ ..................... ..................... ..........38
RE0/RD/AN5 Pin ..............................................9, 37, 38
RE1/WR/AN6 Pin .............................................9, 37, 38
RE2/CS/AN7 Pin ..............................................9, 37, 38
Read Waveforms .......................................................39
Select (P SPMODE Bit ) ........ ........... .......... .....34, 35, 38
Write Waveforms .......................................................39
PCFG0 bit .......................... .......... ........... ..................... ......90
PCFG1 bit .......................... .......... ........... ..................... ......90
PCFG2 bit .......................... .......... ........... ..................... ......90
PCL Register ........ ............................................15, 16, 17, 26
PCLATH Register .............. ..................... .........15, 16, 17, 26
PCON Register ....................................................17 , 25, 100
POR Bit ......................................................................25
PIC16F76 Pinout Description ........................ .... ........... .... ....7
PICDEM-1 Low-Cost PICmicro Demo Board ...................121
PICDEM-2 Low-Cost PIC16CXX Demo Board ................121
PICDEM-3 Low-Cost PIC16CXX X Demo Boar d ..............121
PICSTART Plus Entry Level Development System ......121
PIE1 Register ...............................................................17, 21
PIE2 Register ...............................................................17, 23
Pinout Descriptions
PIC16F73/PIC16F76 ....................................................7
PIC16F74/PIC16F77 ....................................................8
PIR1 Regi ster ............... .......... ..................... ........... ............22
PIR2 Regi ster ............... .......... ..................... ........... ............24
POP ...................................................................................26
POR. See Power-on Reset
PORTA .......................................................................7, 8, 17
Analog Port Pins ......................................................7, 8
Initialization ................................................................ 29
PORTA Register ........................................................29
RA3 RA0 and RA5 Port Pins .....................................29
RA4/T0CKI Pin ...................................................7, 8, 29
RA5/SS/AN4 Pin .......... .......... ..................... ........... ..7, 8
TRISA Register ..........................................................29
PORTA Register ................................................................15
PORTB .......................................................................7, 8, 17
PORTB Register ........................................................31
Pull-up Enable (RBPU Bit) ........................ ........... ......19
RB0/INT Edge Select (INTEDG Bit) . ..........................19
RB0/INT Pin, External ......................................7, 8, 106
RB3:RB0 Port Pins ................................... .................31
RB7:RB4 Interrupt on Change .................................106
RB7:RB4 Interrupt on Change Enable (RBIE Bit) ....106
RB7:RB4 Interrupt on Change Flag (RBIF Bit) ...20, 21,
31, 106
RB7:RB4 Port Pins ................................... .................31
TRISB Register ..........................................................31
PORTB Register ................................................................15
PORTC ......................................................................7, 8, 17
Block Diag ram ........ ..................... .......... .....................33
PORTC Register ........................................................33
RC0/T1OSO/T1CKI Pin ....... ........... ..................... ....7, 8
RC1/T1OSI/CCP2 Pin ..............................................7, 8
RC2/CCP1 Pin .........................................................7, 8
RC3/SCK/SCL Pin .................................... ...............7, 8
RC4/SDI/SDA Pin ....................................................7, 8
RC5/SDO Pin ......................... ..................... .............7, 8
RC6/TX/CK Pin .................................................. 7, 8, 74
RC7/RX/DT Pin ........................................... 7, 8, 74, 75
TRISC Regist e r ..... ..................... ..................... .... 33, 73
PORTC Register ................................................................ 15
PORTD .................................................................... 9, 17, 38
Block Diag ram .................. ..................... .................... 34
Parallel Slave Port (PSP) Function ............................ 34
PORTD Register ........................................................ 34
TRISD Regist e r ..... ..................... ..................... .......... 34
PORTD Register ................................................................ 15
PORTE .......................................................................... 9, 17
Analog Port Pins .............................................. 9, 37, 38
Block Diag ram .................. ..................... .................... 35
Input Buffer Full Status (IBF Bit) ................................ 36
Input Buffer Overflow (IBOV Bit) ................................ 36
PORTE Register ........................................................ 35
PSP Mode Select (PSPM OD E Bit) ................ 34, 35, 38
RE0/RD/AN5 Pin ............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................ 9, 37, 38
RE2/CS/AN7 Pin ............................................. 9, 37, 38
TRISE Register .......................................................... 35
PORTE Register ................................................................ 15
Postscaler, WDT
Assignment (PSA Bit) .......................................... 19, 20
Rate Select (PS2:P S0 Bits) ....................................... 19
Power-down Mode. See SLEEP
Power-on Reset (POR) ........................ 95, 99, 100, 101, 102
Oscillator Start-up Timer (OST) ................... ...... 95, 100
POR Status (POR Bit) ................ ........... .......... .......... 25
Power Control (PCON) Register .............................. 100
Power-down (PD Bit) ................................................. 99
Power-up Timer (PWRT) ................................... 95, 100
Time-out (TO Bit) ................................................. 18, 99
Time-out Sequence on Power-up .................... 103, 104
PR2 .................................................................................... 17
PR2 Register ............................................................... 16, 53
Prescaler, Timer0
Assignment (PSA Bit) .......................................... 19, 20
Rate Select (PS2:P S0 Bits) ....................................... 19
PRO MA TE II Universal Programmer ........................... 121
Program Counter
Reset Conditions ........... ....... .... .. .... .. ......... .. .... .. .... .. 101
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging ................................................................. 11, 26
Program Memory Map ............................................... 11
Reset Vec to r ...... ..................... .......... ..................... .... 11
Program Verification ........................................................ 110
Programming Pi n (Vpp ) ..... ........... ..................... .......... .... 7, 8
Programming, Device Instructions ................................... 111
PUSH ................................................................................. 26
R
R/W .................................................................................... 62
R/W bit ................................................................... 68, 69, 70
RAM. See Data Me mory
RCREG .............................................................................. 17
RCSTA Regist e r .... ..................... .......... ..................... .. 17, 74
OERR Bit ................................................................... 74
SPEN Bit .................................................................... 73
SREN Bit ........... .......... ........... ..................... .......... .... 74
Read/Write bit Information, R/W ........................................ 62
Receive Ove rflow Indicator bi t, SSPOV .... ..................... .... 63
Register File .................................. .......... ..................... ...... 12
Register File Map ....................................................... .. 13, 14
PIC16F7X
DS30325A-page 162 Advance Information 2000 Microchip Technology Inc.
Registers
FSR Summary ............................................................17
INDFSummary ............................................................17
INTCON
Summary ............................................................17
OPTION
Summary ............................................................17
PCL Summary ............................................................17
PCLATH
Summary ............................................................17
PORTB
Summary ............................................................17
SSPSTAT ...................................................................62
STATUS
Summary ............................................................17
Summary ....................................................................15
TMR0
Summary ............................................................17
TRISB
Summary ............................................................17
RESET .........................................................................95, 99
Reset
Block Diag ram ........... ........... ..................... .................99
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers ...........................102
Reset Conditions for PCON Register .......................101
Reset Conditions for Program Counter ....................101
Reset Conditions for STATUS Register ...................101
WDT Reset. See Watchdog Timer (WDT)
Revision History ...............................................................157
S
S .........................................................................................62
SCI. See USART
SCL ....................................................................................67
Serial Communication Interface. See USART
Slave Mode
SCL ............................................................................ 67
SDA ............................................................................67
SLEEP ..................................................................95, 99, 108
SMP ...................................................................................62
Softwa re Simulator (MPLAB-SIM) ...... ........... ...................120
SPBRG ...............................................................................17
SPBRG Register ................................................................16
Speci a l Feat u res of the CPU ...... ............................... .........95
Special Function Registers ................................................15
PIC16F73 ...................................................................15
PIC16F74 ...................................................................15
Speed, Operating ........................... .. .. .... ....... .. .. .... .. .. .. ....... ..1
SPI Block Diagra m ......... ..................... ..................... .........64
Master Mode Timing ..................................................65
Serial Clock ................................................................61
Serial Data In .............................................................61
Serial Data Out ..........................................................61
Slave Mode Timing ....................................................65
Slave Mode Timing Diagram ......................................65
Slave Select ...............................................................61
SPI Mode ...................................................................61
SSPCON .................................................................... 63
SSPSTAT ...................................................................62
SPI Clock Edge Select bit, CKE ........................................ 62
SPI Data Input Sample Phase Select bit, SMP . ... ............. 62
SSP Module Overview ....................................................... 61
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ....... ............................................7, 8
RC4/SDI/SDA Pin .................................................... 7, 8
RC5/SDO Pin ...........................................................7, 8
Section ....................................................................... 61
SSPCON ................................................................... 63
SSPSTAT .................................................................. 62
SSPADD Regist er ..... ........... ............................... ............... 17
SSPBUF ............................................................................ 17
SSPBUF Register .............................................................. 15
SSPCON ............................................................................ 63
SSPCON Register .............................................................15
SSPEN ............................................................................... 63
SSPIF ................................................................................ 22
SSPM3:SSPM0 ................................................................. 63
SSPOV ........................................................................ 63, 67
SSPSTAT Register ................................................ 16, 17, 62
Stack .................................................................................. 26
Overflows ................................................................... 26
Underflow .................................................................. 26
Start bi t, S ..... .......... ..................... ........... ..................... ...... 62
STATUS Regi ster ..... ..................... ..................... ......... 17, 18
DC Bit .................................................................. 18, 36
IRP Bit ............ ........... .......... ........... .......... ................. 18
PD Bit ........................................................................ 99
TO Bit .................................................................. 18, 99
Z Bit ........ ..................... .......... ........... .......... ......... 18, 36
Stop bit, P ................. ........... ..................... .......... ........... .... 62
Synchronous Serial Port Enable bit, SSPEN ..................... 63
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits, SSPM3:SS PM 0 .
63
Synchronous Serial Port Module ....................................... 61
Synchronous Serial Port Status Register .......................... 62
T
T1CKPS0 bit ...................................................................... 49
T1CKPS1 bit ...................................................................... 49
T1CON ............................................................................... 17
T1CON Registe r .................. ..................... ................... 17, 49
T1OSCEN bit .......... ........... ..................... ..................... ...... 49
T1SYNC bit ........................ .......... ..................... ........... ...... 49
T2CKPS0 bit ...................................................................... 53
T2CKPS1 bit ...................................................................... 53
T2CON Registe r .................. ............................... ......... 17, 53
TAD ..................................................................................... 93
Timer0
Clock Source Edge Select (T0SE Bit) ....................... 19
Clock Source Select (T0CS Bit) ................................. 19
Overflow Enable (T0IE Bit) .................................. .... .. 20
Overflow Fla g (T0IF Bit) ......... ........... .......... .............10 6
Overflow In terrupt .... ..................... .......... ................. 106
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ................................................................................ 49
RC0/T1OSO/T1CKI Pin ............ .......... ..................... 7, 8
RC1/T1OSI/CCP2 Pin ............................................. 7, 8
Timers
Timer0
External Clock ................................................... 46
Interrupt ............................................................. 45
Prescaler ........................................................... 46
Prescaler Block Diagram ................................... 45
2000 Microchip Technology Inc. Advance Information DS30325A-page 163
PIC16F7X
Section ...............................................................45
T0CKI .................................................................46
Timer1
Asynchronous Counter Mode ............................51
Capacitor Selection ........................... ......... .... ....51
Operation in Timer Mode .............. .... .. ....... .. .... ..50
Oscillator ............................................................51
Prescaler ............................................................51
Resetting of Timer1 Registers ...........................51
Resetting Timer1 using a CCP Trigger Output ..51
Synchronized Counter Mode .............................50
T1CON ...............................................................49
TMR1H ..............................................................51
TMR1L ............................................................... 51
Timer2
Block Diag ram ............... ..................... ...............53
Postscaler .......................................................... 53
Prescaler ............................................................53
T2CON ...............................................................53
Timing Diagrams
Brown-out Reset ......................................................134
Capture/Compare/PWM ...........................................136
CLKOUT and I/O ......................................................133
I2C Recepti o n (7 - bit Address) ........... ..................... ....69
Power-up Timer ............................ ..................... ......134
Reset ........................................................................134
SPI Master Mode .......................................................65
SPI Slave Mode (CKE = 1) ........................................65
SPI Slave Mode Timing (CKE = 0) ............................65
Start- u p Timer ........ ..................... .......... ...................134
Time-out Sequence on Power-up ......... .... .. .....103, 104
Timer0 ......................................................................135
Timer1 ......................................................................135
USART Asynch ronous Mas ter Transm ission .............78
USART Asynchronous Reception ..............................79
USART Synchronous Receive .................................143
USART Synchronous Reception ................................85
USART Synchronous Tran smiss ion ..................83, 143
Wake - u p from SL EEP via In terru p t ........ ...... ..... ...... .1 0 9
Watchdog Timer ............... .. .... ....... .. .... .. .. .... ....... .. .. ..134
Timing Diagrams and Specifications
A/D Conversion ......................... ..................... ..........145
I2C Bus Data ............................................................141
I2C Bus Start/Stop Bits .............................................140
TMR0 .................................................................................17
TMR0 Register ...................................................................15
TMR1CS bit ...... ..................... ..................... ........... ............49
TMR1H ...............................................................................17
TMR1H Register ................................................................15
TMR1L ...............................................................................17
TMR1L Register .................................................................15
TMR1ON bit .......................................................................49
TMR2 .................................................................................17
TMR2 Register ...................................................................15
TMR2ON bit .......................................................................53
TOUTPS0 bit ......................................................................53
TOUTPS1 bit ......................................................................53
TOUTPS2 bit ......................................................................53
TOUTPS3 bit ......................................................................53
TRISA ................................................................................17
TRISA Register ..................................................................16
TRISB ................................................................................17
TRISB Register ..................................................................16
TRISC ................................................................................17
TRISC Register ... ..................... ..................... .....................16
TRISD ................................................................................ 17
TRISD Regist e r ............ ..................... ..................... ............ 16
TRISE ................................................................................ 17
TRISE Register ............................................................ 16, 35
IBF Bit ....... ........... .......... ........... .......... ..................... .. 36
IBOV Bit ..................................................................... 36
PSPMODE Bit ............................................... 34, 35, 38
TXREG .............................................................................. 17
TXSTA ............................................................................... 17
TXSTA Regi ster ................. ..................... ........... .......... ...... 73
SYNC Bit ............................ ..................... ............ 73, 74
TRMT Bit ....... ..................... ..................... .......... ........ 73
TX9 Bit ....................................................................... 73
TX9D Bit .................................................................... 73
TXEN Bit ........ .......... ........... .......... ........... .......... .. 73, 89
U
UA ...................................................................................... 62
Universal Synchronous Asynchronous Re ceiver Transmitter.
See USART
Update Address bit, UA ........................ .... .. ......... .. .... .. .... .. 62
USART .............................................................................. 73
Asynchronous Mode . ................................................. 77
Receive Block Diagram ................. .................... 81
Asynchronous Receiver ............................................. 79
Asynchronous Receptio n . .......................................... 80
Asynchronous Tra nsmit ter ......................................... 77
Baud Rate Generator (BRG) . .................................... 75
Baud Rate Formula ........................................... 75
Baud Rates, Asynchronous Mode (B RG H=0) ... 7 6
Sampling ........................................................... 75
Mode Select (SYNC Bit) ...................................... 73, 74
Overrun Error (OERR Bit) .......................................... 74
RC6/TX/ CK Pin .............. ........... ..................... .......... 7, 8
RC7/RX/DT Pi n ..... ........... ..................... .................. 7, 8
RCSTA Regist e r ...... ........... .......... ..................... ........ 74
Receive Block Diagram .................. ..................... ...... 79
Serial Port Enable (SPEN Bit) ................................... 73
Single Receive Enable (SREN Bit) ............................ 74
Synchronous Master Mode ...................................... .. 82
Synchronous Master Reception ................................ 84
Synchronous Master Transmission ........................... 82
Synchronous Slave Mode .......................................... 86
Transmit Block Diagram ............................................ 77
Transmit Data, 9th Bit (TX9D) ...... ............................. 73
Transmit Enable (TXEN Bit) ................................ 73, 89
Transmit Enable, Nine-bit (TX9 Bit) ........................... 73
Transmit Shift Register Status (T RMT Bit) .... ............ 73
TXSTA Regi ster ........... ........... .......... ........... .......... .... 73
W
Wake-up from SLEEP ................................................ 95, 108
Interrupts ......................................................... 101, 102
MCLR Reset ...... ..................... ..................... .......... .. 102
Timing Dia g ram .................. ..................... ................ 109
WDT Reset ........ ..................... ..................... ............ 102
Watchdog Timer (WDT) ............................................. 95, 107
Block Diag ram .................. ..................... .................. 107
Enable (WDTE Bit) .................................................. 107
Postscaler. See Postscaler, WDT
Program min g Con side ration s .................................. 107
RC Oscillator ........................................................... 107
Time-o u t Pe riod ........... ........... .......... ........... .......... .. 107
WDT Reset, Normal Operation ................ .. 99, 101, 102
WDT Reset, SLEEP .................................. 99, 101, 102
WCOL ................................................................................ 63
2000 Microchip Technology Inc. Advance Information DS30325A-page 165
PIC16F7X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
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from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
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The file transfer site is available by using an FTP ser-
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The web site and file transfer site provide a variety of
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All other trademarks mentioned herein are the property of
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000815
PIC16F7X
DS30325A-page 166 Advance Information 2000 Microchip Technology Inc.
READER RESPONSE
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DS30325A
PIC16F7X
1. What are t he best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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2000 Microchip Technology Inc. Advance Information DS30325A-page 167
PIC16F7X
PIC16F7X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F7X(1), PIC16F7XT (1); VDD range 4.0V to 5.5V
PIC16LF7X(1), PIC16LF7XT(1); VDD range 2.0V to 5.5V
Temp er ature Rang e I = -40°C to +85°C (Industrial)
Package PT = T QFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic dip
P=PDIP
L=PLCC
SS = SSOP
Pattern QTP, SQTP, Code or Special Requirements
(blank oth erwis e )
Examples:
a) PIC16F77-I/P 301 = Commercial temp., PDIP
package, normal VDD limits, QTP pattern #301.
b) PIC16LF76-I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
c) PIC16F74-I/P = Industrial temp., PDIP pack-
age, normal VDD limits.
Note 1: F = CMOS FLASH
LF = Low Power CMOS FLASH
T = in tape and reel - SOIC, PLCC,
SSOP, TQFP packages only.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
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rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS30325A-page 168 Advance Information
2000 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 3/01 Printed on recycled paper.
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2000 Microchip Technology Inc. Advance Information DS30325A-page 1
PIC16F7X
1.0 Device Overview............................................................................................................................................................ 5
2.0 Memory O rganization .................................................................................................................................................. 11
3.0 I/O Ports...... .......... ........... .......... ..................... ........... .......... ........... ..................... ........................................................ 29
4.0 Reading Program Memory......................................... .. .... .... ......... .... .. .... .... ......... .. .... .... ......... ..................................... 41
5.0 Timer0 Module. ............................................................................................................................................................ 45
6.0 Timer1 Module. ............................................................................................................................................................ 49
7.0 Timer2 Module. ............................................................................................................................................................ 53
8.0 Capture/Compare/PWM Modules.................................... .... ......... .. .... .... .. ......... .. .... .... .. ......... .... ................................. 55
9.0 Synchronous Serial Port (SSP) Module....................................................................................................................... 61
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)...................................................................... 73
11.0 Analog-to-Digital Converter (A/D) Module. .................................................................................................................. 89
12.0 Special Featur e s of the CPU.................. ..................... ..................... .......... ..................... ............................................ 95
13.0 Instruction Set Summary ........................................................................................................................................... 111
14.0 Development Support................................................................................................................................................ 119
15.0 Electrical Characteristics ........................................................................................................................................... 125
16.0 DC and AC Characteristics Graphs and Tables...... .. .... .... .. ......... .... .. .... .. ......... .... .. .... .... ....... .... .. .... ......................... 147
17.0 Packaging Infor mation..... ..................... .......... ..................... ........... ..................... .......... ............................................ 149
Revision History 157
Device Differences 157
Conversion Considerations 157
................................................................................................................................................................. ....... .... .. ...On-Line Support165
•............................................................................................................................................................................. Reader Respons e166
........................................................................................................................................... PIC16F7X Product Identification System167
PIC16F7X
DS30325A-page 2 Advance Information 2000 Microchip Technology Inc.
