ky, SGS-THOMSO ST. Ses THOMSON MK45H01,02,03 MK45H11,12,13 VERY FAST CMOS 512/1K/ 2K x 9 BIPORT FIFO = FIRST-IN-FIRST-OUT MEMORY BASED ARCHITECTURE FLEXIBLE x 9 ORGANIZATIONS: ~ MK45H01,11 (512 x 9) MK45H02, 12 (1K x 9) MK45H03,13 (2K x 9) = LOW POWER, HIGH SPEED HCMOS TECH- NOLOGY ASYNCHRONOUS AND SIMULTANEOUS READ/WRITE FULLY EXPANDABLE IN WORD WIDTH AND DEPTH EMPTY AND FULL WARNING FLAGS RETRANSMIT CAPABILITY HALF-FULL FLAG IN SINGLE DEVICE MODE DESCRIPTION The MK45H01,11,02,12,03,13 are BIPORT FIFO memories from SGS-THOMSON Microelectronics, which utilize special two-port memory cell tech- niques. Specifically, these devices implement a First-In-First-Out (FIFO) algorithm, featuring asyn- chronous read/write operations, full, empty, and half full status flags, and unlimited expansion ca- pability in both word size and depth. The full and empty flags are provided to prevent data overflow and underflow. PIN NAMES Ww Write R Read RS Reset DO-D8 Data Inputs Q0-Q8 Data Outputs FURT First Load / Retransmit xt Expansion Input XO/HF Expansion Output / Half-full Flag FF Full Flag EF Empty Flag Vec, GND 5 Volts, Ground NC Not Connected February 1992 28 1 PDIP28 (N) PSDIP28 (N) PLCC32 (K) Figure 1. Pin Connections wd sh Voc D8 g 2 271 D4 D3. q3 26 ff D5 D2 44 25 1 06 DIigis 24 7} D7 DOW 6 23 1 FL/RT xXig7 22 1 RS FF da MK45HXX 2) EF Qo f 9 20 1 XO/HF Q1q 10 19 1] Q7 Q2 91 18 7 Q6 Q3 q 12 171 Q5 a8 q 13 16 1 Q4 GND Q 14 is DR zoo OND el S 4\ 2 25 COO oo Troe al 8 aalaal 1/16 821MK45H01,11,02,12,03,13 Figure 2. Block Diagram 9 9 Dg Dg | 99 % INPUT | OUTPUT BUFFER | BUFFER _ WRITE WRITE x9 READ READ Ww ADDRESS BiPORT ADDRESS rR CONTROL POINTER MEMORY ARRAY POINTER CONTROL FLAG LoGic _ FF . EF EXPANSION L _ = oaic XO/HF x. _ | - RS RESET/RETRANSMIT RT LoGic vRoo0g62 DESCRIPTION (Continued) The data is loaded and emptied on a first-in-first-out basis, and the latency for retrieval of data is ap- proximately one load (write) cycle. These devices feature a read/write cycle time of only 35ns (28.5MHz). The reads and writes are internally sequential through the use of separate read and write pointers in a ring counter fashion. Therefore, no address information is required to load or unload data. Data is loaded and unloaded with the use of W (write), and R (read) input pins. Separate data in (DO-D8) and data out (Q0-Q8) pins allow simultaneous and asynchronous read/write operations, provided the status flags are not protecting against data under- flow or overflow. The main application of these devices is a buffer for sourcing and absorbing data at different rates (e.g., interfacing fast processors and slow periphe- rals). The MK45HX1, MK45HX2, and MK45HX3 incor- porate 9-bit wide data arrays that provide for support control or parity bit functions. This feature is helpful in data communications where the extra parity bit is used for transmission and reception error checking. These devices also offer retransmit (RT) and half-full features in single device or width expansion modes. The retransmit function allows 2/16 822 ky7_ SGS-THOMSON Tf, menor sciromsies data to be re-read by resetting the read pointer while not disturbing the write pointer. This is for applications where the FIFO is not full, or is written with less than 512, 1024, or 2048 words. FUNCTIONAL DESCRIPTION Unlike conventional shift register based FIFOs, the MK45HX1, MK45HX2, and MK45HX3 employ a memory-based architecture wherein a byte written into the device does not ripple through. Instead, a byte written into the device is stored in a specific location, where it remains until over-written. The byte can be read and re-read as often as desired in the single device configuration. Two internal pointers (ring counters) automatically generate the addresses required for each write and read operation. The empty/full flag circuit prevents illogical operations, such as reading un-written bytes (reading while empty) or over-writing un-read bytes (writing while full}. Once a byte stored at a given address has been read, it can be over-writ- ten. The address pointers automatically loop back to address zero after reaching the final address in the FIFO (512, 1024, or 2048). The empty, half full, and full status of the FIFO is therefore a function of the distance between the pointers, not of their absolute location.FUNCTIONAL DESCRIPTION (Continued) As long as the pointers do not catch one another, the FIFO can be written and read continuously without ever becoming full or empty. Resetting the FIFO simply resets the write and read pointers to location zero. Pulsing retransmit resets the read address pointer without effecting the write address pointer. With conventional FIFOs, implementation of a larger FIFO is accomplished by cascading individ- ual FIFOs. The penalty of cascading is often unac- ceptable ripple through delays. The MK45HX1, MK45HX2, and MK45HX3 allow implementation of very large FIFOs with no timing penalties. The memory-based architecture of the device allows the connection of the read, write, data in, and data out lines of the device in parallel. The write and read control circuits of the individual FIFOs are then automatically enabled and disabled through the expansion-in and expansion-out pins. Figure 3. Write and Full Flag Waveforms MK45HO01,11,02,12,03,13 WRITE MODE The MK45HXx initiates a Write Cycle (see Figure 3) on the falling edge of the Write Enable control input (W), provided that the Full Flag (FF) is not set. Data set-up and hold-time requirements must be satisfied with respect to the rising edge of W. The data is stored sequentially and independent of any ongoing Read operations. FF is set during the last valid write as the MK45H03 becomes full. Write operations begun with FF low are inhibited. FF will go high tace after completion of a valid READ operation. FF will again go low twrr from the begin- ning of a subsequent WRITE operation, provided that a second READ has not been completed (see Figure 5). Writes beginning trrw after FF goes high are valid. Writes beginning after FF goes low and more than twr; before FF goes high are invalid (ignored). Writes beginning less than twe; before FF goes high and less than trrw later may or may not occur (be valid), depending on the internal flag status. LAST VALID WRITE INVALID WRITE =| NOT FULL 7 | = tDH ts ~ o 8 iN INDETERMINANT FIRST VALID WRITE WRITE NOT FULL VALID DATA VALID DATA IN IN VROCO953 ky SGS-THOMSON V7, menoescTromes 3/16 823MK45H01,11,02,12,03,13 Write and Full Flag AC Operating Conditions (0C < Tas +70C, Voc = +5V + 10%) Symbol Parameter 75 38 0 8 2 Unit | Note Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. two Write Cycle Time 35 45 65 80 140 ns twew Write Pulse Width 25 35 50 65 120 ns 1 twr Write Recovery Time 10 10 15 15 20 ns tos Data Set Up Time 15 18 30 30 40 ns toH Data Hold Time 0 0 0 0 0 ns twre W Low to FF Low 25 35 45 60 60 | ns | 2 trFw FF High to Valid Write 10 10 10 10 10 ; ns 2 tRFF R High to FF High 25 35 45 60 60 | ns 2 twer | Wate Protect 10 10 10 10 10 ns | 2 Notes: 1. Pulse widths less than minimum values are not allowed 2. Measured using equivalent output load circuit READ MODE The MK45HXxX initiates a Read Cycle (see Fig- ure 4) on the falling edge of Read Enable con- trol input (R), provided that the Empty Flag (EF) is not set. In the read mode of operation, the MK45HOX provides fast access to data from 9 of the locations in the static storage array. The data is accessed on a FIFO basis independent of any on-going WRITE operations. After R goes high, data outputs will return to a high impedance condition until the next read oper- ation. In the event that all data has been read from the FIFO, the EF will go low, and further Figure 4. Read and Empty Flag Waveforms READ operationswillbeinhibited(thedatainputs will remain in high impedance). EF will go high twer after completion of a valid WRITE operation. EF will again go low trer from the beginning a subsequent read operation, provided that a second WRITE has not been completed (see Figure 6). Reads begin- ning terr after EF goes high are valid. Reads begun after EF goes low and more that tap: before EF goes high are invalid (ignored). Reads beginning less than tre: before EF goes high and less then terr later may or may not occur (be valid) depending on internal flag status. FIRST =| FF EMPTY 7 +RPi| INDETERMINANT INVALID VALID WRITE jt WEF NOT EMPTY EMPTY VAGOOSeS 4/16 824 ky SGS-THOMSON 7, incrosecrnomesMK45H01,11,02,12,03,13 Read and Empty Flag AC Operating Conditions (OC < Ta < +70C, Voc = +5V + 10%) -25 -35 -50 -65 -12 | Symbol Parameter Unit | Note Min. | Max. } Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. tre Read Cycle Time 35 45 65 80 140 ns ta Access Time 25 35 50 65 120 | ns 2 trR Read Recovery Time 10 10 15 15 20 ns trew Read Pulse Width 25 35 50 65 120 ns 1 taL R Low to Low Z 0 0 0) 0 0 ns | 2 tov Data Valid from R High 5 5 5 5 5 ns | 2 tanz R High to High Z 18 20 25 25 35 | ns | 2 trer R Low to EF Low 25 35 40 60 60 | ns | 2 terR EF High to Valid Read 10 10 10 10 10 | ns | 2 twer W High to EF High 25 35 45 60 60 | ns 2 Read Protect {RPI Indeterminant 10 10 10 10 10 ns 2 Notes: 1. Pulse widths less than minimum values are not allowed 2. Measured using equivalent output load circuit Figure 5. Read/Write to Full Flag Waveforms TT tRFF FIRST READ = SINCE FULL 7 tFFW re po | = tWFF Ww fl vRO0I012 Figure 6. Write/Read to Empty Flag Waveforms . (WEF FIRST WRITE _ SINCE EMPTY w tEFR EF - tREF i ROOIOT3 5/16 Yi ICT] THOMSON MF. cncromecraomes 825MK45H01,11,02,12,03,13 RESET The MK45HXxX is reset (see Figure 7) whenever the Reset pin (RS) is in the low state. During a reset, both the internal read and write pointers are set to Although neither W or R need be high when RS goes low, both R and W must be high trss before RS goes high, and must remain high trsr after- wards. Refer to the following discussion for the the first location. Reset is required after power up, @quired state of FL/AT and XI during Reset. before a WRITE operation can begin. Figure 7. Reset Waveforms tRSC tRS RS \ I tRSR tRSS we _XXXXXXXXXXXMP a tRSS ROOF BF XO OOOO AIK nee XY XXYXYXYXYXXH LULU XY HYRULE REIL VROGIOI4 Note : HF, EF and FF may change status during Reset, but flags will be valid at tasc. Reset AC Operating Conditions (0C < Ta < +70C, Voc = +5V + 10%) -25 35 -50 65 -12 Symbol Parameter Unit | Note Min. | Max.) Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. trsc Reset Cycle Time 35 45 65 80 140 ns trs Reset Pulse Width 25 35 50 65 120 ns 1 trasR Reset Recovery Time 10 10 15 15 20 ns trass Reset Set Up Time 25 30 30 45 100 ns Note: 1. Pulse widths less than minimum values are not allowed 6/16 kz SGS-THOMSON IF. wicrosectromes 826MK45H01,11,02,12,03,13 RETRANSMIT The MK45HXX can be made to retransmit (re-read previously read data) after the Retransmit pin (RT) is pulsed low (see Figure 8). ARetransmit operation sets the internal read pointer to the first location in the array, but will not affect the position of the write Figure 8. Retransmit Waveforms pointer. R must be inactive tats before RT goes high, and must remain high for tatr afterwards. The Retransmit function is particularly useful when blocks of less than the total FIFO depth are per- formed between Resets. The Retransmit feature is not compatible with Depth Expansion. tRTC tRT RT \ J tRTR tRTS RB AXXXXXXXKXXIOH A AREREE X XXX KKK KKM MMMXXXXXX AAA FLAG VALID VROO101S Note : HF, EF and FF may change status during Retransmit, but flags will be valid at terc. Retransmit AC Operating Conditions (0C < Ta < +70C, Voc = +5V + 10%) -25 -35 -50 -65 -12 Symbol Parameter Unit | Note Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. tate Retransmit Cycle Time 35 45 65 80 140 ns tar Retransmit Pulse Width | 25 35 50 65 120 ns 1 Retransmit trTR Recovery Time 10 10 15 15 20 ns tats Retransmit Set Up Time | 25 30 30 45 100 ns Note: 1. Pulse widths less that minimum values are not allowed L577 SGS-THOMSON TING STF. inicrosectromes 827MK45H01,11,02,12,03,13 SINGLE DEVICE CONFIGURATION Asingle MK45HXX may be used when application requirements are for a depth of the device depth or less. The MK45HXx is placed in the Single Device Configuration mode when the chip is Reset with the Expansion in pin (XI) grounded (see Figure 9). WIDTH EXPANSION Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status Flags (EF and FF) can be detected from any one device. Figure 10 demonstrates an 18-bit word width by using two MK45HXXs. Any word width can be attained by adding additional MK45HXxXs. The half full flag (HF) operates the same as in single device configuration. Figure 9. A Single MK45HXX FIFO Configuration EXPANSION OUT {XO} | WRITE iw (R) READ 9 9 DATA IN MK45HOX _ 7x DATA OUT FULL FLAG (FF) (EF) EMPTY FLAG RESET (RS} (RT) RETRANSMIT EXPANSION IN (XI) VA0NI0I6 Figure 10. A Two Device Width Expansion FIFO Configuration (XO) EXPANSION OUT 18 9 DATA IN / L (w) = WRITE F) _ _ (R) READ FULL FLAG irs) | MK45HOX MK45HOX | (EF) EMPTY FLAG RESET (RT) RETRANSMIT 9 7 18 EXPANSION IN (XI) xi para = = out vRO01017 Note : Flag detection is accomplished by monitoring the FF and EF signals on either (any) device used in the width expansion configuration. Do not connect flag output signals together. 86 {57 SGS-THOMSON S/ A MICROELECTROMICS 828HALF FULL FLAG LOGIC When in single device configuration, the (HF) out- put acts as an indication of a half full memory. After half of the memory is filled, and at the falling edge of the next write operation, the half full flag (HF) will be set low and remain low until the difference between the write pointer and read pointer is less than or equal to one half the total memory. The half full flag (HF) is then reset by the rising edge of the read operation (see Figure 11). Figure 11. Half Full Flag Waveforms MK45H01,11,02,12,03,13 DEPTH EXPANSION (Daisy Chain) The MK45HXX can be easily adapted to applica- tions when the requirements are greater than the individual device word depth. Figure 12 demon- strates Depth Expansion using two MK45HXXs. Any depth can be attained by adding additional MK45HXXs. External logic is needed to generate a composite Full and Empty Flag. This requires the ORing of all the EFs and the ORing of all the FFs (i.e., all must be set to generate the composite FF or EF). HALF-FULL HALF-FULL+1 HALF-FULL w yy N / tRHF R \ L tWHF HF ft VRGO1006 Haif Full Flag AC Operating Conditions (0C < Ta < +70C, Vcc = +5V + 10%) -25 -35 -50 -65 -12 . Symboi Parameter Unit | Note Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. Write Low to Half Full twHr Flag Low 30 35 45 60 60 ns Read High to Half Full TRHF Flag High 30 35 45 60 60 ns Ki SGS-THOMSON 9/16 If, isicrorectRomes 829MK45H01,11,02,12,03,13 The MK45HXX operates in the Depth Expansion configuration after the chip is Reset under the below listed conditions : 1. The first device must be designated by ground- ing the First Load pin (FL). The Retransmit function is not available in the Depth Expansion Mode. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (Xl) pin of the next device. The Half Full Flag (HF) is disabled in this mode. EXPANSION TIMING Figures 13 and 14 illustrate the timing of the Ex- pansion Out and Expansion In signals. Discussion of Expansion Out/Expansion In timing is provided to clarify how Depth Expansion works. Due to the fact that Expansion Out pins are generally con- nected only to Expansion In pins, the user does not need to be concerned with the actual timing in a normal Depth Expanded application unless_ex- treme propagation delays exist between the XO/XI pin pairs. Expansion Out pulses are the identical to the WRITE and READ signals but ; delayed in time by txoL and txou. The Expansion Out signal is propa- gated when the last physical location in the memory array is written and again when it is read (Last Read). This is in contrast to when the Full and Empty Flags are activated, which is in response to writing and reading a last available location. Figure 12. A Two Device Depth Expansion Configuration _ xo _ w R FF EF MK45HOX 8 9 9 DATA OUT DATA IN 7) Vcc FL/RT xi FULL C ewer xo FF | mk45HOx | EF 9 a 7V Fi RS CY an xl = vrooto%a 10/16 {57 SGS-THOMSON SJ. wcnomsctromes 830When in Depth Expansion mode, a given MK45HXxX will begin writing and reading as soon as valid WRITE and READ signals begin, provided FL was grounded at RESET time. A MK45HXxX in Depth Expansion mode with FL high at RESET will not begin writing until after an Expansion In pulse occurs. Figure 13. Expansion Out Waveforms MK45H01,11,02,12,03,13 It will not begin reading until a second Expansion In pulse and the Empty Flag has gone high. Expan- sion In pulses must occur txis before the WRITE and READ signals are intended to enable. Mini- mum Expansion In pulse width, txi, and recovery time, txin, must be observed. WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION vRO0989 Expansion Out AC Operating Conditions (0C < Tas +70C, Voc = +5V + 10%) -25 -35 -50 -65 -12 . Symbol Parameter Unit | Note Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. txoL Expansion Out Low 25 35 40 55 90 | ns txou Expansion Out High 25 35 40 55 90 | ns iy, SGS-THOMSON Wn6 VM. isicrogtectRomes 831MK45H01,11,02,12,03,13 Figure 14. Expansion In Waveforms x! | tXIR tXIS WRITE TO FIRST PHYSICAL w LOCATION xis _| READ FROM FIRST PHYSICAL _ LOCATION R vRO00960 Expansion In AC Operating Conditions (0C < Ta S$ +70C, Voc = +5V + 10%) -25 35 -50 65 -12 Symbo! Parameter Unit | Note Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. t Expansion in Pulse 25 35 45 60 115 ns | 1 xl Width Expansion In txin Recovery Time 10 10 10 10 10 ns txis Expansion In Setup Time} 15 15 15 15 15 ns Note: 1. Pulse widths less than minimum vaiues are not allowed COMPOUND EXPANSION The two expansion techniques described above can be applied together in a straight forward man- ner to achieve large FIFO arrays (see Figure 15). BIDIRECTIONAL APPLICATIONS Applications, which require data buffering between 12/16 s 47. 832 THOMSON MICRORLECTROMICS two systems (each system capable of READ and WRITE operations), can be achieved by pairing MK45HXXs, as shown in Figure 16. Care must be taken to ensure that the appropriate flag is monitored by each system. (i.e., FF is monitored on the device where W is used ; EF is monitored on the device where R is used). Both Depth Expansion and Width Expansion may be used in this mode.Figure 15. Compound FIFO Expansion Configuration MK45H01,11,02,12,03,13 Q0_a8 Q0_aQi7 Q0_a8 Q9_Q17 Q(N-8)_QN a MK45HOX MK45HOX MK45HOX R W,RS I DEPTH EXPANSION I DEPTH EXPANSION r DEPTH EXPANSION BLOCK BLOCK BLOCK DO_Ds D(N-8)_DN D9_D17 | DO_DN D9_DN D18_DN DIN-8)_DN vROvION Figure 16. Bidirectional FIFO Application w, Re FF EF MK45HOX 8 D,0-8 Q0-8 SYSTEM A ( __ - _ SYSTEM B Q,0-8 D,0-8 R MK45HOX Ww A B EF, FF, vroa1020 &57 SGS-THOMSON 13/16 SY, microectRones 833MK45H01,11,02,12,03,13 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit vi Voltage on any Pin Relative to Ground 0.3 to +7 v Ta Operating Temperature 0 to 70 C Tste Storage Temperature 55 to +125 C Pp Power Dissipation 1 Ww lout Output Current 20 mA Note : This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this spefication in not imptied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (0C < Ta < +70C) Symbol Parameter Min. Max. Units Note Vec Supply Voltage 45 5.5 Vv 1 GND Ground 0 0 Vv Vin Logic 1 All Inputs 2 Vec + 0.3 Vv 1,2 Vit Logic 0 All Inputs -0.3 0.8 Vv 1 Notes: 1. All Voltages are referenced to ground 2. Vin = 2.5V on the RS pin for MK45H01,1t, 02,12 DC ELECTRICAL CHARACTERISTICS (0C < Ta<+70C, Voc= +5V+ 10%) Symbol Parameter Min. Max. Units Note lect Average Vcc Power Supply Current 120 mA 1 lec2 nw Standby AR Vn ) 12 mA 1 Ices flepute Dee OM 2 mA 1 Me Input Leakage Current (Any Input) ~1 1 pA 2 lot Output Leakage Current -10 10 pA 3 Vou Output Logic 1 Voltage (lout = -4.0mA) 2.4 v 4 Vor Output Logic 0 Voltage (lout = 8.0mA) 0.4 v 4 Notes : i. Icc measurements are made with outputs open. s Mee ie vs 4. All voltages are referenced to ground. CAPACITANCE (Ta= 25C, f= 1MHz) Symbol Parameter Typ. Max. Unit Note Cy Capacitance on Input Pins 8 pF 1 Co Capacitance on Output Pins 12 pF 1,2 Notes : 1. This parameter is only sampled and not 100% tested 2. Output butfer deselected 14/16 {7 SGS-THOMSON Tf, MICROELECTRONICS 834MK45H01,11,02,12,03,13 AC TEST CONDITIONS Parameter Value Unit Input Levels 0to3 Vv Transition Time 5 ns Input Signal Timing Reference Level 1.5 Vv Output Signal Timing Reference Levels 1.5 and 1.9 Vv Ambient Temperature 0 to 70 C Supply Voltage +10% Vv Figure 17. Equivalent Output Load Circuit ov ] 4700 DEVICE UNDER OUT TEST 2400 mem C= 30pF = Cy includes JIG capacitance VA00614 ky SGS-THOMSON 15/16 Y, MICROELECTROMICS 835MK45H01,11,02,12,03,13 ORDERING INFORMATION Example: MK45H02 N 25 Package | | Speed | N PDIP28 25 25ns and/or PSDIP28 35 35ns K PLOC32 50 50ns 65 65ns 12 120ns For a list of available options of Package and Speed, refer to the Selector Guide in this Data Book or to the current Memory Shortform Catalogue. For further information on any aspect of this device, please contact our Sales Office nearest you. 16/16 G7 SGS-THOMSoN Jf. SGS-THOMSON 836