Features e High speed tg, = 12 os CMOS for optimum speed/power e Low active power $25 mW e Low standby power 275 mW e 2.0V data retention (optional) 100 pW @ Automatic power-down when deselected PRELIMINARY CY7C1007 Functional Description The CY7C1007 is a high-performance CMOS static RAM organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and three-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 65% when deselected. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW, Data on the input pin (Dyn) is written into the memory location specified on the address pins (Ag through 1M x 1 Static RAM Reading from the device is accomplished by taking chip enable (CE) LOW while write enable (WE) remains HIGH. Un- der these conditions, the contents of the memory location specified by the address pins will appear on the data output (Dour) pin. The output pin (Dout) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW). The CY7C1007 is available in standard e TTL-compatible inputs and outputs Ayj9). 300-mil-wide DIPs and SOJs, Logic Block Diagram Pin Configuration a DIP/SOJ <] Din Top View INPUT BUFFER Ay A oa oc ab AO o Ag my = ATW LN 512x 2048 =< sel > [| ARRAY o > D Rms 2 OUT Ay i . i COLUMN DOWN ne DECODER - CE TEETER ERTS OrnNO TH ORD OH ME EEE LE EEKE WE 1007-1 Selection Guide 7C1007-12 7C1007-15 7C100720 7C1007-25 Maximum Access Time (ns} 12 15 20 25 Maximum Operating Current (mA} | Commercial 150 135 125 120 Military 145 135 130 Maximum Standby Current (mA) Commercial 50 40 30 30 Military 40 30 30 3901 North First Street @ SanJose @ CA95134 408-943-2600 November 1991 Revised April 1995 Cypress Semiconductor Corporation PRELIMINARY CY7C1007 Maximum Ratings (Above which the useful life maybe impaired. Foruser guidelines, Static Discharge Voltage ..............00 000 eee >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ..........0000005, 65Cto +150C - Latch-Up Current .......... 0... eer ee rere >200 mA Ambient Temperature with * Power Applied ......ssseeseeeeeeeeees -s5C1o +125 Operating Range Supply Voltage on Vcc Relative to GNDU!) , -0,5V to +7.0V Range Temperatnn 2] Vee DC Voltage Applied to Outputs : 7 ; in High Z Statel) 6... so... eee -0.5V to Vcc + 0.5V Commercial OC to +70C SV + 10% DC Input Voltagel!] ......0......... -0.5V to Vcc + 0.5V Military 55C to +125C 5V + 10% Current into Outputs (LOW) ...............00 ees 20 mA Electrical Characteristics Over the Operating Rangel?) 7C1007-12 | 7C1007-15 | 7C1007-20 | 7C1007-25 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH = | Vcc = Min. Ion = 4.0mA | 2.4 24 2.4 24 V Voltage Voi Output LOW Voc = Min., Ip, = 8.0 mA 0.4 0.4 0.4 0.4 Vv Voltage Vin Input HIGH 2.22 | Veco | 2.2 | Veco | 2.2 | Veo | 22 | Veco | V Voltage +03 +03 +03 +03 VIL Input LOW -03 | 08 | -03]) 08 |-03) 08 | -03] 08 Vv Voltagel!] Ix Input Load GND < V| < Vcc -1 +1 -1 +1 -1 +1 -1 +1 [pA Current loz Output Leakage | GND < V] < Vcc, -5 +5 -5 +5 -5 +5 -5 +5 | WA Current Output Disabled los Output Short Vcc = Max., Vour = GND 300 300 300 300 | mA CircuitCurrentl4 Icc ack Pperating Vcc = Max., Com! 150 135 125 120 | mA nu rrent |J = 0mA, me f= fwax = litpe | Mil 145 135 130 Ispi Automatic CE | Max.. Voc, Com'l 50 40 30 30 | mA Power-Down CE > Vin, Current Vin > Vin or - -TTLInputs | Vn < Viz, Mil 40 30 30 f=f max Isp2 Automatic CE =| Max. Vcc, Com! 2 2 2 2 |mA Power-Down CE > Voc 0.3V, Current Vn= Veco -0.3Vor G7 CMOS Inputs | Vy <03v,f=0 | Mil 2 2 2 Capacitancel5] Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF Veco = 5.0V Cin: Controls 10 pF CouT Output Capacitance 10 pF Notes: 1. Viz (min.} = 2.0V for pulse durations of less than 20 ns. 2. Ty is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing in- formation. 4, Notmorethan 1 output should beshorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.PRELIMINARY CY7C1007 AC Test Loads and Waveforms ourPur we tL , ot 480 4802 R1 4802 A a f z Re 5 pF = Re | [ee | ] 25522 INCLUDING = INCLUDING JIG AND - - JIGAND ~ - SCOPE (a) SCOPE (b) 1007-3 Equivalent to: THEVENIN EQUIVALENT OUTPUT ose? ns 1.73 Switching Characteristics. 4] Over the Operating Range ALL INPUT PULSES 7C1007-12 7C100715 7C100720 7C1007 -25 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 ns tad Address to Data Valid 12 15 20 25 ns toHA Data Hold from Address Change 3 3 3 3 ns tack CE LOW to Data Valid 12 15 20 25 ns tLZcE CE LOW to Low ZI] 3 3 3 3 ns tyzcE CE HIGH to High ZI? 3] 6 7 8 10 ns teu CE LOW to Power-Up 0 0 0 0 ns tpp CE HIGH to Power-Down 12 15 20 25 ns WRITE CYCLEl! tw Write Cycle Time 12 15 20 25 ns tscr CE LOW to Write End 10 12 15 20 ns taw Address Set-Up to Write End 10 12 15 20 ns tHa Address Hold from Write End 0 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 0 ns tpwE WE Pulse Width 10 12 15 20 ns tsp Data Set-Up to Write End 7 8 10 1s ns typ Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low ZI) 3 3 3 3 ns tHZWE WE LOW to High ZI7-5) 6 7 8 10 | ns Notes: 6. Test conditions assume signal transition time of 3 ns or less.timingref- 9. The internal write time of the memory is defined by the overlap of CE erence levels of 1.5V, inputpulse levels of Oto 3.0V, and output loading LOW and WELOW. CE and WE must be LOW to initiate awrite, and of the specified Ig /loy and 30-pF load capacitance. the transition ofany of these signals can terminate the write. The input 7. Atany given temperature and voltage condition, tyzcr is less than data set-up and hold timing should be referenced to the leading edge tizce and tyzwe is less than thzwe for any given device. of the signal that terminates the write. 8 tyzce and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage.PRELIMINARY CY7C1007 Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!) Min. | Max. | Min. | Max. | Unit Vpr Vcc for Data Retention 2.0 2.0 Vv Iccpr Data Retention Current Vcc = Vopr = 2.09, 50 70 pA - - - CE > Vcc 0.39, tcpr) Chip Deselect to Data Retention Time Vin = Vec 0.3V or 0 0 ns tpbl Operation Recovery Time Vin = 0.3V tre tre ns Note: 10. No input may exceed Voc + 05V. Data Retention Waveform DATA RETENTION MODE ?+ Yoo 4.5V Vpp > 2V 4.5V i topp i tp 7 . CLLLLLLLLL XD 1007-5 Switching Waveforms Read Cycle No. 1[11, 12] at tao | ADDRESS * a tan | DATA OUT PREVIOUS DATA VALID KXXKK DATA VALID 1007-6 Read Cycle No, 212, 13] ADDRESS xX Y aa tric 7 CE . 7x nal tace - t Ht {LCE mt tHZCE HIGH HIGH IMPEDANCE 7 IMPEDANCE DATA OUT \ DATA VALID _ ty p {pp supPiy X Ice 50% 50% AK CURRENT NN isp 1007-7 Notes: 11. Device is continuously selected, CE = Vjz. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW,PRELIMINARY CY7C1007 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)l4) at two ADDRESS Y YY to tsa a tsce > CE Ze N / at taw at tus cr i. tpwe a FE MS XX VM a tsp = typ DATA IN DATA VALID DATA OUT HIGH IMPEDANCE 1007-8 Write Cycle No. 2 (WE Controlled)!4) ADDRESS tsp typ DATA IN DATA VALID tuzwe | tLzwe | HIGH IMPEDANCE DATA OUT DATA UNDEFINED FX 1007-9 Note: 14. 1fCEgoes HIGH simultaneously with WE going HIGH, the output re- mains in a high-impedance state. Truth Table CE | WE Dour Mode Power H | X | Highz Power-Down Standby (Isp) L | H | Data Out Read Active (Icc} L | L | HighZ Write Active cc}PRELIMINARY CY7C1007 Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C100712PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C100712VC v21 28-Lead (300-Mil) Molded SO] 15 CY7C100715PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1007-15VC v21 28-Lead (300-Mil) Molded SO} CY7C100715DMB D22 28-Lead (300-Mil) CerDIP Military 20 CY7C100720PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1007-20VC V21 28-Lead (300-Mil) Molded SOF CY7C1007-20DMB D22 28-Lead (300-Mil) CerDIP Military 25 CY7C100725PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C100725VC v21 28-Lead (300-Mil)} Molded SO] CY7C100725DMB D22 28-Lead (300-Mil) CerDIP Military Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups VoH 1, 2,3 READ CYCLE VoL 1, 2,3 tre 7, 8, 9, 10, 11 Vin 1,2,3 taa 7,8, 9, 10,11 VIL Max. 1, 2,3 toHA 7, 8, 9, 10, 11 Ix 1, 2,3 tAcE 7, 8, 9, 10, 11 Ioz 1, 2,3 WRITE CYCLE Toc 1, 2,3 twec 7, 8, 9, 10, 11 Ispi 1, 2,3 tscE 7, 8,9, 10, 11 Isp2 1,2,3 taw 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 Document #: 3800198-B tsa 7, 8, 9, 10, 11 tpwE 7, 8,9, 10, 11 tsp 7, 8, 9, 10, 11 typ 7, 8, 9, 10, 11PRELIMINARY Package Diagrams 28-Lead (300-Mil) CerDIP D22 MILSTD1835 D-15 Config. A PIM Ll , a DIMENSIONS Ih IMCHE> PIiPifififiPiriririr IN we ] f AY 45 )) \ CEI0 14 OOOO Oe NES . - L282 0S MIN BATE PLANE ass Lazo ~2 be Lass se Eh ly ka 3 iy O o 28-Lead (300-Mil) Molded DIP P21 PIN 1 r hh f DIMENSIONS IN INCHET MIN. MAR, { U.250 1270 1 t Teo a a AP i a O02 0,080 1.370 - sic Ta25 SEATING PLANE 280 | | [ee O20 ei ee wef O.1i0 CY7C1007PRELIMINARY CY7C1007 Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 PIM 1 ID DIMENSION? IM TMHCHES MI-, eg? W713 |b Tin | o.007 u.140 {_ 1.0 m * 0.013 THR, ine 025 MIM, here Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.