  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DEasily Interfaced to Microprocessors
DOn-Chip Data Latches
DMonotonic Over the Entire A/D Conversion
Range
DSegmented High-Order Bits Ensure
Low-Glitch Output
DInterchangeable With Analog Devices
AD7524, PMI PM-7524, and Micro Power
Systems MP7524
DFast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320
DCMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity error
Power dissipation at VDD = 5V
Setting time
Propagation delay time
8 Bits
1/2LSB Max
5mW Max
100ns Max
80ns Max
description
The TLC7524C, TLC7524E, and TLC7524I are
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
microprocessors.
The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5mW typically.
Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses
or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation
from −25°C to +85°C. The TLC7524E is characterized for operation from −40°C to +85°C.
Copyright 1998−2007, Texas Instruments Incorporated
  !" # $%&" !#  '%()$!" *!"&+
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#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3
RFB
REF
VDD
WR
CS
DB0
DB1
DB2
3212019
910111213
4
5
6
7
8
18
17
16
15
14
VDD
WR
NC
CS
DB0
GND
DB7
NC
DB6
DB5
FN PACKAGE
(TOP VIEW)
OUT2
OUT1
NC
DB2
DB1 REF
DB4
DB3
NC
NC−No internal connection
RFB
D, N, OR PW PACKAGE
(TOP VIEW)
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
Data Inputs
Data Latches
13
WR
12
CS
REF 15
11
DB0
(LSB)
6
DB5
5
DB6
4
DB7
(MSB)
GND
3
OUT2
2
OUT1
1
RFB
16
R
RRR
2R
2R
S-8
2R
S-3
2R
S-2
S-1
2R
Terminal numbers shown are for the D or N package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD 0.3V to 16.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, VI 0.3V to V DD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage, Vref ±25V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak digital input current, II 10µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC7524C 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC7524I 25°C to +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC7524E 40°C to +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, TC: FN package +260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package +260°C. . . . . . . . . . .
package/ordering information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
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recommended operating conditions
VDD = 5V VDD = 15V
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
Supply voltage, VDD 4.75 5 5.25 14.5 15 15.5 V
Reference voltage, Vref ±10 ±10 V
High-level input voltage, VIH 2.4 13.5 V
Low-level input voltage, VIL 0.8 1.5 V
CS setup time, tsu(CS) 40 40 ns
CS hold time, th(CS) 0 0 ns
Data bus input setup time, tsu(D) 25 25 ns
Data bus input hold time, th(D) 10 10 ns
Pulse duration, WR low, tw(WR) 40 40 ns
TLC7524C 0 +70 0 +70
Operating free-air temperature, T
A
TLC7524I −25 +85 −25 +85 °C
Operating free-air temperature, TA
TLC7524E −40 +85 −40 +85
C
electrical characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5V VDD = 15V
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
IIH High-level input current VI = VDD 10 10 µA
IIL Low-level input current VI = 0 −10 −10 µA
IIkg
Output leakage
OUT1 DB0−DB7 at 0V,
Vref = ±10V WR, CS at 0V, ±400 ±200
nA
IIkg
Output leakage
current OUT2 DB0−DB7 at VDD,
Vref = ±10V WR, CS at 0V, ±400 ±200 nA
IDD
Supply current
Quiescent DB0−DB7 at VIHmin or VILmax 1 2 mA
IDD Supply current Standby DB0−DB7 at 0V or VDD 500 500 µA
kSVS Supply voltage sensitivity,
gain/VDD VDD = ±10% 0.01 0.16 0.005 0.04 %FSR/%
CiInput capacitance,
DB0−DB7, WR, CS VI = 0 5 5 pF
OUT1
WR, CS at 0V
30 30
Co
Output capacitance
OUT2
WR, CS at 0V
120 120
pF
CoOutput capacitance OUT1
WR, CS at 0V
120 120 pF
OUT2
DD
WR, CS at 0V
30 30
Reference input impedance
(REF to GND) 5 20 5 20 k
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5V VDD = 15V
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Linearity error ±0.5 ±0.5 LSB
Gain error See Note 1 ±2.5 ±2.5 LSB
Settling time (to 1/2 LSB) See Note 2 100 100 ns
Propagation delay from digital input
to 90% of final analog output current See Note 2 80 80 ns
Feedthrough at OUT1 or OUT2 Vref = ±10V (100kHz sinewave)
WR and CS at 0V, DB0−DB7 at 0V 0.5 0.5 %FSR
Temperature coefficient of gain TA = +25°C to MAX ±0.004 ±0.001 %FSR/°C
NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB.
2. OUT1 load = 100, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V.
operating sequence
DB0−DB7
WR
CS
th(D)
ÎÎÎ
ÎÎÎ
tsu(D)
tw(WR)
th(CS)
tsu(CS)
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
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PRINCIPLES OF OPERATION
voltage-mode operation
It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.
R
10
REF (Analog Output Voltage)
OUT2
OUT1 (Fixed Input Voltage)
R
RR
2R
2R2R2R
Figure 1. Voltage Mode Operation
The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
VO = VI (D/256)
where
VO = analog output voltage
VI = fixed input voltage
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER TEST CONDITIONS MIN MAX UNIT
Linearity error at REF VDD = 5V, OUT1 = 2.5V, OUT2 at GND, TA = +25°C 1 LSB
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, I ref, is switched to OUT2. The current source I/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch
capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however , in this case, I ref would
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input
coding for unipolar and bipolar operation respectively.
Iref
REF OUT2
OUT1
RFB
R
120 pF
30 pF
IIkg
I/256
IIkg
Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
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PRINCIPLES OF OPERATION
+
Output
RA = 2 k
(see Note A)
WR
CS
DB0−DB7
Vref
C (see Note B)
RB
VDD
GND
OUT2
OUT1
RFB
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
Output
20 k
5 k
10 k
20 k
+
+
RFB
OUT1
OUT2
GND
VDD
RB
C (see Note B)
Vref
DB0−DB7
CS
WR
(see Note A)
RA = 2 k
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see Note 3)
ANALOG OUTPUT
DIGITAL INPUT
(see Note 4)
ANALOG OUTPUT
MSB LSB
ANALOG OUTPUT
MSB LSB
ANALOG OUTPUT
1 1 1 1 1 1 1 1 −Vref (255/256) 1 1 1 1 1 1 1 1 Vref (127/128)
1 0 0 0 0 0 0 1 −Vref (129/256) 1 0 0 0 0 0 0 1 Vref (1/128)
1 0 0 0 0 0 0 0 −Vref (128/256) = −Vref/2 1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 −Vref (127/256) 0 1 1 1 1 1 1 1 −Vref (1/128)
0 0 0 0 0 0 0 1 −Vref (1/256) 0 0 0 0 0 0 0 1 −Vref (127/128)
0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 −Vref
NOTE 3: LSB = 1/256 (Vref) NOTE 4: LSB = 1/128 (Vref)
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
microprocessor interfaces
A0−A15
Z−80A
D0−D7
WR
IORQ
Address Bus
Decode
Logic
TLC7524 OUT2
OUT1
CS
WR
DB0−DB7
Data Bus
Figure 5. TLC7524: Z-80A Interface
Data Bus
DB0−DB7
WR
CS
OUT1
OUT2
TLC7524
Decode
Logic
Address Bus
VMA
φ2
D0−D7
6800
A0−A15
Figure 6. TLC7524: 6800 Interface
  
   
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
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PRINCIPLES OF OPERATION
microprocessor interfaces (continued)
8-Bit
Latch
AD0−AD7
8051
A8−A15
ALE
Adress/Data Bus
Decode
Logic
TLC7524 OUT2
OUT1
CS
WR
DB0−DB7
Address Bus
WR
Figure 7. TLC7524: 8051 Interface
Revision History
DATE REV PAGE SECTION DESCRIPTION
6/07
D
Front Page Deleted Available Options table.
6/07
D
2 Inserted Package/Ordering information.
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC7524CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CFN ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524CFNR ACTIVE PLCC FN 20 1000 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524CN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524CNE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524CNS ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CNSG4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CNSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524ED ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524EDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524EDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524EDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524EN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524ENE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 28-May-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC7524IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IFN ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC7524IN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524INE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC7524IPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7524IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-May-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC7524CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TLC7524CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC7524EDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLC7524IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7524CDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524CNSR SO NS 16 2000 367.0 367.0 38.0
TLC7524CPWR TSSOP PW 16 2000 367.0 367.0 35.0
TLC7524EDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524IDR SOIC D 16 2500 367.0 367.0 38.0
TLC7524IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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