BCM8212
®
TRANSCEIVER WITH INTERNAL LOOP TIMING AND PHASE DETECTOR
Application Block Diagram
•2.488- Gbps SO NE T/SDH tra nsceiver with dual differential
serial I/O
•Fully integrated CDR, MUX, DEMUX, and CMU with 16-bit,
155.52-MHz LV PECL interface
•On-chip, PLL-based clock generator
•Internal ph ase detector and charge pump for cleanup PLL
•Line and system loopback modes
•Loss-of-signal output (LOSB) and input (LOSIB)
•TX and RX lock detect
•Elastic buffering with FIFO overflow alarm
•Selectabl e 77.76/155.52-MHz reference clock
•Selectable RX clock and RX data squelch on LOS
•Selectable loop timing mode
•Dual 2.5V/3 .3V supplies
•Power dissipation: 1.2W typical
•Selectable div ide-by-32 or divide-by-16 receiver/ transm i tter
low-speed parallel output clock
•Standard CMOS fabrication process
•23 ¥ 23 mm, 208-pi n BGA package
•Low power consum ptio n el iminates extern al he at sinks , fan s
for s yst em ai rflo w, an d exp ensi ve hi gh cu rren t pow er su ppli es.
•Supports SONET dual-fiber ring architecture.821 2-PB05-R
•High integration reduces design cycle and time to market.
•Provides increased port density per board and system.
•Fea t ures low j it t e r: 3 mU I RMS typical.
•CMOS-based d evice uses th e most effective silicon econom y of
scale.
•Exceeds SONET jitter requi rements, which allows the use of
low-cost optics.
•Target applications:
•OC-4 8/S TM- 1 6 tra nsm is s ion eq uip m en t
•SONET/SDH optica l modules
•ADD/DROP multiplexers
•Digital cross-connects
•ATM switch backboneONE T/SDH test eq uipment
•SONET/SDH test equipment
•Terabit and edge route rs
FEATURES SUMMARY OF BENEFITS
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BCM8212
BCM8212
16
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BCM8212 OVERVIEW
®
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8212-PB05-R 04/15/03
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM8212 SONET/SDH transceiver is a fully integrated
serialization/deserialization SONET OC-48 (2.488 Gbps) interface
device with an integrated Clock Multiplication Unit (CMU) and an
integrated Clock and Data Recovery (CDR) circuit. On-chip clock
synthesis is performed by the high- frequency and low-jitter, phase-
locked loop on the BCM8212 transceiver chip, allowing the use of a
slower 77.76/155.52-MHz external transmit clock reference.
Dual RX and TX 2.488 Gbps interfaces support dual-fiber ring
architectures. Clock recovery is performed on the device by
synchronizin g its on-chip VCO directly to the incoming data strea m. The
low-jitter, LVPECL interface guarantees compliance with the bit error
rate requirements of the Telcordia GR-253-CORE, ANSI, and ITU-T
stand ards. T he BCM82 12 is pack aged in a 2 3 x 23 x 1. 53 mm, 20 8-pin
BGA.
The BCM8212 operates in a 2.5/3.3V configuration. The core and CML
I/Os operate at 2.5 V. The LVPECL I/Os operate at 3.3V.
A
CLK16IP
CLK16IN
PHDCKP
PHDCKN
DI0
DI15
RESETB
CKSEL
RTSYNC
TXDP
TXDN
TXCKP
TXCKN
TCK16ON
TCK16OP
TXLKDT
RCK16ON0
RCK16OP0
RCK16ON1
RCK16OP1
DO0
IOVREF
DO15
LOSB
RXLKDT
OVFB
TCK320
PD LKDT
PD OUT
REFCKP
REFCKN
REF 155EN
DOSQ
RCK16SQ
RDINP0
RDINN0
RDINP1
RDINN1
SELRD1
LOSIB
VCN_CDR
VCP_CDR
REFCKENB
RCK1SEL
TSEL
LPBKSB
LPBKFB
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