82541ER Gigabit Ethernet Controller
Networking Silicon
Datasheet
Product Features
■PCI Bus
—PCI r evision 2.3, 32-bit, 33/66 MHz
—Algorithms that optimally use advanced PCI,
MWI, MRM, and MRL commands
—3.3 V (5 V tolerant PCI signaling)
■MAC Specific
—Low-lat ency transmit and receive queues
—IEEE 802. 3x-complian t flow-control suppor t
with software-con trol la ble thresho ld s
—Caches up to 64 packet descriptors in a single
burst
—Programmabl e host memory receive b uffers
(256 B to 16 KB) and cache line size (16 B to
256 B)
—Wide, optimized internal data path
architecture
—64 KB configurable Transmit and Receive
FIFO buffers
■PHY Specific
—Integrated for 10/100/1000 Mb/s operation
—IEEE 802. 3a b Auto -Ne go tiatio n supp o rt
—IEEE 802. 3a b PHY comp lia nc e and
compatibility
—State -of-the-art DSP archit ecture implements
digital adaptive equalization, echo
cancellation, and cross-talk cancellation
—Autom ati c pola rity detectio n
—Automatic detection of cable lengths and
MDI vs. MDI-X ca bl e at all speeds
■Host Off-Loading
—Transmit and receive IP, TCP, and UDP
checksum off-loading capabilities
—Transmit TCP segmentation
—Adva nced packed f iltering
—Jumbo frame support up to 16 KB
—Intelligent Interrupt generation (multiple
packets per i nterrupt)
■Manageabiltiy
—Network Devi ce Class Power Management
Specificatio n 1.1
—Compliance with PCI Power Management
1.1 and ACPI 2.0
—SNMP and RMON statistic counters
—D0 and D3 po wer st ates
■Additional Device
—Four programm able LED outputs
—On-chi p power control circuitry
—BIOS LAN Disable pin
—JTAG (IEEE 1149.1) Test Access Port built
in silicon (3.3 V, 5 V tolerant PCI signaling)
■Lead-freea 196-p in Ball Grid Array (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUxxxxxx.
a. Thi s devic e is lead- f ree. Th at is, le ad has no t been i n tentio n ally added, but lead may still exist as an im purity at
<1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other
Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has be en tested and conforms to the same parametr ic spec ifications as previous versio ns of
the dev i ce.
For more in form ation regarding lead-free products from Inte l Co rporation, contact your Intel Field S ales re presen-
tative
318139-002
Revision 4.3
ii
Revision History
Date Revision Notes
Aug 2003 2.0 Non-classified release.
Mar 2004 3.0 Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the C-0
stepping.
Oct 2004 3.1 • Corrected EEMODE signal description.
• Updated signal names to match design guide and reference schematics.
Nov 2004 3.2
• Added lead free information.
• Added in formation about migrating from a 2-layer 0.36 mm wide-trace substrate to
a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and
Pinout Information.
• Added statement that no changes to existing soldering processes are needed for
the 2-layer 0.32 mm wide-trace substrate change in the section describing
“Packa ge Info rm atio n”.
• Corrected pinout discrepancies between sections “Signal Descriptions” and
“Package and Pinout Information”.
Jan 2005 3.3 • Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See
Table 2, Recommended Operating Conditions and Table 6, DC Characteristics.
Feb 2005 3.4 • Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14, and H14.
Apr 2005 3.5 • Removed all references to CLK_RUN# signal.
• Corrected the FLSH_SO/LAN_DISABLE signal de finition. If Flash functionality is
not used then an external pull-down resistor is required.
July 2005 3.6 • Added pin C8 description to Table 29 and Table 31.
Aug 2005 3.7 • Corrected 25 MHz Clock Input Requirements in Table 13.
June 2006 3.8 • Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is
not used then an external pull-up resistor is required.
June 2006 3.9 • Updated Table 13 “25 MHz Clock Input Requirements” .
Aug 2006 4.0 • Updated Table 40 descriptions for pins A10, B10, and C9.
• Updated pinout descriptions from Tables 25 - 42 to match Figure 13.
Sept 2006 4.1 • Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved the note
following Table 5 before Table 3 “3.3V Supply Volt age Ramp”
Aug 2007 4.2 • Added new Intel logo, updated “Product Features”, and added new document
ordering information to copyright page.
June 2008 4.3 • Clarified product ordering codes.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m.
The 82541ER Gigabit Ethernet Controller may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 8021 7- 980 8
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countr ies 7 0 8-
296-9333.
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2008
*Third-party brands and names are the property of their respective owners.
iii
82541ER Gigabit Ethernet Controller
Contents
1.0 Introduction ......................................................................................................................1
1.1 Document Scope...................................................................................................1
1.2 Referenc e Docume nts. ....... ...... ....... ...... ...... ....... ...... ....... ...... .......................... ......2
1.3 Product Codes.......................................................................................................2
1.4 Block Diagram.......................................................................................................3
2.0 Product Code....................................................................................................................5
3.0 Signal Descriptions..........................................................................................................7
3.1 Signal Type Definitions..........................................................................................7
3.2 PCI Bus Interface Signals (56)..............................................................................7
3.2.1 PCI Address, Data and Control Signals (44)............................................8
3.2.2 Arbitration Signals (2)...............................................................................9
3.2.3 Interrupt Signal (1)....................................................................................9
3.2.4 System Signals (3) ...................................................................................9
3.2.5 Error Reporting Signals (2).....................................................................10
3.2.6 Power Management Signals (2).............................................................10
3.3 EEPROM and Serial FLASH Interface Signals (9)..............................................10
3.4 Miscellaneous Signals.........................................................................................11
3.4.1 LED Signals (4)......................................................................................11
3.4.2 Other Signa ls (4)...................... ...... ....... ...... .......................... .................11
3.5 PHY Signa ls....................... ...... ....... ...... ...... .............................................. ..........1 1
3.5.1 Crystal Signals (2)..................................................................................11
3.5.2 Analog Signals (10)..... ....... ...... ...... .......................... ..............................1 2
3.6 Test Interface Signals (6)....................................................................................12
3.7 Power Supply Connections.................................................................................13
3.7.1 Digital and Analog Supplies ...................................................................13
3.7.2 Grounds, Reserved Pins and No Connects ...........................................13
3.7.3 Voltage Regulation Control Signals (2) ..................................................13
4.0 Voltage, Temperature, and Timing Specifications......................................................15
4.1 Absolute Maximum Ratings.................................................................................15
4.2 Targeted Recommended Operating Conditions..................................................15
4.2.1 General Op erati ng Cond iti ons..................... ....... ...... ....... ...... ....... ..........1 5
4.2.2 Voltage Ramp and Sequencing Recommendations...............................16
4.3 DC Specificat ion s.. ...... ....... ...... ....... ...... ...... ....... ...... .......................... .................18
4.4 AC Characteristics...............................................................................................21
4.5 Timing Specifications ..........................................................................................23
4.5.1 PCI Bus Interface...................................................................................23
4.5.1.1 PCI Bus Interface Clock ............................................................23
4.5.1.2 PCI/PCI-X Bus Interface Timing................................................24
4.5.2 Link Interface Timing..............................................................................27
4.5.3 EEPROM Interface.................................................................................27
5.0 Package and Pinout Information ..................................................................................29
5.1 Package Information ...........................................................................................29
5.2 Thermal Specifications........................................................................................31
82541ER Gigabit Ethernet Controller
iv
5.3 Pinout Information...............................................................................................32
5.4 Visual Pin Assignments.......................................................................................42
Figures 1 82541ER Block Diagram.......................................................................................3
2 AC Test Loads for General Output Pins..............................................................23
3 PCI Clock Timing ................................................................................................23
4 PCI Bus Interface Output Timing Measurement .................................................24
5 PCI Bus Interface Input Timing Measurement Conditions ..................................25
6 TVAL (max) Rising Edge Test Load....................................................................25
7 TVAL (max) Falling Edge Test Load...................................................................26
8 TVAL (min) Test Load.........................................................................................26
9 TVAL Test Load (PCI 5 V Signaling Environment) .............................................26
10 Link Interface Rise/Fall Timing............................................................................27
11 82541ER Mechanical Specifications...................................................................29
12 196 PBGA Package Pad Detail...........................................................................30
13 Visual Pin Assignments.......................................................................................42
Tables 1 Absolute Maximum Ratings ................................................................................15
2 Recommended Operating Conditions ................................................................15
3 3.3V Supply Voltage Ramp.................................................................................16
4 1.8V Supply Voltage Ramp.................................................................................16
5 1.2V Supply Voltage Ramp.................................................................................17
6 DC Characteristics..............................................................................................18
7 Power Specifi ca tio ns - D0a... ...... ....... ...... ...... ....... .......................... ....................18
8 Power Specifi ca tio ns - D3cold ........... ...... ...... ....... ...... ....... ...... ....... ...... ..............18
9 Power Specifications D(r) Uninitialized)..............................................................19
10 Power Specifi catio ns - Complet e Subs yste m ............. ....... ...... ....... ....................19
11 I/O Characteristics...............................................................................................20
12 AC Characteristics: 3.3 V Interfacing..................................................................21
13 25 MHz Clock Input Requirements .....................................................................21
14 Reference Crystal Specification Requirements...................................................22
15 Link Interface Clock Requirements .....................................................................22
16 EEPROM Interface Clock Requirements............................................................22
17 AC Test Loads for General Output Pins..............................................................22
18 PCI Bus Interface Clock Parameters ..................................................................23
19 PCI Bus Interface Timing Parameters.................................................................24
20 PCI Bus Interface Timing Measurement Conditions...........................................25
21 Rise and Fall Times ............................................................................................27
22 Link Interface Clock Requirements .....................................................................27
23 Link Interface Clock Requirements .....................................................................27
24 Thermal Characteristics ......................................................................................31
25 PCI Address, Data and Control Signals..............................................................32
26 PCI Arbitration Signals........................................................................................32
27 Interrupt Signals..................................................................................................32
28 System Signals ...................................................................................................32
29 Error Reporting Signals.......................................................................................33
30 Power Management Signals ...............................................................................33
31 Serial EEPROM Interface Signals.......................................................................33
v
82541ER Gigabit Ethernet Controller
32 Serial FLASH Interface Signals...........................................................................33
33 LED Signals.........................................................................................................33
34 Other Signa ls......... ...... ....... ...... ....... ...... ...... ....... ...... .......................... .................33
35 IEEE Test Signals ...............................................................................................34
36 PHY Signa ls... ....... ...... ....... ...... ....... ...... ............................................. .................34
37 Test Interface Signals..........................................................................................34
38 Digital Power Signals ..........................................................................................34
39 Analog Pow er Signals ........ ...... ....... ...... ...... ....... ...... ....... ...... ....... .......................35
40 Grounds and No Connect Signals.......................................................................35
41 Voltage Regulation Control Signals.....................................................................35
42 Signal Names in Pin Order..................................................................................36
82541ER Gigabit Ethernet Controller
vi
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82541ER Gigabit Ethernet Controller
1
1.0 Introduction
The Intel® 82541ER Gigabit Ethernet is a single, compact component with an integrated Gigabit
Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For embedded
communication and network devices such as web kiosks, and Point-of-Sale terminal designs with
critical space constraints, the Intel 82 541ER allows for a Gigab it Ethernet implementation in a ver y
small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs.
The Intel® 82541ER integrates fourth generation gigabit MAC design with fully integrated,
physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE_TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is
capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In
addition t o managing MAC and PHY lay er funct ions, the controller provides a 32-bi t wide direct
Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66
MHz.
The 82541ER Architecture is designed for high performance and low memory latency. Wide
internal data paths elimin ate perf orm ance bot tlenecks by efficiently handling large address and
data words. The 825 41ER control ler includes advanced interr upt handling features to limit PCI bus
traffic and a PCI interface that maximizes efficient bus usage. The 82541ER uses efficient ring
buff er descriptor data structur es, with up to 64 packet de scriptors cached on ch ip. A large 64 KByte
on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In
addition, using har dware acceleration, the controller of floads tasks from the host con troller , such as
TCP/UDP/IP checksum calculations and TCP segmentation.
The 82541ER i s packag ed i n a 15 mm X 15 mm 196- bal l gri d arr ay and i s pin comp at ibl e with t he
82559ER/82551ER 10/100 Mbps Fast Eth e rnet Multifunction PCI/CardBus Controller, 82562EZ/
82562EX Platform LAN Connect devices, the 82540EM Gigabit Ethernet Controller and the
82540EP Gigabit Ethernet Controller.
1.1 Document Scope
This document contains datasheet specifications for the 82541 ER Gig abi t Ethern et Cont roll er,
including signal descriptions, DC and AC parameters, packaging data, and pinout information.
82541ER Gigabit Ethernet Controller
2
1.2 Ref eren ce Doc u m ents
This document assumes that the designer is acquainted with high-speed design and board layout
techniques. The following documents provide additional information:
•825462EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide. Intel
Corporation.
•82547GI(EI)/82541(PI/GIEI) & 82541ER EEPROM Map and Programming Information
Guide. Intel Corporation .
•PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group.
•PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest
Group.
•IEEE Standar d 802. 3, 2003 Edition. Incorporates variou s IEEE standard s previously published
separately. Institute of Electrical and Electronics Engineers (IEEE).
•Intel Ethernet Controllers Timing Device Selection Guide. Intel Corp oration.
•PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group.
Software driver developers should contact their local Intel representatives for programming
information.
1.3 Product Codes
The product ordering codes are:
•GD82541ER (leaded device)
•LU82541ER (lead-free device)
82541ER Gigabit Ethernet Controller
3
1.4 Block Diagram
Figure 1. 82541ER Block Diagram
VLA
N
PCI Core
Slave
Access
Logic
DMA Function
Descri ptor Ma nage m ent
Control
Status
Logic
Statistics
TX/RX MAC
CSMA/CD
64KB
Packet
RAM
Management
Interface
PHY
Control
Side-stream
Scrambler/
Descrambler
Media Dependent Interface
ECHO, NEXT,
FEXT
Cancellers
Trellis Viterbi
Encoder/Decoder
Line DriverHybrid
Pulse Shaper,
DAC, Filter
AGC, A/D
Timing
Recovery
4DPAM5
Encoder
8 bits
8 bits
4 bits
4 bits
FlashEEPROM
RX FIlters
(Perfect & VLAN)
VLA
N
PCI Core
Slave
Access
Logic
DMA Function
Descri ptor Ma nage m ent
Control
Status
Logic
Statistics
TX/RX MAC
CSMA/CD
64KB
Packet
RAM
Management
Interface
PHY
Control
Side-stream
Scrambler/
Descrambler
Media Dependent Interface
ECHO, NEXT,
FEXT
Cancellers
Trellis Viterbi
Encoder/Decoder
Line DriverHybrid
Pulse Shaper,
DAC, Filter
AGC, A/D
Timing
Recovery
4DPAM5
Encoder
8 bits
8 bits
4 bits
4 bits
FlashEEPROM
RX FIlters
(Perfect & VLAN)
82541ER Gigabit Ethernet Controller
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82541ER Gigabit Ethernet Controller
5
2.0 Product Ordering Codes
The product ordering codes for the 82541ER Gigabit Ethernet Controller are:
•GD82541ER (leaded device)
•LU82541ER (lead-free device)
82541ER Gigabit Ethernet Controller
6
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82541ER Gigabit Ethernet Controller
7
3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of the 82541ER controller are electrically defined as follows:
3.2 PCI Bus Interface Signals (56)
When the Reset signal (RST#) is asserted, the 82541ER will not drive any PCI output or bi-
directional pins.
Name Definition
IInput. Standard input only digital signal.
OOutput. Standard output only digital signal.
TS Tri-state. Bi-directional tri-state digital input/output signal.
STS
Sust ained Tri-state. An active low tri-state signal owned and driven by only one agent at a
time. The agent that drives an STS pin low must drive it high for at least one clock before letting
it float. A new agent cannot start driving an STS signal any sooner than one clock after the
previous owner tri-states it. A pullup is required to sustain the inactive state until another agent
drives it, and must be provided by the central resource.
OD
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore
the signal to the de-asserted state.
AAnalog. PHY analog data signal.
PPower. Power connection, voltage reference, or other reference connection.
82541ER Gigabit Ethernet Controller
8
3.2.1 PCI Address, Data and Control Signals (44)
Symbol Type Name and Function
AD[31:0] TS
Address and Data. Address and data signals are multiplexed on the same PCI pins. A
bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
82541ER device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]
contain the most significant byte (MSB).
C/BE#[3:0] TS
Bus Command and Byte Enables. Bus command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction, C/
BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte
enables. The byte enables are valid for the ent ire dat a phase and determine which byte
lanes contain meaningful data.
C/BE#[0] applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).
PAR TS
Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/
BE#[3:0]. PAR is stable and valid one clock after the address phase. During data
phases, PAR is stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted aft er a read transaction. Once P AR is valid, it remains
valid until one clock after the completion of the current data phase.
When the 82541ER controller is a bus master, it drives PAR for address and write data
phases, and as a slave device, drives PAR for read data phases.
FRAME# STS
Cycle Frame. The Frame s i gnal is d r i ven by the 82541ER device to indicate the
beginning and length of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the
transaction is in the final data phase.
IRDY# STS
Initiator Ready. Initiator Ready indicates the ability of the 82541ER controller (as a bus
master device) to complete the current data phase of the transaction. IRDY# is used in
conjunction with the Target Ready signal (TRDY#). The data phase is completed on
any clock when both IRDY# and TRDY# are asserted.
During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a
read cycle, it indicates the master is ready to accept data. W ait cycles are inserted until
both IRDY# and TRDY# are asserted together. The 82541ER controller drives IRDY#
when acting as a master and samples it when acting as a slave.
TRDY# STS
Target Ready. The Target Ready signal indicates the ability of the 82541ER controller
(as a selected device) to complete the current dat a phase of the transaction. TRDY# is
used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed
on any clock when both TRDY# and IRDY# are sampled asserted.
During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write
cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together. The 82541ER device drives TRDY# when
acting as a slave and samples it when acting as a master.
STOP# STS
Stop. The Stop signal indicates the current target is requesting the master to stop the
current transaction. As a slave, the 82541ER controller drives STOP# to request the
bus master to stop the transaction. As a master, the 82541ER controller receives
STOP# from the slave to stop the current transaction.
82541ER Gigabit Ethernet Controller
9
3.2.2 Arbitration Signals (2)
3.2.3 Interrupt Signal (1)
3.2.4 System Signals (3)
IDSEL# I Initialization Device Select. The Initialization Device Select signal is used by the
82541ER as a chip select signal during configuration read and write transactions.
DEVSEL# STS
Device Select. When the Device Select signal is actively driven by the 82541ER, it
signals notifies the bus master that it has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
VIO P
VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI
signaling environment). It is used as the clamping voltage.
Note: VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with
the pull-up clamps specification.
Symbol Type Name and Function
REQ# TS Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
GNT# I Grant Bus. The Grant Bus signal notifies the 82541ER that bus access has been
granted. This is a point-to-point signal.
Symbol Type Name and Function
INTA# TS Interrupt A. I nterrupt A is used to request an interrupt of the 82541ER. It is an active
low, level-triggered interrupt signal.
Symbol Type Name and Function
CLK I
PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus
and is an input to the 82541ER device. All other PCI signals, except the Interrupt A
(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other
timing parameters are defined with respect to this edge.
M66EN I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz
RST# I
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals are floated
and all input signals are ignored.
Most of the internal state of the 82541ER is reset on the de-assertion (rising edge) of
RST#.
Symbol Type Name and Function
82541ER Gigabit Ethernet Controller
10
3.2.5 Error Report ing Signals (2)
3.2.6 Power Management Signals (2)
3.3 EEPROM and Serial FLASH Inte rface Signals (9)
Symbol Type Name and Function
SERR# OD System Error. The System Error signal is used by the 82541ER controller to report
address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
PERR# STS
Pari ty Er ror. The Parity Error signal is used by the 82541ER controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
tri-state and must be driven active by the 82541ER controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
Symbol Type Name and Function
LAN_PWR
GOOD IPower Good (Power-on Reset). The Power Good signal is used to indicate that stable
power is available for the 82541ER. When the signal is low , the 82541ER holds itself in
reset state and floats all PCI signals.
AUX_PWR I Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available
and the 82541ER device should support the D3cold power state.
Symbol Type Name and Function
EEMODE I
EEPROM Mode. The EEPROM Mode pin is used to select the interface and
source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on
the standard EEPROM pins, tie this pin to ground wit h a 100 Ω pull-down resistor.
For a Serial Peripheral Interface (SPI*) EEPROM, leave this pin disconnected.
EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the
memory device.
EEDO I EEPROM Data Output. The EEPROM Data Output pin is used for input from the
memory device. The EEDO includes an internal pull-up resistor.
Note: Voltage for EEDO must be less than 0.7 V.
EECS O EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the
device.
EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the
EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHZ for
SPI.
FLSH_CE# O Flash Chip Enable Output. Used to enable FLASH device.
FLSH_SCK O Flash Serial Clock Output. The clock rate of the serial FLASH interface is
approximately 1 MHz.
FLSH_SI O Flash Serial Data I nput. This pin is an output to the memory device.
FLSH_SO/
LAN_DISABLE# I
Flash Serial Data Output / LAN Disable. This pin is an input from the Flash
memory. Alternatively, the pin can be used to disable the LAN port from a system
General Purpose Input Output (GPIO) port. It has an internal pullup device. If the
82541ER is not using Flash functionality, the pin should be connected to an
external pull-up resistor.
If this pin is used as LAN_DISABLE#, the device goes to low power state and the
LAN port is disabled when this pin is sampled low on rising edge of PCI reset.
82541ER Gigabit Ethernet Controller
11
3.4 Miscellaneous Signals
3.4.1 LED Signals (4)
3.4.2 Other Signal s (4)
3.5 PHY Signals
3.5.1 Crystal Signals (2)
Symbol Type Name and Function
LINK_LED# O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link
connectivity.
ACTIVITY# O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate
transmit or receive activity.
LINK100# O LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at
100 Mbps.
LINK1000# O LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at
1000 Mbps.
Symbol Type Name and Function
SDP[3:0] TS
Sof t ware D efi ned Pi n. The Software Defined Pins are reserved and programmable
with respect to input and output capability. These default to input signals upon power-
up but may be configured differently by the EEPROM . The upper four bits may be
mapped to the General Purpose Interrupt bits if they are configured as input signals.
Symbol Type Name and Function
XTAL1 I Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It should be
connected to a crystal, and the other end of the crystal should connect to XTAL2.
XTAL2 O Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a
crystal into oscillation.
82541ER Gigabit Ethernet Controller
12
3.5.2 A nalog Sign als (10)
3.6 Test Interface Signals (6)
Symbol Type Name and Function
MDI[0]+/- A
Media Dependent Interface [0].
1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDI[0]+/- corresponds to BI_DB+/-.
100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in
MDI-X configuration, MDI[0]+/- is used for the receive pair.
10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X
configuration, MDI[0]+/- is used for the receive pair.
MDI[1]+/- A
Media Dependent Interface [1].
1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDI[1]+/- corresponds to BI_DA+/-.
100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in
MDI-X configuration, MDI[1]+/- is used for the transit pair.
10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X
configuration, MDI[1]+/- is used for the transit pair.
MDI[2]+/- A
Media Dependent Interface [2].
1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X
configuration, MDI[2]+/- corresponds to BI_DD+/-.
100BASE_TX: Unused.
10BASE-T: Unused.
MDI[3]+/- A
Media Dependent Interface [3].
1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-X
configuration, MDI[3]+/- corresponds to BI_DD+/-.
100BASE_TX: Unused.
10BASE-T: Unused.
IEEE_TEST- A IEEE test pin out put mi nus. Used to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformanc e testing.
IEEE_TEST+ A Analog test pin output plus. U sed to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformanc e testing.
Symbol Type Name and Function
TEST I Test Enable. Enables test mode.
Normal mode: connect to VSS.
JTAG_TCK I JTAG Test Access Port Clock.
JTAG_TDI I JTAG Test Access Port Data In.
JTAG_TDO O JTAG Test Access Port Data Out.
JTAG_TMS I JTAG Test Access Port Mode Select.
JTAG_TRST# I JTAG Test Access Port Reset. This is an active low reset signal for JT AG.
To disable the JTAG interface, this signal should be terminated using a
100 Ω pull-down resistor to ground. It must not be left unconnected.
82541ER Gigabit Ethernet Controller
13
3.7 Power Supply Connections
3.7.1 Digital and Analog Supplies
3.7.2 Grounds, Reserved Pins and No Connects
3.7.3 Voltage Regulation Control Signals (2)
Symbol Type Name and Function
3.3V P 3.3 V I/O Power Supply.
Analog_1.8V P 1.8V Analog Power Supply.
CLKR_1.8V P 1.8V analog power supply for the clock recovery.
XTAL_1.8V P Input power for the XTAL regulator.
1.2V P 1.2V Power suppl y. This is for analog and digital circuits.
Analog_1.2V P 1.2V Analog Power Supply.
PLL_1.2V P Input power for the ICS regulator.
Symbol Type Name and Function
VSS P Ground.
AVSS P S hared analog Ground.
RSVD_VSS P Reserved Ground. This pin is reserved by Intel and may have factory test functions.
For normal operation, connect to ground.
RSVD_NC P Reserved No connect. This pin is reserved by Intel and may have factory test
functions. For normal operation, do not connect any circuit to these pins. Do not
connect pull-up or pull-down resistors.
NC P No Connect. This pin is not connected internally.
RSVD_VCC P Reserved VCC. This pin is reserved by Intel and may have factory test functions. For
normal operation, connect to VCC through a 1K pull-up resistor
Symbol Type Name and Function
CTRL12 A
1.2V Control. LDO voltage regulator output to drive external PNP pass transistor. If
1.2V is already present in the system, leave output unconnected. To achieve optimal
D3 power consumption, leave the output unconnected and use a high-efficiency
external switching regulator.
CTRL18 A
1.8V Control. LDO voltage regulator output to drive external PNP pass transistor. If
1.8V is already present in the system, leave output unconnected. To achieve optimal
D3 power consumption, leave the output unconnected and use a high-efficiency
external switching regulator.
82541ER Gigabit Ethernet Controller
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82541ER Gigabit Ethernet Controller
15
4.0 Voltage, Temperature, and Timing Specifications
4.1 Absolute Maximum Ratings
4.2 Targeted Recomm e nded Op erating Cond itio ns
4.2.1 General Operating Conditions
Table 1. Absolute Maximum Ratingsa
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are
exceeded. These values should not be used as the limits for normal device operations.
Symbol Parameter Min Max Unit
VDD (3.3) DC supply voltage on 3.3 V pins
with respect to VSS VSS - 0.5 4.6 V
VDD (1.8) DC supply voltage on 1.8 V pins
with respect to VSS VSS - 0.5 2.5 or
VDD (1.8) + 0.5b
b. The maximum value is the lesser value of 2.5V or VDD (2.5) + 0.5 V. This specification applies to biasing the device to a steady
state for an indefinite duration.
V
VDD (1.2) DC supply voltage on 1.2V pins
with respect to VSS VSS - 0.5 1.7 or
VDD (1.2) + 0.5c
c. The maximum value is the lesser value of 1.7 V or VDD (2.5) + 0.5 V.
V
VDD DC supply voltage VSS - 0.5 4. 6 V
VI / VO LV TTL input voltage VSS - 0.5 4.6d
d. The maximum value must also be less than VIO.
V
IO Output current 40 mA
TSTG Storage temperature range -40 125 °C
ESD per MIL_STD-883 Test
Method 3015, Specif ication 2001V
Latchup Over/Undersho ot: 150
mA, 125 C
VDD overstress:
VDD (3.3) * 7.2 V
Table 2. Recommended Operating Conditions (Sheet 1 of 2)a
Symbol Parameter Min Max Unit
VDD (3.3) DC supply voltage on 3.3 V pins 3.0 3.6 V
VDD (1.8) DC supply voltage on 1.8 V pins 1.71b1.89cV
VDD (1.2) DC supply voltage on 1.2 V pins 1.14d1.26eV
VIO PCI bus reference voltage 3.0 5.25 V
tR / tF Input rise/fall time (normal input) 0 200 ns
82541ER Gigabit Ethernet Controller
16
4.2.2 Voltage Ramp and Sequenci ng Recommendations
Note: In any case or time period (greater than 1 ns), the supply voltage should comply with 3.3V > 1.8V
> 1.2V. This is important to avoid stress in the ESD protection circuits. After 3.3V reaches 10% of
its final value, all voltage rails (1.8V and 1.2V) have 150 ms to reach their final operating values.
tr/tf input rise/fall time (Schmitt input) 0 10 ms
TAO per ating temperature range
(ambient) 070°C
TJJunction temperature ≤125 °C
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating
limits, might result in permanent damage.
b. The value list ed in thi s table is for exter nal volt age reg ulation. If the inte rnal volt age r egulato r is used , the minim um value i s
1.67 V.
c. The val u e li sted in th i s tab le i s fo r ext ern al vo ltage regulation. If th e i nte rn al volt a ge reg ulat or i s u sed , the ma xi mu m va lue is
1.926 V.
d. The value list ed in thi s table is for exter nal volt age reg ulation. If the inte rnal volt age r egulato r is used , the minim um value i s
1.12 V.
e. The valu e l isted i n th is table is for ext ern al vo ltage re gul a tion. If the inte rn al volt a ge reg ulat or i s u sed , the ma xi mu m va lue is
1.284 V.
Table 3. 3.3V Supply Voltage Ramp
Parameter Description Min Max Unit
Rise Time Time from 10% to 90% mark 0.1 100 ms
Monotonicity Voltage dip allowed in ramp 0 mV
Slope Ramp rate at any time between 10% to 90% 28800 V/s
Operational
Range Voltage range for normal operating conditions 3 3.6 V
Ripple Maximum voltage ripple at a bandwidth equal
to 50 MHz 70 mV
Overshoot Maximum voltage allowed 4 V
Table 4. 1.8V Supply Voltage Ramp
Symbol Parameter Min Max Unit
Rise Time Time from 10% to 90% mark 0.1 100 ms
Monotonicity Voltage dip allowed in ramp 0 mV
Slope Ramp rate at any time between 10% to 90% 57600 V/s
Operational
Range V ol tage range f or normal operating conditions
(PNP’s)a1.674 1.89 V
Operational
Range V ol tage range f or normal operating conditions
(PNP’s) -7 5 %
Operational
Range V ol tage range f or normal operating conditions
(external regulator) 1.71 1.89 V
Operational
Range V ol tage range f or normal operating conditions
(external regulator) -5 5 %
Table 2. Recommended Operating Conditions (Sheet 2 of 2)a
Symbol Parameter Min Max Unit
82541ER Gigabit Ethernet Controller
17
Ripple Maximum volt age ripple at a bandwidth equal
to 50 MHz 20 mV
Overshoot Maximum voltage allowed 2.2 V
Output
Capacitance Capacitance range when using PNP circuit 4.7 20 µF
Input
Capacitance Capacitance range when using PNP circuit 4.7 20 µF
Capacitance
ESR Equivalent series resistance of output
capacitanceb5 100 mΩ
Ictrl_18 Maximum output current rating to CTRL18 20 mA
a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking.
b. Tantalum capacitors must not be used.
Table 5. 1.2V Supply Voltage Ramp
Symbol Parameter Min Max Unit
Rise Time Time from 10% to 90% mark 0.025 ms
Monotonicity Voltage dip allowed in ramp 0 mV
Slope Ramp rate at any time between 10% to 90% 38400 V/s
Operational
Range V oltage range for normal operating conditions
(PNP’s)a
a. Operating with an internal regulator (PNP) supports a wider tolerance output voltage due to process tracking.
1.116 1.26 V
Operational
Range V oltage range for normal operating conditions
(PNP’s) -7 5 %
Operational
Range V oltage range for normal operating conditions
(external regulator) 1.14 1.26 V
Operational
Range V oltage range for normal operating conditions
(external regulator) -5 5 %
Ripple Maximum volt age ripple at a bandwidth equal
to 50 MHz 20 mV
Overshoot Maximum voltage allowed 1.45 V
Output
Capacitance Capacitance range when using PNP circuit 4.7 20 µF
Input
Capacitance Capacitance range when using PNP circuit 4.7 20 µF
Capacitance
ESR Equivalent series resistance of output
capacitanceb
b. Tantalum capacitors must not be used.
5 100 mΩ
Ictrl_12 Maximum output current rating to CTRL_12 20 mA
Table 4. 1.8V Supply Voltage Ramp
82541ER Gigabit Ethernet Controller
18
4.3 DC Specific ations
Table 6. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
VDD (3.3) DC supply volt age on 3.3 V
pins 3.00 3.3 3.60 V
VDD (1.8) DC supply volt age on 1.8 V
pins 1.71a
a. The value list ed in this table is for e xter nal vo lt age reg ulat i on. If the internal volta ge regu lato r i s use d, the mini m um value is
1.67 V.
1.8 1.89b
b. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is
1.926 V.
V
VDD (1.2) DC supply volt age on 1.2 V
pins 1.14c
c. The val ue list ed in th is tab le is for e xter nal vo lt age reg ulat i on. If the i nt ern al volt a ge regu lato r is use d, the minim um v alue is
1.12 V.
1.2 1.26d
d. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is
1.284 V.
V
Table 7. Power Specifications - D0a
D0a
unplugged no link @10 Mbps @100 Mbps @ 1000 Mbps
Typ Icc
(mA)a
a. Typical conditions: operating temper ature (T A) = 25 C, nominal voltages, moderate network traffic at full duplex,
and PCI 33 MHz system interface.
Max Icc
(mA)b
b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network
traffic at full duplex, and PCI 33 MHz system interface.
Typ Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)b
3.3V 3 5 5 1013153040
1.8V 14 15 85 85 110 115 315 320
1.2V 30 35 85 90 90 100 380 400
Total
Device
Power 75 mW 270 mW 355 mW 1.1 W 1.2 W
Table 8. Power Specifications - D 3cold
D3cold - wake-up enabledaD3cold-wake
disabled
unplugged link @10 Mbps @100 Mbps
Typ Icc
(mA)bMax Icc
(mA)cTyp Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)b
3.3V 23232345
82541ER Gigabit Ethernet Controller
19
1.8V 14 15 20 25 110 115 1 2
1.2V 21 25 30 35 80 85 7 10
Total
Device
Power 60 mW 80 mW 305 mW 25 mW
a. The power consumption for 1000 Mbps is not shown since the controller moves to the 10/100 Mbps mode before
going into the D3 state to co nserve power.
b. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex,
and PCI 33 MHz system interface.
c. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network
traffic at full duplex, and PCI 33 MHz system interface.
Table 9. Power Specifications D(r) Uninitialized)
D(r) Uninitialized (FLSH_SO/LAN_DISABLE # = 0)
Typ Icc (mA) Max Icc (mA)
3.3V 510
1.8V 12
1.2V 12 15
Total
Device
Power 35 mW
Table 8. Power Specifications - D3cold
D3cold - wake-up enabledaD3cold-wake
disabled
unplugged link @10 Mbp s @100 Mbps
Typ Icc
(mA)bMax Icc
(mA)cTyp Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)bTyp Icc
(mA)aMax Icc
(mA)b
Table 10. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits
D3cold - wake
disabled
D3cold wake-
enabled @
10 Mbps
D0 @10 Mbps
active D0 @100 Mbps
active
D0 @
1000 Mbps
active
Typ Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)b
3.3 V 4 5 7 10 12153345
82541ER Gigabit Ethernet Controller
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1.8 V 1 7 2 30 35 135 140 410
1.2 V 7 1030 358085380
Subsystem
3.3V
Current 10 40 120 710
a. Typical cond i ti o ns : o pe ra t in g t e mp e ra tur e (T A) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 33 MHz
system interface.
b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full du-
plex, and PCI 33 MHz system interface.
Table 10. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuit s
D3cold - wake
disabled
D3cold wake-
enabled @
10 Mbps
D0 @10 Mbps
active D0 @100 Mbp s
active
D0 @
1000 Mbps
active
Typ Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)bTyp Icc
(mA)aMax
Icc
(mA)b
Table 11. I/O Characteristics (Sheet 1 of 2)
Symbol Parameter Condition Min Typ Max Units
VIH Input high voltage 3.3 V PCI 0.5 * VDD(3.3) VDD(3.3) or
VIO V
VIL Input low voltage 3.3 V PCIaVSS 0.3 * VDD(3.3) V
IIN
Input current 0 < VIN < VDD(3.3) -10 10
µA
Input with pull-
down resistor (50
KΩ)VIN = VDD(3.3) 28 191
Inputs with pull-up
resistor (50 KΩ)VIN = VSS -28 -191
IOL Output low
current
3.3 V PCI 2.09
mA
0 ≤ VOUT ≤ 3.6V 100 * VOUT
0 ≤ VOUT ≤ 1.3V 48 * VOUT
1.3V ≤ VOUT ≤ 3.6V 5.7 * VOUT+ 55
IOH Output high
current:
0 ≤ (VDD-VOUT) ≤
3.6V -74 * (VDD -
VOUT)
mA
0 ≤ (VDD-VOUT) ≤
1.2V -32 * (VDD -
VOUT)
1.2V ≤ (VDD-VOUT) ≤
1.9V -11 * (VDD -
VOUT)-25.2
1.9V ≤ (VDD-VOUT) ≤
3.6V -1.8 * (VDD -
VOUT)-42.7
VOH Output high
voltage: V
3.3 V PCI IOH = -500 mA 0.9 * VDD(3.3)
82541ER Gigabit Ethernet Controller
21
4.4 AC Characteristics
VOL Output low
voltage: V
3.3 V PCI IOL = 1500 mA 0.1 * VDD(3.3)
IOZ Off-st ate output
leakage current VO = VDD or VSS -10 10 µA
IOS Output short
circuit current -250 mA
CIN Input
capacitancebInput and bi-
directional buffers 8pF
a. The maximum VIL is 0.6 V for the following Pins: A13, C5, C8, J4, L7, L12, L13, M8, M12, M13, N10, N11, N13, N14, P9, and P13.
b. VDD (3.3) = 0 V; TA = 25 C; f = 1 Mhz
Table 12. AC Characteristics: 3.3 V Interfacing
Symbol Parameter Min Typ Max Unit
PCICLK Clock frequency in PCI mode 66 MHz
Table 13. 25 MHz Clock Input Requirements
Symbol Parameter Specifications Units
Min Typ Max
f0 Frequency 25 MHz
df0 Frequency variation -50 +30 ppm
Dc Duty cycle 40 60 %
tr Rise time 5 ns
tf Fall time 5 ns
Jptp Clock jitter (peak-to-peak)a
a. Clock jitter is defined according to the recommendat ions of part 40.6.1.2.5 IEEE 1000BASE- T Standard (at least
105 clock edges, filtered by HPF with cut off frequency 5000 Hz).
250 ps
Cin Input capacitance 20 pF
T Operating temperature 70 ° C
Aptp Input clock amplitude (peak-to-peak) 1.0 1.2 1.3 V
Vcm Clock common mode 0.6 V
Table 11. I/O Characteristics (Sheet 2 of 2) (Continued)
Symbol Parameter Condition Min Typ Max Units
82541ER Gigabit Ethernet Controller
22
Table 14. Reference Crystal Specification Requirements
Specification Value
Vibrational Mode Fundamental
Nominal Frequency 25. 000 MHz at 25° C
Frequency Tolerance ±30 ppm
Temperature S tability ± 30 ppm at 0° C to 70° C
Calibration Mode Parallel
Load Capacitance 20 pF to 24 pF
Shunt Capacitance 6 pF maximum
Series Resistance, Rs 50 W maximum
Drive Level 0.5 mW maximum
Aging ±5.0 ppm per year maximum
Insulation Resistance 500 MΩ at DC 100 V
Table 15. Link Interface Clock Requirements
Symbol Parameter Min Typ Max Unit
fGTXaGTX_ CLK frequency 125 MHz
a. GTX_CLK is used externally for test purposes only.
Table 16. EEPROM Interface Clock Requirements
Symbol Parameter Min Typ Max Unit
fSK Microwire EEPROM Clock 1 MHz
SPI EEPR OM Clock 2 MHz
Table 17. AC Test Loads for General Output Pins
Symbol Signal Name Value Units
CL TDO 10 pF
CL SDP[3:0] 16 pF
CL EEDI, EESK 18 pF
CL LED[3:0] 20 pF
82541ER Gigabit Ethernet Controller
23
Figure 2. AC Test Loads for General Output Pins
4.5 Timing Specifications
4.5.1 PCI Bus Interf ace
4.5.1.1 PCI Bus Interface Clock
Figure 3. PCI Clock Timing
C
L
Table 18. PCI Bus Interface Clock Parameters
Symbol Parametera
a. Rise and fall times a re specified in te rms of t he edge rate me asured in V/ns. Thi s slew rate mu st be me t across th e
minimum peak-to-peak portion of the clock waveform as shown.
PCI 66 MHz PCI 33 MHz Units
Min Max Min Max
TCYC CLK cycle time 15 30 30 ns
TH CLK high time 6 11 ns
TL CLK low time 6 11 ns
CLK slew rate 1.5 4 1 4 V/ns
RST# slew rateb
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system
noise cannot render a monotonic signal to appear bouncing in the switching range.
50 50 mV/ns
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
Tcyc
Th
Tl
0.4 Vcc p-to-p
(minimum)
3.3 V Clock
PCI Clock Timing.vsd
82541ER Gigabit Ethernet Controller
24
4.5.1.2 PCI/PCI-X Bus Interface Timing
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have dif ferent output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Figure 4. PCI Bus Interface Output Timing Measurement
Table 19. PCI Bus Interface Timing Parameters
Symbol Parameter PCI 66 MH z PCI 3 3 MH z Units
MinMaxMinMax
TVAL CLK to signal valid delay: bussed
signals 26211ns
TVAL(ptp) CLK to signal valid delay: point-
to-point signals 26212ns
TON Float to active delay 2 2 ns
TOFF Active to float delay 14 28 ns
TSU Input setup time to CLK: bussed
signals 37ns
TSU(ptp) Input setup time to CLK: point-to-
point signals 5 10, 12 ns
TH Input hold time from CLK 0 0 ns
VTH
VTL
VTEST
PCI_CLK
VTEST
VSTEP (3.3V Signalling
)
Output
Delay
Tri-State
Output
output current ≤
leakage current
TONTOFF
82541ER Gigabit Ethernet Controller
25
Figure 5. PCI Bus Interface Input Timing Measurement Condit ions
Figure 6. TVAL (max) Rising Edge Test Load
VTH
VTL
VTEST
PCI_CLK
T
SU
VTEST
Input VMAX
VTEST
VTL
VTH
Input
Valid
TH
Table 20. PCI Bus Interface Timing Measurement Conditions
Symbol Parameter PCI 66 MHz
3.3 v Unit
VTH Input measurement test voltage (high) 0.6 * VCC V
VTL Input measurement test voltage (low) 0.2 * VCC V
VTEST Output measurement test voltage 0.4 * VCC V
Input signal slew rate 1.5 V/ns
10 pF
25Ω
Pin Te s t
Poin
t
1/2 inch max.
82541ER Gigabit Ethernet Controller
26
Figure 7. TVAL (max) Falling Edge Test Load
Figure 8. TVAL (min) Test Load
Figure 9. TVAL Test Load (PCI 5 V Signaling Environment)
NOTE: Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
10 pF
25Ω
Pin Te s t
Poin
t
1/2 inch max.
V
CC
50 pF
Pin Test
Point
1/2 inch max.
82541ER Gigabit Ethernet Controller
27
4.5.2 Link Interface Timing
Figure 10. Link Interface Rise/Fall Timing
4.5.3 EEPROM Interface
Table 21. Rise and Fall Times
Symbol Parameter Condition Min Max Unit
TR Clock rise tim e 0.8 V to 2.0 V 0.7 ns
TF Clock fall time 2.0 V to 0.8 V 0.7 ns
TR Data rise time 0.8 to 2.0 V 0.7 ns
TF Data fall time 2.0 V to 0.8 V 0.7 ns
2.0 V
0.8 V
T
F
T
R
Table 22. Link Interface Clock Requirements
Symbol Parametera
a. The EEPROM clock is derived from a 125 MHz internal clock.
Min Typ Max Unit
TPW Microwire EESK pulse width TPERIOD x
64 ns
SPI EESK pulse width TPERIOD x
32 ns
Table 23. Link Interface Clock Requirements
Symbol ParameteraMin Typ Max Unit
TDOS EEDO setup time TCYC*2 ns
TDOH EEDO hold time 0 ns
a. The EE_DO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EE_SK.
82541ER Gigabit Ethernet Controller
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82541ER Gigabit Ethernet Controller
29
5.0 Package and Pinout Information
This section describes the device physical characteristics. The pin number-to-signal mapping is
indicated beginning with Table 25.
5.1 Package Information
The 82541ER device i s a 196 -l ead plas ti c bal l gri d ar ray (B GA ) meas uring 15 m m by 1 5 mm . The
package dimensions are detailed below. The nominal ball pitch is 1 mm.
Figure 11. 82541ER Mechanical Specifications
Note: No changes to exis ting soldering processes are needed for the 0.32 mm substrate change.
0.32 +/-0.04
0.40 +/-0.10 Seating Plate
0.85
1.56 +/-0.19
30 o
82541ER Gigabit Ethernet Controller
30
Figure 12. 196 PBGA Package Pad Detail
As illustrated in Figure 12, the Ethernet controller package uses solder mask defined pads. The
copper area is 0.60 mm and the opening in the solder mask is 0.45mm. The nominal ball sphere
diameter is 0.50 mm.
0.45
Solder Resist Opening
0.60
Metal Diameter
Detail Area
82541ER Gigabit Ethernet Controller
31
5.2 Thermal S pecificati ons
The 82541ER device is specified for operation when the ambient temperature (TA) is within the
range of 0° C to 70° C.
TC (case temperature) is calculated using the equation:
TC = TA + P (θJA - θJC)
TJ (junction temperature) is calculated using the equation:
TJ = TA + P θJA
P (power consumption) is calculated by using the typical ICC and nominal VCC. The preliminary
thermal resistances are shown in Table 24.
Thermal resistances are determined empirically with test devices mounted on standard thermal test
boards. R eal system designs may hav e dif ferent character istics due to board thickness, arr angement
of ground planes, and proximity of other components. The case temperature measurements should
be used to assure that the 82541ER device is operating under recommended conditions.
Table 24. Thermal Characteristics
Symbol Parameter
Preliminary Value at specified
airflow (m/s) Units
012
θJA Thermal resistance, junction-to-ambient 29 25.0 23.5 C/Watt
θJC Thermal resistance, junction-to-case 11.1 11. 1 11. 1 C/Watt
82541ER Gigabit Ethernet Controller
32
5.3 Pi nout Infor matio n
Table 25. PCI Address, Data and Control Signals
Signal Pin Signal Pin Signal Pin
AD[0] N7 AD[16] K1 C/BE#[0] M4
AD[1] M7 AD[17] E3 C/BE#[1] L3
AD[2] P6 AD[18] D1 C/BE#[2] F3
AD[3] P5 AD[19] D2 C/BE#[3] C4
AD[4] N5 AD[20] D3 PAR J1
AD[5] M5 AD[21] C1 FRAME# F2
AD[6] P4 AD[22] B1 IRDY# F1
AD[7] N4 AD[23] B2 TRDY# G3
AD[8] P3 AD[24] B4 STOP# H1
AD[9] N3 AD[25] A5 DEVSEL# H3
AD[10] N2 AD[26] B5 IDSEL A4
AD[11] M1 AD[27] B6 VIO G2
AD[12] M2 AD[28] C6
AD[13] M3 AD[29] C7
AD[14] L1 AD[30] A8
AD[15] L2 AD[31] B8
Table 26. PCI Arbitration Signals
Signal Pin
REQ# C3
GNT# J3
Table 27. Interrupt Signals
Signal Pin
INTA# H2
Table 28. System Signals
Signal Pin Signal Pin
CLK G1 RST# B9
M66EN C2
82541ER Gigabit Ethernet Controller
33
Table 29. Error Reporting Signals
Signal Pin Signal Pin
SERR# A2 PERR# J2
Table 30. Power Management Signals
Signal Pin
LAN_PWR_GOOD A9
AUX_PWR J12
Table 31. Serial EEPROM Interface Signals
Signal Pin Signal Pin Signal Pin
EESK M10 EEDI P10 EECS P7
EEDO N10 EEMODE J4
Table 32. Serial FLASH Interface Signals
Signal Pin Signal Pin Signal Pin
FLSH_SCK N9 FLSH_SI M11 FLSH_CE# M9
FLSH_SO/LAN_DISABLE# P9
Table 33. LED Signals
Signal Pin Signal Pin
LINK_UP# A12 LINK100# B11
ACTIVITY# C11 LINK1000# B12
Table 34. Other Signals
Signal Pin Signal Pin
SDP[0] N14 SDP[2] N13
SDP[1] P13 SDP[3] M12
82541ER Gigabit Ethernet Controller
34
Table 35. IEEE Test Signals
Signal Pin Signal Pin
IEEE_TEST- D14 IEEE_TEST+ B14
Table 36. PHY Sig nals
Signal Pin Signal Pin Signal Pin
MDI[0]- C14 MDI[2]- F14 XTAL1 K14
MDI[0]+ C13 MDI[2]+ F13 XTAL2 J14
MDI[1]- E14 MDI[3]- H14
MDI[1]+ E13 MDI[3]+ H13
Table 37. Test Interface Signals
Signal Pin Signal Pin Signal Pin
JTAG_TCK L14 JTAG_TDO M14 JTAG_TRST# L13
JTAG_TDI M13 JTAG_TMS L12 TEST A13
Table 38. Digital Power Signals
Signal Pin Signal Pin Signal Pin
3.3V A3 1.2V G5 1.2V J9
3.3V A7 1.2V G6 1.2V K10
3.3V A11 1.2V H5 1.2V K11
3.3V E1 1.2V H6 1.2V K5
3.3V K3 1.2V H7 1.2V K6
3.3V K4 1.2V H8 1.2V K7
3.3V K13 1.2V J10 1.2V K8
3.3V N6 1.2V J11 1.2V K9
3.3V N8 1.2V J5 1.2V L10
3.3V P2 1.2V J6 1.2V L4
3.3V P12 1.2V J7 1.2V L5
1.2V J8 1.2V L9
82541ER Gigabit Ethernet Controller
35
Table 39. Analog Power Signals
Signal Pin Signal Pin Signal Pin
ANALOG_1.2V E11 ANALOG_1.8V D11 CLKR_1.8V D12
ANALOG_1.2V E12 ANALOG_1.8V G12 XTAL_1.8V J13
ANALOG_1.2V G13 PLL_1.2V G4
ANALOG_1.2V H11 PLL_1.2V H4
Table 40. Grounds and No Connect Signals
Signal Pin Signal Pin Signal Pin Signal Pin
VSS B3 VSS F5 VSS M6 NC L8
VSS B7 VSS F6 VSS N1 NC P1
VSS C10 VSS F7 VSS N12 NC P14
VSS D5 VSS F8 VSS P8 Pull up to
VCCaA10
VSS D6 VSS F9 AVSS C12 Pull up to
VCCaB10
VSS D7 VSS F10 AVSS D13 Pull up to
VCCaC9
VSS D8 VSS G7 AVSS F11 VSS D4
VSS E10 VSS G8 AVSS G11 VSS E4
VSS E2 VSS G9 AVSS G14 NC A6
VSS E5 VSS G10 AVSS K12 NC C5
VSS E6 VSS H9 NC A1 NC F12
VSS E7 VSS H10 NC A14 NC L7
VSS E8 VSS K2 NC D9 NC M8
VSS E9 VSS L6 NC D10 NC N11
VSS F4 VSS L11 NC H12 NC C8
a. Use a 1 K Ω resistor.
Table 41. Voltage Regulation Control Signals
Signal Pin Signal Pin
CTRL18 B13 CTRL12 P11
82541ER Gigabit Ethernet Controller
36
Table 42. Signal Names in Pin Order (Sheet 1 of 6)
Signal Name Pin
NC A1
SERR# A2
3.3V A3
IDSEL A4
AD[25] A5
NC A6
3.3V A7
AD[30] A8
LAN_PWR_GOOD A9
Pull up to VCCaA10
3.3V A11
LINK_LED# A12
TEST A13
NC A14
AD[22] B1
AD[23] B2
VSS B3
AD[24] B4
AD[26] B5
AD[27] B6
VSS B7
AD[31] B8
RST# B9
Pull up to VCCaB10
LINK100# B11
LINK1000# B12
CTRL18 B13
IEEE_TEST+ B14
AD[21] C1
M66EN C2
REQ# C3
C/BE#[3] C4
NC C5
AD[28] C6
82541ER Gigabit Ethernet Controller
37
AD[29] C7
NC C8
Pull up to VCCaC9
VSS C10
ACTIVITY# C11
AVSS C12
MDI[0]+ C13
MDI[0]- C14
AD[18] D1
AD[19] D2
AD[20] D3
VSS D4
VSS D5
VSS D6
VSS D7
VSS D8
NC D9
NC D10
ANALOG_1.8V D11
CLKR_1.8V D12
AVSS D13
IEEE_TEST- D14
3.3V E1
VSS E2
AD[17] E3
VSS E4
VSS E5
VSS E6
VSS E7
VSS E8
VSS E9
VSS E10
ANALOG_1.2V E11
ANALOG_1.2V E12
MDI[1]+ E13
MDI[1]- E14
Table 42. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
82541ER Gigabit Ethernet Controller
38
IRDY# F1
FRAME# F2
C/BE#[2] F3
VSS F4
VSS F5
VSS F6
VSS F7
VSS F8
VSS F9
VSS F10
AVSS F11
NC F12
MDI[2]+ F13
MDI[2]- F14
CLK G1
VIO G2
TRDY# G3
PLL_1.2V G4
1.2V G5
1.2V G6
VSS G7
VSS G8
VSS G9
VSS G10
AVSS G11
ANALOG_1.8V G12
ANALOG_1.2V G13
AVSS G14
STOP# H1
INTA# H2
DEVSEL# H3
PLL_1.2V H4
1.2V H5
1.2V H6
1.2V H7
1.2V H8
VSS H9
Table 42. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
82541ER Gigabit Ethernet Controller
39
VSS H10
ANALOG_1.2V H11
NC H12
MDI[3]+ H13
MDI[3]- H14
PAR J1
PERR# J2
GNT# J3
EEMODE J4
1.2V J5
1.2V J6
1.2V J7
1.2V J8
1.2V J9
1.2V J10
1.2V J11
AUX_PWR J12
XTAL_1.8V J13
XTAL2 J14
AD[16] K1
VSS K2
3.3V K3
3.3V K4
1.2V K5
1.2V K6
1.2V K7
1.2V K8
1.2V K9
1.2V K10
1.2V K11
AVSS K12
3.3V K13
XTAL1 K14
AD[14] L1
AD[15] L2
C/BE#[1] L3
1.2V L4
Table 42. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
82541ER Gigabit Ethernet Controller
40
1.2V L5
VSS L6
NC L7
NC L8
1.2V L9
1.2V L10
VSS L11
JTAG_TMS L12
JTAG_TRST# L13
JTAG_TCK L14
AD[11] M1
AD[12] M2
AD[13] M3
C/BE#[0]# M4
AD[5] M5
VSS M6
AD[1] M7
NC M8
FLSH_CE# M9
EESK M10
FLSH_SI M11
SDP[3] M12
JTAG_TDI M13
JTAG_TDO M14
VSS N1
AD[10] N2
AD[9] N3
AD[7] N4
AD[4] N5
3.3V N6
AD[0] N7
3.3V N8
FLSH_SCK N9
EEDO N10
NC N11
VSS N12
SDP[2] N13
Table 42. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
82541ER Gigabit Ethernet Controller
41
SDP[0] N14
NC P1
3.3V P2
AD[8] P3
AD[6] P4
AD[3] P5
AD[2] P6
EECS P7
VSS P8
FLSH_SO P9
EEDI P10
CTRL12 P11
3.3V P12
SDP[1] P13
NC P14
a. Use a 1 K Ω resistor.
Table 42. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
82541ER Gigabit Ethernet Controller
42
5.4 Vis ual Pin Assignments
Figure 13. Visual Pin Assignments
AD[22] AD[21] AD[18] 3.3V IRDY# CLK STOP# PA R NCVSSAD[11]AD[14]AD[16]NC
AD[23] M66EN AD[19] VSS FRAME# VIO INTA# PERR# 3.3VAD[10]AD[12]AD[15]VSS
SERR#
VSS REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# AD[8]AD[9]AD[13]C/B3#[1]3.3V3.3V
AD[24] C/BE#[3] VSS VSS VSS PLL_1.2V EEMODE AD[6]AD[7]
C/BE#[0]
1.2V3.3VIDSEL
AD[26] NC VSS VSS VSS 1.2V AD[3]AD[4]AD[5]1.2VAD[25]
AD[27] AD[28] VSS VSS VSS 1.2V AD[2]3.3VVSSVSS NC
VSS AD[29] VSS VSS VSS VSS EECSAD[0]AD[1]NC3.3V
AD[31] VSS VSS VSS VSS VSS
3.3V
NC
NCAD[30]
RST# Pull Up To
VCC NC VSS VSS VSS VSS FLSH_SOFLSH_SCKFLSH_CE#1.2V
LAN_PWR_
GOOD
VSS NC VSS VSS VSS EEDI
EEDO
EESK
1.2V
Pull Up To
VCC
LINK100# ACTIVITY# ANALOG_
1.8V AVSS AVSS CTRL12
NCFLSH_SIVSS3.3V
LINK1000# AVSS NC NC AUX_PWR 3.3V
VSS
SDP[3]
JTAG_TMS
AVSS
LINK_LED#
CTRL18 MDI[0]+ AVSS XTAL_1.8V SDP[1]SDP[2]
JTAG_TDI
JTAG_TRST#
3.3V
TEST
IEEE_TEST+ AVSS XTAL2 NC
JTAG_TDO
JTAG_TCK
XTAL1NC
ABCDEFGHJKL
MNP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pull Up To
VCC
MDI[0]-
CLKR_
1.8V
IEEE_TEST-
ANALOG_
1.2V
ANALOG_
1.2V
VSS
MDI[1]+
MDI[1]-
MDI[2]+
MDI[2]-
ANALOG_
1.2V
ANALOG_
1.8V
PLL_1.2V
1.2V
1.2V
1.2V
1.2V
ANALOG_
1.2V
MDI[3]+
MDI[3]-
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
SDP[0]
NC
Pins A10, B-10, and C9 - Use 1K ohm resistors.
Datasheet 1
82541ER Gigabit Ethernet Controller
1 Absolute Maximum Ratings................................................................................ 15
2 Recommended Operating Conditions ................................................................ 15
3 3.3V Supply Voltage Ramp................................................................................. 16
4 1.8V Supply Voltage Ramp................................................................................. 16
5 1.2V Supply Voltage Ramp................................................................................. 17
6 DC Characteristics.............................................................................................. 18
7 P owe r Specifi catio ns - D0a.... .......................... .......................... ......................... 18
8 P owe r Specifi catio ns - D3cold...... ...... ....... ......................................................... 18
9 Power Specifications D(r) Uninitialized).............................................................. 19
10 Power Specifi catio ns - Complet e Subs yste m......... ...... ...... ....... ......................... 19
11 I/O Characteristics.............................................................................................. 20
12 AC Characteristics: 3.3 V Interfacing.................................................................. 21
13 25 MHz Clock Input Requirements..................................................................... 21
14 Reference Crystal Specification Requirements.................................................. 22
15 Link Interface Clock Requirements..................................................................... 22
16 EEPROM Interface Clock Requirements............................................................ 22
17 AC Test Loads for General Output Pins............................................................. 22
18 PCI Bus Interface Clock Parameters.................................................................. 23
19 PCI Bus Interface Timing Parameters................................................................ 24
20 PCI Bus Interface Timing Measurement Conditions........................................... 25
21 Rise and Fall Times............................................................................................ 27
22 Link Interface Clock Requirements..................................................................... 27
23 Link Interface Clock Requirements..................................................................... 27
24 Thermal Characteristics...................................................................................... 31
25 PCI Address, Data and Control Signals.............................................................. 32
26 PCI Arbitration Signals........................................................................................ 32
27 Interrupt Signals.................................................................................................. 32
28 System Signals................................................................................................... 32
29 Error Reporting Signals ...................................................................................... 33
30 Power Management Signals............................................................................... 33
31 Serial EE PRO M Inte rface Signals...... ....... ...... ............................................. ...... 33
32 Serial FLASH Interface Signals.......................................................................... 33
33 LED Signa ls........ ...... ....... ...... ....... ...... ....... ...... ....... ...... .......................... ............ 33
34 Other Signals...................................................................................................... 33
35 IEEE Test Signals............................................................................................... 34
36 PHY Signals........................................................................................................ 34
37 Test Interface Signals...... ...... ....... ............................................. ......................... 34
38 Digital Power Signals.......................................................................................... 34
39 Analog Power Signals......................................................................................... 35
40 Grounds and No Connect Signals...................................................................... 35
41 Voltage Regulation Control Signals.................................................................... 35
42 Signal Names in Pin Order................................................................................. 36
82541ER Gigabit Ethernet Controller
2 Datasheet
Datasheet 1
82541ER Gigabit Ethernet Controller
1 82541ER Block Diagram ...................................................................................... 3
1 AC Test Loads for General Output Pins............................................................. 23
2 PCI Clock Timing................................................................................................ 23
3 PCI Bus Interface Output Timing Measurement................................................. 24
4 PCI Bus Interface Input Timing Measurement Conditions.................................. 25
5 TVAL (max) Rising Edge Test Load................................................................... 25
6 TVAL (max) Falling Edge Test Load................................................................... 26
7 TVAL (min) Test Load......................................................................................... 26
8 TVAL Test Load (PCI 5 V Signaling Environment)............................................. 26
9 Link Interface Rise/Fall Timing ........................................................................... 27
10 82541ER Mechanical Specifications .................................................................. 29
11 196 PBGA Package Pad Detail.......................................................................... 30
12 Visual Pin Assignments...................................................................................... 42
