SN74LS85MR1 - ON Semiconductor

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6 1Publication Order Number:

SN74LS85/D

SN74LS85

4-Bit Magnitude

Comparator

The SN74LS85 is a 4-Bit Magnitude Camparator which compares

two 4-bit words (A, B), each word having four Parallel Inputs

(A0–A3, B0–B3); A3, B3 being the most significant inputs. Operation

is not restricted to binary codes, the device will work with any

monotonic code. Three Outputs are provided: “A greater than B”

(OA>B), “A less than B” (OA<B), “A equal to B” (OA=B). Three

Expander Inputs, IA>B, IA<B, IA=B, allow cascading without external

gates. For proper compare operation, the Expander Inputs to the least

significant position must be connected as follows: IA<B= IA>B = L,

IA=B = H. For serial (ripple) expansion, the OA>B, OA<B and OA=B

Outputs are connected respectively to the IA>B, IA<B, and IA=B

Inputs of the next most significant comparator, as shown in Figure 1.

Refer to Applications section of data sheet for high speed method of

comparing lar ge words.

The Truth T able on the following page describes the operation of the

SN74LS85 under all possible logic conditions. The upper 11 lines

describe the normal operation under all conditions that will occur in a

single device or in a series expansion scheme. The lower five lines

describe the operation under abnormal conditions on the cascading

inputs. These conditions occur when the parallel expansion technique

is used.

•Easily Expandable

•Binary or BCD Comparison

•OA>B, OA<B, and OA=B Outputs Available

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 4.75 5.0 5.25 V

TAOperating Ambient

Temperature Range 0 25 70 °C

IOH Output Current – High –0.4 mA

IOL Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS85N 16 Pin DIP 2000 Units/Box

SN74LS85D 16 Pin

SOIC

D SUFFIX

CASE 751B

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2500/Tape & Reel

PLASTIC

N SUFFIX

CASE 648

SN74LS85

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LOGIC SYMBOL

CONNECTION DIAGRAM DIP (TOP VIEW)

Parallel Inputs

A = B Expander Inputs

A < B, A > B, Expander Inputs

A Greater than B Output

B Greater than A Output

A Equal to B Output

A0 – A3, B0 – B3

IA = B

IA < B, IA > B

OA > B

OA < B

OA = B

1.5 U.L.

0.5 U.L.

10 U.L.

0.75 U.L.

0.25 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

A HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES

VCC = PIN 16

GND = PIN 8

10 12 13 15 9 11 14 1

A0A1A2A3B0B1B2B3

IA>B

IA<B

IA=B

OA>B

OA<B

OA=B

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

14 13 12 11 10 9

1234567

16 15

VCC

A3B2A2A1A0

B1B0

IA<B IA=B IA>B OA>B OA=B OA<B GND

H = HIGH Level

L = LOW Level

X = IMMATERIAL

SN74LS85

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LOGIC DIAGRAM

OA>B

OA<B

OA=B

(5)

(6)

(7)

A<B

A=B

A>B

(15)

(1)

(13)

(14)

(12)

(11)

(10)

(9)

(2)

(3)

(4)

TRUTH TABLE

COMPARING INPUTS CASCADING

INPUTS OUTPUTS

A3,B3A2,B2A1,B1A0,B0IA>B IA<B IA=B OA>B OA<B OA=B

A3>B3X X X X X X H L L

A3<B3XXXXXX L HL

A3=B3A2>B2XXXXX H LL

A3=B3A2<B2XXXXX L HL

A3=B3A2=B2A1>B1XXXX H LL

A3=B3A2=B2A1<B1XXXX L HL

A3=B3A2=B2A1=B1 A0>B0XXX H LL

A3=B3A2=B2A1=B1A0<B0XXX L HL

A3=B3A2=B2A1=B1A0=B0HLL H LL

A3=B3A2=B2A1=B1A0=B0LHL L HL

A3=B3A2=B2A1=B1A0=B0XXH L LH

A3=B3A2=B2A1=B1A0=B0HHL L LL

A3=B3A2=B2A1=B1A0=B0L L L H H L

NOTE:

The SN74LS85 can be used as a 5-bit comparator only

when the outputs are used to drive the A0–A3 and B0–B3

inputs of another SN74LS85 as shown in Figure 2 in posi-

tions #1, 2, 3, and 4.

SN74LS85

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Figure 1. Comparing Two n-Bit Words

L = LOW LEVEL

H = HIGH LEVEL

A0A1A2A3B0B1B2B3

A0A1A2A3B0B1B2B3A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

A > B

A < B

A = B

SN74LS85 SN74LS85

An3

An2

An1

Bn3

Bn2

Bn1

APPLICATIONS

Figure 2 shows a high speed method of comparing two

24-bit words with only two levels of device delay. W ith the

technique shown in Figure 1, six levels of device delay result

when comparing two 24-bit words. The parallel technique

can be expanded to any number of bits, see Table 1.

Table 1

WORD LENGTH NUMBER OF PKGS.

1–4 Bits 1

5–24 Bits 2–6

25–120 Bits 8–31

MSB = MOST SIGNIFICANT BIT

LSB = LEAST SIGNIFICANT BIT

L = LOW LEVEL

H = HIGH LEVEL

NC = NO CONNECTION

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

(LSB)

INPUTS

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

LNC

A20 A21 B23

B22

B21

B20

A23

A22

A19

B19

(MSB)

A5A6A7A8B5B6B7B8

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

A10 A11 B13

B12

B11

B10

A13

A12

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

A14

B14

A15 A16 B18

B17

B16

B15

A18

A17

OUTPUTS

A0A1A2A3B0B1B2B3

IA > B

IA < B

IA = B

OA > B

OA < B

OA = B

INPUTS

Figure 2. Comparison of Two 24-Bit Words

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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for

All Inputs

VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

Out

ut LOW Voltage

0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN =V

IL or VIH

LOW

Voltage

0.35 0.5 V IOL = 8.0 mA

IN =

per T ruth Table

IIH

Input HIGH Current

A < B, A > B

Other Inputs 20

60 µA VCC = MAX, VIN = 2.7 V

A < B, A > B

Other Inputs 0.1

0.3 mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

A < B, A > B

Other Inputs –0.4

–1.2 mA VCC = MAX, VIN = 0.4 V

IOS Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 20 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits

Symbol Parameter Min Typ Max Unit Test Conditions

tPLH

tPHL Any A or B to A < B, A > B 24

20 36

30 ns

tPLH

tPHL Any A or B to A = B 27

23 45

45 ns

tPLH

tPHL A < B or A = B to A > B 14

11 22

17 ns VCC = 5.0 V

CL = 15 pF

tPLH

tPHL A = B to A = B 13

13 20

26 ns

tPLH

tPHL A > B or A = B to A < B 14

11 22

17 ns

AC WAVEFORMS

Figure 3. Figure 4.

VIN

VOUT

1.3 V

tPHL

1.3 V

1.3 V 1.3 V

tPLH

VIN

VOUT

1.3 V

tPHL

1.3 V

1.3 V 1.3 V

tPLH

SN74LS85

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PACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

SN74LS85

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PACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

SN74LS85

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