1
EM MICROELECTRONIC-MARIN SA A6150
High Efficiency Linear Power Supply with
Power Surveillance and Software Monitoring
Features
Highly accurate 5 V, 100 mA guaranteed output
Low dropout voltage, typically 380 mV at 100 mA
Low quiescent current, typically 175 µA
Standby mode, maximum current 340 µA (with
100 µA load on OUTPUT)
Unregulated DC input can withstand –20 V reverse
battery and + 60 V power transients
Fully operational for unregulated DC input voltage
up to 26 V and regulated output voltage down to 3.0 V
Reset output guaranteed for regulated output voltage
down to 1.2 V
No reverse output current
Very low temperature coefficient for the regulated output
Current limiting
Comparator for voltage monitoring,voltage reference
1.52 V
Programmable reset voltage monitoring
Programmable power on reset (POR ) delay
Watchdog with programmable time windows guarant-
ees a minimum time and a maximum time between
software clearing of the watchdog
Time base accuracy ± 10%
System enable output offers added security
TTL/CMOS compatible
-40 to +85 °C temperature range
On request extended temperature range,-40 to +125 °C
DIP8 and SO8 packages
Description
The A6150 offers a high level of integration by combining
voltage regulation, voltage monitoring and software
monitoring in an 8 lead package. The voltage regulator
has a low dropout voltage (typ. 380 mV at 100 mA) and a
low quiescent current (175 µA). The quiescent current
increases only slightly in dropout prolonging battery life.
Built-in protection includes a positive transient absorber for
up to 60 V (load dump) and the ability to survive an
unregulated input voltage of –20 V (reverse battery). The
input may be connected to ground or a reverse voltage
without reverse current flow from the output to the input. A
comparator monitors the voltage applied at the VIN input
comparing it with an internal 1.52 V reference. The power-
on reset function is initialized after VIN reaches 1.52 V and
takes the reset output inactive after TPOR depending of
external resistance. The reset output goes active low when
the VIN voltage is less than 1.52 V. The RES and EN
outputs are guaranteed to be in a correct state for a
regulated output voltage as low as 1.2 V. The watchdog
function monitors software cycle time and execution. If
software clears the watchdog too quickly (incorrect
cycle time) or too slowly (incorrect execution) it will
cause the system to be reset. The system enable
output prevents critical control functions being
activated until software has successfully cleared the
watchdog three times. Such a security could be used
to prevent motor controls being energized on
repeated resets of a faulty system.
Applications
Automotive systems
Cellular telephones
Security systems
Battery powered products
High efficiency linear power supplies
Automotive electronics
Typical Operating Configuration
Pin Assignment
5 V
Fig. 1
GND
A6150
VIN
TCL
RES
EN
R
VSS
INPUT OUTPUT
Unregu-
lated
voltage
Version A0:
Version A1:
DIP8/ SO8
OUTPUT
Fig. 2
VIN
R
INPUT
A6150
EN
RES
TCL
VSS
2
A6150
Absolute Maximum Ratings
Parameter Symbol Conditions
Continuous voltage at INPUT
to VSS VINPUT -0.3 to + 30 V
Transients on INPUT for
t < 100 ms and duty cycle 1% VTRANS up to + 60 V
Reverse supply voltage on INPUT VREV - 20 V
Max. voltage at any signal pin VMAX OUTPUT + 0.3 V
Min. voltage at any signal pin VMIN VSS – 0.3 V
Storage temperature TSTO -65 to + 150 °C
Electrostatic discharge max. to
MIL-STD-883C method 3015 VSmax 1000 V
Max. soldering conditions TSmax 250 °C x 10 s
Table 1
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure be-
yond specified operating conditions may affect device
reliability or cause malfunction.
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precau-
tions must be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only
occur when all terminal voltages are kept within the
supply voltage range. At any time, all inputs must be tied
to a defined logic voltage level.
Operating Conditions
Parameter Symbol Min. Typ. Max. Units
Operating junction
temperature 1) TJ-40 +125 °C
INPUT voltage 2) VINPUT 2.3 26 V
OUTPUT voltage 2) 3) VOUTPUT 1.2 V
RES & EN guaranteed 4) VOUTPUT 1.2 V
OUTPUT current 5) IOUTPUT 100 mA
Comparator input
voltage VIN 0V
OUTPUT V
RC-oscillator
programming R 10 1000 kΩ
Thermal resistance from
junction to ambient 6)
-DIP8 Rth(j-a) 105 °C/W
-SO8 Rth(j-a) 160 °C/W
Table 2
1) The maximum operating temperature is confirmed by
sampling at initial device qualification. In production, all
devices are tested at +85 °C. On request devices tested at
+125 °C can be supplied.
2) Full operation quaranteed. To achieve the load regulation
specified in Table 3 a 22 µF capacitor or greater is
required on the INPUT, see Fig. 18. The 22 µF must have
an effective resistance ≤ 5 Ω and a resonant frequency
above 500 kHz.
3) A 10 µF load capacitor and a 100 nF decoupling capacitor
are required on the regulator OUTPUT for stability. The
10 µF must have an effective series resistance of ≤ 5 Ω and
a resonant frequency above 500 kHz.
4) RES and EN (EN only for version A0) must be pulled up
externally to VOUTPUT even if they are unused. (Note: RES
and EN are used as inputs by EM test).
5) The OUTPUT current will not apply for all possible
combinations of input voltage and output current.
Combinations that would require the A6150 to work above
the maximum junction temperature (+125 °C) must be
avoided.
6) The thermal resistance specified assumes the package is
soldered to a PCB.
3
A6150
Electrical Characteristics
VINPUT = 6.0 V, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +85 °C, unless otherwise specified
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Supply current in standby mode ISS REXT = don’t care, TCL = VOUTPUT,
VIN = 0 V, IL = 100 µA 340 µA
Supply current 1) ISS REXT = 100 kΩ, I/PS at VOUTPUT,
O/PS 1 MΩ to VOUTPUT, IL = 100 µA 175 400 µA
Supply current 1) ISS REXT = 100 kΩ, I/PS at VOUTPUT, VINPUT =
8.0 V, O/PS 1 MΩ to VOUTPUT, IL = 100 mA 1.7 4.2 mA
Output voltage VOUTPUT IL = 100 µA 4.88 5.12 V
Output voltage VOUTPUT 100 µA ≤ IL ≤ 100 mA,
-40 °C ≤ TJ ≤+125 °C 4.85 5.15 V
Output voltage temperature
coefficient 2) Vth(coeff) 50 180 ppm/°C
Line regulation 3) VLINE 6 V ≤ VINPUT ≤26 V, IL = 1 mA,
TJ = +125 °C0.20.5%
Load regulation 3) VL100 µA ≤ IL ≤ 100 mA 0.2 0.6 %
Dropout voltage 4) VDROPOUT IL = 100 µA 40 170 mV
Dropout voltage 4) VDROPOUT IL = 100 mA 380 mV
Dropout voltage 4) VDROPOUT IL = 100 mA, -40 °C ≤ TJ ≤+125 °C 650 mV
Dropout supply current ISS VINPUT = 4.5 V, IL = 100 µA,
REXT = 100 kΩ, O/PS 1 MΩ to
VOUTPUT, I/PS at VOUTPUT 1.2 1.6 mA
Thermal regulation 5) Vthr TJ = +25 °C, IL = 50 mA,
VINPUT = 26 V, T = 10 ms 0.05 0.25 %/W
Current limit ILmax OUTPUT tied to VSS 450 mA
OUTPUT noise, 10Hz to 100kHz VNOISE 200 µVrms
RES & EN
Output Low Voltage VOL VOUTPUT = 4.5 V, IOL= 20 mA 0.4 V
VOL VOUTPUT = 4.5 V, IOL = 8 mA 0.2 0.4 V
VOL VOUTPUT = 2.0 V, IOL = 4 mA 0.2 0.4 V
VOL VOUTPUT = 1.2 V, IOL = 0.5 mA 0.06 0.2 V
EN (vers. A1)
Output High Voltage VOH VOUTPUT = 4.5 V, IOH= -1 mA 3.5 4.1 V
VOH VOUTPUT = 2.0 V, IOH= -100 µA1.81.9V
VOH VOUTPUT = 1.2 V, IOH= -30 µA1.01.1V
TCL and VIN
TCL Input Low Level VIL VSS 0.8 V
TCL Input High Level VIH 2.0 VOUTPUT V
Leakage current ILI VSS ≤ VTCL ≤ VOUTPUT 0.05 1 µA
VIN input resistance RVIN 100 MΩ
VREF TJ = +25 °C 1.474 1.52 1.566 V
Comparator reference 6)7) VREF 1.436 1.620 V
VREF -40 °C ≤TJ ≤+125 °C 1.420 1.620 V
Comparator hysteresis 7) VHY 2mV
Table 3
1) If INPUT is connected to VSS, no reverse current will flow from the OUTPUT to the INPUT, however the supply current specified will
be sank by the OUTPUT to supply the A6150.
2) The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.
3) Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage
due to heating effects are covered in the specification for thermal regulation.
4) The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.
5) Thermal regulation is defined as the change in OUTPUT voltage at a time T after a change in power dissipation is applied,
excluding load or line regulation effects.
6) The comparator and the voltage regulator have separate voltage references (see “ Block Diagram” Fig. 7).
7) The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference
voltage plus the comparator hysteresis (see Fig. 4).
4
A6150
Timing Characteristics
V INPUT = 6.0 V, IL = 100 µA, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to + 85 °C, unless otherwise specified
Parameter Symbol Test Conditions Min. Typ. Max. Units
Propagation delays:
TCL to Output Pins TDIDO 250 500 ns
VIN sensitivity TSEN 1520
µs
Logic Transition Times on all Output Pins TTR Load 10 kΩ, 50 pF 30 100 ns
Power-on Reset delay TPOR REXT = 123 kΩ ±1% 90 100 110 ms
Watchdog Time TWD REXT = 123 kΩ ±1% 90 100 110 ms
Open Window Percentage OWP ±0.2 TWD
Closed Window Time TCW 0.8 TWD
TCW REXT = 123 kΩ ±1% 72 80 88 ms
Open Window Time TOW 0.4 TWD
TOW REXT = 123 kΩ ±1% 36 40 44 ms
Watchdog Reset Pulse TWDR TWD/40
TWDR REXT = 123 kΩ ±1% 2.5 ms
TCL Input Pulse Width TTCL 150 ns
Table 4
Timing Waveforms
Watchdog Timeout Period
Voltage Monitoring
TWD = TPOR
TCW – closed window TOW – open window
Watchdog
timer reset
Condition:
REXT = 123 kΩ
− OWP
− 20%
+ OWP
+ 20%
80 100 120 Fig. 3
t [ms]
TSEN TSEN
TSEN
TSEN
TPOR TPOR
RES
VIN
VREF
VHY Conditions:
VOUTPUT ≥ 3 V
No timeout
Fig. 4
5
A6150
Timer Reaction
Combined Voltage and Timer Reaction
Block Diagram
TCW+TOW
T
OW
V
IN
VREF
TCL
RES
EN
Condition:
V
OUTPUT
≥ 3 V
Fig. 6
- Watchdog timer reset
TCL
too early 3 correct TCL service
EN goes active low
123
T
POR
=T
WD
T
CW
Voltage
Regulator
Voltage
Reference
Voltage
Reference
INPUT
VIN
R
OUTPUT
Enable
Logic
Reset
Control
Timer
VREF Comparator
TCL Fig. 7
EN
RES
Current
Controlled
Oscillator
Open drain
output RES
Vers. A0
Vers. A1
Conditions: VIN > VREF after power-up sequence
TCW
TOW TCW TOW TCW
TTCL
TWDR
TCL
RES
EN
Fig.5
1 2 3
- Watchdog timer reset
TCW+TOW TCW+TOW TCW+TOW
3 correct TCL services Timeout
EN goes active low
6
A6150
Pin Description
Pin Name Function
1EN Vers. A0:
Open drain active low enable output.
EN must be pulled to VOUTPUT
even if unused
Vers. A1:
Push-pull active low reset output
2 RES Open drain active low reset output.
RES must be pulled up to VOUTPUT
even if unused
3 TCL Watchdog timer clear input signal
4V
SS GND terminal
5 INPUT Voltage regulator input
6 OUTPUT Voltage regulator output
7R R
EXT input for RC oscillator tuning
8V
IN Voltage comparator input
Table 5
Functional Description
Voltage Regulator
The A6150 has a 5 V ± 2%, 100 mA, low dropout volt-
age regulator. The low supply current (typ.155 µA) mak-
es the A6150 particularly suited to automotive systems
then remain energized 24 hours a day. The input voltage
range is 2.3 V to 26 V for operation and the input protec-
tion includes both reverse battery (20 V below ground)
and load dump (positive transients up to 60 V). There is
no reverse current flow from the OUTPUT to the INPUT
when the INPUT equals VSS. This feature is important for
systems which need to implement (with capacitance) a
minimum power supply hold-up time in the event of
power failure. To achieve good load regulation a 22 µF
capacitor (or greater ) is needed on the INPUT (see
Fig. 18). Tantalum or aluminium electrolytics are adequate
for the 22 µF capacitor; film types will work but are relati-
vely expensive. Many aluminium electrolytics have
electrolytes that freeze at about –30 °C, so tantalums are
recommended for operation below –25 °C. The impor-
tant parameters of the 22 µF capacitor are an effective series
resistance of ≤ 5 Ω and a resonant frequency above
500 kHz.
A 10 µF capacitor (or greater) and a 100 nF capacitor are
required on the OUTPUT to prevent oscillations due to
instability. The specification of the 10 µF capacitor is as
per the 22 µF capacitor on the INPUT (see previous
paragraph).
The A6150 will remain stable and in regulation with no
external load and the dropout voltage is typically con-
stant as the input voltage fall to below its minimum level
(see Table 2). These features are especially important in
CMOS RAM keep-alive applications.
Care must be taken not to exceed the maximum junction
temperature (+ 125 °C). The power dissipation within
the A 6150 is given by the formula:
PTOTAL = (VINPUT – VOUTPUT) * IOUTPUT + (VINPUT) * ISS
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
PMAX = ( 125 °C – TA) / Rth(j-a)
where Rth(j-a) is the termal resistance from the junction to
the ambient and is specified in Table 2. Note the Rth(j-a)
given in Table 2 assumes that the package is soldered
to a PCB. The above formula for maximum power dissi-
pation assumes a constant load (ie.≥100 s). The
transient thermal resistance for a single pulse is much
lower than the continuous value. For example the A6150
in DIP8 package will have an effective thermal resistance
from the junction to the ambient of about 10 °C/W for a
single 100 ms pulse.
VIN Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the VIN input. The VDD voltage at which reset is
asserted or released is determined by the external
voltage divider between VDD and VSS, as shown on Fig.
18. A part of VDD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at VIN must be taken into account as well
as the current consumption of the divider itself. Low
resistor values will need more current, but high resistor
values will make the reset threshold less accurate at
high temperature, due to a possible leakage current at
the VIN input. The sum of the two resistors should stay
below 300 kΩ. The formula is: VRESET = VREF *(1 + R1/R2).
Example: choosing R1 = 100 kΩ and R2 = 51 kΩ will
result in a VDD reset threshold of 4.5 V (typ.).
At power-up the reset output (RES) is held low (see
Fig. 4). After INPUT reaches 3.36 V (and so OUTPUT
reaches at least 3 V) and VIN becomes greater than VREF,
the RES output is held low for an additional power-on-
reset (POR) delay which is equal to the watchdog time
TWD (typically 100 ms with an external resistor of 123 kΩ
connected at R pin). The POR delay prevents repeated
toggling of RES even if VIN and the INPUT voltage drops
out and recovers. The POR delay allows the micropro-
cessor’s crystal oscillator time to start and stabilize and
ensures correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the power-
down reset whenever VIN falls below VREF. The sensiti-
vity or reaction time of the internal comparator to the vol-
tage level on VIN is typically 5 µs.
Timer Programming
The on-chip oscillator with an external resistor REXT con-
nected between the R pin and VSS (see Fig. 18) allows
the user to adjust the power-on reset (POR) delay,
watchdog time TWD and with this also the closed and
open time windows as well as the watchdog reset pulse
width (TWD/40).
With REXT = 123 kΩ typical values are:
-Power-on reset delay: TPOR is 100 ms
-Watchdog time: TWD is 100 ms
7
A6150
-Closed window: TCW is 80 ms
-Open window: TOW is 40 ms
-Watchdog reset: TWDR is 2.5 ms
Note the current consumption increases as the fre-
quency increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see Fig. 3) and
is defined by two parameters, TWD and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer
resets and is defined by TCW = TWD – OWP(TWD).
The open window starts after the closed time window
finishes and lasts till TWD + OWP(TWD).The open window
time is defined by TOW = 2 x OWP (TWD)
For example if TWD = 100 ms (actual value) and OWP =
± 20% this means the closed window lasts during first
the 80 ms (TCW = 80 ms = 100ms – 0.2 (100 ms)) and
the open window the next 40 ms (TOW = 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between
80 ms and 120 ms after the timer reset. However as the
time base is ± 10% accurate, software must use the
following calculation as the limits for servicing signal TCL
during the open window:
Related to curves (Fig. 10 to Fig. 20), especially Fig. 19
and Fig. 20, the relation between TWD and REXT could
easily be defined. Let us take an example describing the
variations due to production and temperature:
1.Choice, TWD = 26 ms.
2.Related to Fig. 20, the coefficient (TWD to REXT) is
1.155 where REXT is in kΩ and TWD in ms.
3.REXT (typ.) = 26 x 1.155 = 30.0 kΩ.
4. 26 ms at +25 °C
a) (26 − 10% = 23.4 ms) (26 + 10% = 28.6 ms) a)
b) (23.4 − 5% = 22.2 ms) (28.6 + 5% = 30.0 ms) b)
min.: (30.0 − 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between TWD = 26 ms and the (TCL period)
= 25.4 ms is 0.975.
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x TWD or
TCL period = , as typical value.
a) While PRODUCTION value unknown for the custo-
mer when REXT ≠ 123 kΩ.
b) While operating TEMPERATURE range
-40 °C ≤ TJ ≤ +85 °C.
5. If you fixed a TCL period = 26 ms
⇒ REXT = = 30.8 kΩ.
If during your production the TWD time can be mea-
sured at TJ = + 25 °C and the µC can adjust the TCL
period, then the TCL period range will be much larger
for the full operating temperature.
TWD versus VOUTPUT at TJ = +25 °C TWD versus R at TJ = +25 °C
1
0
’
000
1000
1
00
1
0
1
4
5
VOUTPUT [V] Fi
g
. 8
TWD [ms]
6
R
=
10 MΩ
R = 1 MΩ
R = 100 kΩ
R
=
10 kΩ
R = 1 kΩ
0.1 110 100 1000 10’000
1
10
100
1000
10’000
TWD [ms]
R[kΩ]Fig. 9
3 V
4.8 V
5 V
5.2 V
6 V
0.975 x REXT
1.1
55
26 x 1.155
0
.
9
7
5
8
A6150
TWD versus R at TJ = +25 °C
1
10
100
1000
TWD [ms]
0
.1 110 100 1000 10’000
R[kΩ]Fig. 10
3 V
4.8 V
5 V
5.2 V
6 V
10’000
9
A6150
TWD versus VOUTPUT at TJ = +85 °C TWD versus R at TJ = +85 °C
TWD versus VOUTPUT at TJ = -40 °C TWD versus R at TJ = -40 °C
Fig. 12
0.1 10 100 1000 10’000
1
10
100
1000
10’000
TWD [ms]
R[kΩ]
1
3 V
4.8 V
5 V
5.2 V
6 V
10’000
1000
100
10
1
3 4 5
VOUTPUT [V] Fig. 11
T
WD
[ms]
6
R = 10 MΩ
R = 1 MΩ
R = 100 kΩ
R = 10 kΩ
R = 1 kΩ
10’000
1000
100
10
1
34 5
VOUTPUT [V] Fig. 13
T
WD
[ms]
6
R = 10 MΩ
R = 1 MΩ
R = 100 kΩ
R = 10 kΩ
R = 1 kΩ
0.1
10 100 1000 10’000
1
10
100
1000
1
R[kΩ]
0.1
TWD [ms]
Fig. 14
3 V
4.8 V
5 V
5.2 V
6 V
10
A6150
TWD versus temperature at 5 V T WD versus R at 5 V
OUTPUT Current versus INPUT Voltage
10’000
1000
100
10
1
-40 0+40
TJ [°C] Fig. 15
T
WD
[ms]
+80
R = 10 MΩ
-20 +20 +60
R = 1 MΩ
R = 100 kΩ
R = 10 kΩ
R = 1 kΩ
0.1 10 100 1000 10’000
1
10
100
1000
10’000
TWD [ms]
R[kΩ]Fig. 16
1
-40 °C
-20 °C
+25 °C
+70 °C
+85 °C
0
5
10
15
20
25
30
INPUT voltage [V]
Fig.17
20
0
40
60
80
1
00
OUTPUT current[mA]
TA=+50 °C
TA=+85 °C
TA=+25 °C
SO8 package
soldered to PC board
TJmax = + 125 °C
11
A6150
Timer Clearing and RES Action
The watchdog circuit monitore the activity of the proces-
sor. If the user’s software does not send a pulse to the
TCL input within the programmed open window timeout
period a short watchdog RES pulse is generated which
is equal to TWD /40 = 2.5 ms typically (see Fig. 5).
With the open window constraint new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If software is stuck in a loop which includes the routine
to clear the watchdog then a conventional watchdog
would not make a system reset even though software is
malfunctioning; the A6150 would make a system reset
because the watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (TCW + TOW + TWDR). The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up se-
quence. The system enable output, EN , can be used to
prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable-EN Output”).
The RES output must be pulled up to VOUTPUT even if the
output is not used by the system (see Fig 18).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrat-
ed by the sequence of events shown in Fig. 6. On pow-
er-up, when the voltage at VIN reaches VREF, the power-
on-reset, POR, delay is initialized and holds RES active
for the time of the POR delay. A TCL pulse will have no
effect until this power-on-reset delay is completed. When
the risk exists that TCL temporarily floats, e.g. during
TPOR, a pull-up to VDD is required on that pin. After the
POR delay has elapsed, RES goes inactive and the
watchdog timer starts acting. If no TCL pulse occurs,
RES goes active low for a short time TWDR after each
closed and open window period. A TCL pulse coming
during the open window clears the watchdog timer.
When the TCL pulse occurs too early (during the closed
window), RES goes active and a new timeout sequence
starts. A voltage drop below the VREF level for longer than
typically 5µs overrides the timer and immediately forces
RES active and EN inactive. Any further TCL pulse
has no effect until the next power-up sequence has
completed.
Enable - EN Output
The system enable output, EN ,is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (ie. the TCL pulse must come in the open win-
dow). After three consecutive services of the watchdog
with TCL during the open window, the EN goes active
low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes inac-
tive (time allowed for the system to restart) and in this
way the electrical motors driven by the system could
function out of control. The A6150 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (ie. the system has correctly re-
started after a reset condition).
For the version A0 the EN output must be pulled up to
VOUTPUT even if the output is not used by the system (see
Fig. 18.
Typical Application
INPUT OUTPUT
A6150
R
VSS
22 µF
+
+
Regulated voltage
Fig.18
Unregulated voltage
GND
100 kΩ
100 nF
10
µ
FR1
R2
Address
decoder
Microprocessor
RES
M
o
t
or
EN
controls
VIN
TCL
RE
S
EN
Version A0:
Version A1:
12
A6150
TWD Coefficient versus REXT at TJ = + 25 °C
REXT Coefficient versus TWD at TJ = + 25 °C
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
TWD Coefficient
10 1000
100
R
EXT
[
kΩ
]
Fig. 19
Fig. 20
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
REXT Coefficient
10 100 1000
TWD [ms]
13
A6150
Package Information
Dimensions of 8-Pin SOIC Package
Min Nom Max
A 1.35 1.63 1.75
A1 0.10 0.15 0.25
B 0.33 0.41 0.51
C 0.19 0.20 0.25
D 4.80 4.93 5.00
E 3.80 3.94 4.00
e 1.27
H 5.80 5.99 6.20
L 0.40 0.64 1.27
2
3
4
5 6 7 8
H
L
0 - 8°
C
E
A
1
A
B
e
D
Dimensions in mm
Fig. 21
Dimensions of 8-Pin Plastic DIP Package
A
1
A
2
A
L
e
b2 eB
eA
C
b3
b
E
Dimensions in mm
1
2
3
4
5 6 7 8
Min. Nom. Max. Min. Nom. Max.
A 5.33 D 9.01 9.27 10.16
A1 0.38 E 7.62 7.87 8.25
A2 2.92 3.30 4.95 E1 6.09 6.35 7.11
b 0.35 0.45 0.56 e 2.54
b2 1.14 1.52 1.78 eA 7.62
b3 0.76 0.99 1.14 eB 10.92
C 0.20 0.25 0.35 L 2.92 3.30 3.81
E1
Fig.22
14
A6150
Ordering Information
When ordering, please specify complete Part Number
Part Number Output EN Temperature Range Package Delivery Form Package Marking
(first line)
A6150A1SO8A 8-pin SOIC Stick 6150A1
A6150A1SO8B Push-pull 8-pin SOIC Tape & Reel 6150A1
A6150A1DL8A* -40 °C to +85 °C 8-pin plastic DIP Stick A6150A1
A6150A0SO8A* 8-pin SOIC Stick 6150A0
A6150A0SO8B* Open drain 8-pin SOIC Tape & Reel 6150A0
A6150A0DL8A* 8-pin plastic DIP Stick A6150A0
A6150A1XSO8A* 8-pin SOIC Stick 6150A1X
A6150A1XSO8B* Push-pull 8-pin SOIC Tape & Reel 6150A1X
A6150A1XDL8A* -40 °C to +125 °C 8-pin plastic DIP Stick A61501X
A6150A0XSO8A* 8-pin SOIC Stick 6150A0X
A6150A0XSO8B* Open drain 8-pin SOIC Tape & Reel 6150A0X
A6150A0XDL8A* 8-pin plastic DIP Stick A61500X
* = non stock item. Might be available on request and upon minimum order quantity (please contact EM Microelectronic).
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely
embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the
circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given
has not been superseded by a more up-to-date version.
© 2002 EM Microelectronic-Marin SA
,
03/02
,
Rev. N/344
EM Microelectronic-Marin SA
,
CH - 2074 Marin
,
Switzerland
,
Tel. +41 –
(
0
)
32 75 55 111
,
Fax +41 –
(
0
)
32 75 55 403