ACX302AK
8.80cm (3.5 Type) NTSC/PAL Color LCD Panel
Description
The ACX302AK is a 8.80cm diagonal active matrix
TFT-LCD panel addressed by low temperature
polycrystalline silicon transistors with built-in
peripheral driving circuitry. This panel provides full-
color representation for NTSC and PAL systems. In
addition, RGB dots are arranged in a delta pattern
that provides smooth picture quality without fixed
color patterns compared to vertical stripe and mosaic
patterns.
Features
•Number of active dots: 200,000, 8.80cm (3.5 Type) in diagonal
•Horizontal resolution: 440 TV lines
•Optical transmittance: 8.2% (typ.)
•High contrast ratio with normally white mode: 200 (typ.)
•Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
•Low voltage, low power consumption 12V drive: 60mW (typ.)
•Smooth pictures with a RGB delta arrangement
•Supports NTSC/PAL
•Built-in picture quality improvement circuit
•Up/down and/or right/left inverse display function
•16:9 screen display function
•AR (anti-reflectance) surface treatment provides an easy-to-see display even outdoors
•Dirt-resistant surface treatment
•Narrow frame
•High color reproductivity
Element Structure
•Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
•Number of pixels
Total number of dots : 884 (H) ×230 (V) = 203,320
Number of active dots : 880 (H) ×228 (V) = 200,640
•Panel dimensions
Package dimensions : 78.8 (W) ×63.3 (D) ×2.2 (H) (mm)
Effective display dimensions : 70.400 (H) ×52.725 (V) (mm)
Applications
LCD monitors, etc.
– 1 – E99419A9Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
For the availability of this product, please contact the sales office.
– 2 –
ACX302AK
Block Diagram
The panel block diagram is shown below.
LCCS
TESTL
TESTR
COM
VST
VCK
EN
DWN
VV
DD
V
SS
HV
DD
VSSG
TEST2
WIDE
HST
REF
TEST1
Cext/Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
COM
2345678910 11 12 13 14 15 16 18 19 20 21 22 23
124
17
V Shift Register
V Shift Register
V Level Shifter
Negative Voltage
Generation Circuit
Common
Voltage
H Level Shifter & Shift Register
– 3 –
ACX302AK
Absolute Maximum Ratings (Vss = 0V)
•H driver supply voltage HVDD, Cext/Rext –1.0 to +17 V
•V driver supply voltage VVDD –1.0 to +15 V
•V driver negative supply voltage VSSG –3.0 to +1.0 V
•Common voltage of panel COM –1.0 to +17 V
•H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE –1.0 to +17 V
•V driver input pin voltage VST, VCK, EN, DWN, REF –1.0 to +15 V
•Video signal, uniformity improvement signal input pin voltage
GREEN, RED, BLUE, PSIG –1.0 to +13 V
•Operating temperature Topr –10 to +60 °C
•Storage temperature Tstg –30 to +85 °C
Operating Conditions
1. Input/output supply voltage conditions∗1(Vss = 0V)
Item
Supply voltage
HVDD
VVDD
Cext/Rext∗2
VSSG
11.4
11.4
HVDD – 2.0
–2.3
12.0/13.5
12.0/13.5
12.0/13.5
–1.8
14.0
14.0
—
–1.5
V
V
V
V
VSSG output voltage setting∗3
Symbol Min. Typ. Max. Unit
∗1The HVDD/VVDD typical voltage setting is noted as 12.0V in these specifications.
∗2Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
∗3For the VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode
as shown in the figure below.
HVDD – Cext/Rext
Cext/Rext
HVDD
HVDD
7
Voltage
Time
text
Set a Cext value that satisfies
text > 1ms.
The Cext/Rext value differs
according to the rising time
of the panel supply voltage.
Rext
ACX302AK
HVDD VSSG
VSS
Cext/Rext 1µF Use a Zener
voltage of 2.7V.
(RD2.7UM is
recommended.)
Cext
– 4 –
ACX302AK
∗4Input video and uniformity improvement signals should be symmetrical to VVC. The input conditions for the
uniformity improvement signal Vpsig differ for 4:3 display and 16:9 display.
1) During 4:3 display, input the voltage amplitude symmetrical to VVC as shown in Fig. 1.
2) During 16:9 display, input the same signal amplitude as in 1) above during the effective display portion,
and input the black signal level VpsigBK during the top/bottom black input portion as shown in Fig. 2.
Item
H/V driver input voltage (Low)
(High)
VIL
VIH
VREF
VVC
Vsig
Vpsig
VpsigBK
Vcom
–0.3
2.6
VIH/2 – 0.3
5.3
1.0
VVC ± 2.3
VVC – 0.4
0.0
3.0
VIH/2
5.5
VVC ± 4.0
VVC ± 2.5
VVC ± 4.0
VVC – 0.3
0.3
5.5
VIH/2 + 0.3
5.7
VVDD – 2.0
(however, 10V or less)
VVC ± 2.7
VVC ± 4.5
VVC – 0.2
V
V
V
V
V
V
V
V
REF input voltage
Video signal center voltage
Video signal input range
Uniformity improvement signal
16:9 display top/bottom black signal∗4
Common voltage of panel (Ta = 25°C)
Symbol Min. Typ. Max. Unit
2. Input signal voltage conditions (Vss = 0V)
During 4:3 display
PSIG
VVC Vpsig
During 16:9 display
PSIG
VVC Vpsig VpsigBK
VVC ± 4.0V
VVC ± 2.5V
Top/bottom black display portion
(letterbox portion)
Effective display portion
Fig. 1
Fig. 2
– 5 –
ACX302AK
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
TESTL
COM
VST
VCK
EN
DWN
VVDD
VSS
HVDD
VSSG
TEST2
WIDE
13
14
15
16
17
18
19
20
21
22
23
24
HST
REF
TEST1
Cext/
Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Start pulse input for H shift register
drive
Level shifter circuit REF voltage
input
Panel test output; no connection
Time constant power supply input
for H shift register drive
Clock input for H shift register drive
Clock input for H shift register drive
Uniformity improvement signal input
Video signal (G) input to panel
Video signal (R) input to panel
Video signal (B) input to panel
H shift register drive direction signal
input
Panel test output; no connection
Symbol Description Pin
No. Symbol Description
Panel test output; no connection
Common voltage input of panel
Start pulse input for V shift register
drive
Clock input for V shift register drive
Gate selection pulse enable input
V shift register drive direction signal
input
Power supply input for V driver
H and V driver GND
Power supply input for H driver
Negative power supply setting for
V driver
Test; no connection
Pulse input for 16:9 mode
Pin Description
– 6 –
ACX302AK
Input Equivalent Circuits
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to Vss with a
high resistance of 1MΩ(typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
HVDD
1MΩ
Input
Signal line
(2) HCK1, HCK2
1MΩ
1MΩ
HVDD HVDD
HCK1
HCK2
H level shifter and
shift register circuit
(3) HST, WIDE, REF
1MΩ
350Ω
1MΩ
350Ω
HVDD HVDD
Input
REF
Level conversion
circuit
(4) RGT, REF
1MΩ
2kΩ
1MΩ
2kΩ
HVDD HVDD
Input
REF
Level conversion
circuit
(5) VST, VCK, EN, REF
1MΩ
800Ω
1MΩ
800Ω
VVDD
VVDD
Input
REF
Level conversion
circuit
– 7 –
ACX302AK
(10) TEST1/TEST2
HVDD
TEST1 350Ω
1MΩ
350ΩTEST2
1MΩ
(11) TESTL, TESTR
TESTL
TESTR
(6) DWN, REF
1MΩ
1MΩ
VVDD VVDD
Input
REF
Level conversion
circuit
2kΩ2kΩ
(7) VSSG
HVDD
VSSG Negative voltage
generation circuit
(8) COM
1MΩ
Input
LC
(9) Cext/Rext
HVDD
Cext/Rext H driver
1MΩ
– 8 –
ACX302AK
Clock Timing Conditions (VIH = 3.0V, HVDD = VVDD = 12V, Ta = 25°C)
HST rise time
HST fall time
HST data setup time
HST data hold time
HCKn rise time
HCKn fall time
HCK1∗5fall to HCK2 rise time
HCK1∗5rise to HCK2 fall time
VST rise time
VST fall time
VST data setup time
VST data hold time
VCK rise time
VCK fall time
EN rise time
EN fall time
EN rise to VCK rise/fall time
EN pulse width
WIDE rise time
WIDE fall time
WIDE (H) rise to VCK rise/fall time
WIDE (H) pulse width
WIDE (V) pulse width
WIDE (V) fall to EN rise time
EN fall to WIDE (V) fall time
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
trEn
tfEn
tdEn
twEn
trWide
tfWide
tdhWide
twhWide
twvWide
tov1Wide
tov2Wide
—
—
137
–30
—
—
–15
–15
—
—
30
–34
—
—
—
—
2400
5400
—
—
0.9
2.8
1928
25
25
—
—
167
0
—
—
0
0
—
—
32
–32
—
—
—
—
2500
5500
—
—
1.1
3.0
1933
32
32
30
30
197
30
30
30
15
15
100
100
34
–30
100
100
100
100
2600
5600
100
100
1.3
3.3
1938
—
—
ns
µs
µs
ns
Item Symbol Min. Typ. Max. Unit
HST
HCK
VST
VCK
EN
WIDE
∗5HCKn means HCK1 and HCK2. (fHCKn = 3.0MHz)
– 9 –
ACX302AK
Horizontal Standard Timing
FRP
VCK
EN
WIDE∗6
HCK2
HCK1
HST 5.0µs
1.3µs
2.5µs 3µs
1.9µs1.1µs
∗6WIDE represents every 1H pulse indicated on the horizontal timing.
– 10 –
ACX302AK
∗7Definitions:
The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.
<Horizontal Shift Register Driving Waveforms>
HST rise time
HST
HCK
HST fall time
HST data setup time
HST data hold time
HCKn∗5rise time
HCKn∗5fall time
HCK1 fall to HCK2 rise
time
HCK1 rise to HCK2 fall
time
•HCKn∗5duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
•HCKn∗5duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
•HCKn∗5duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 167ns
thHst = 0ns
•tdHst = 167ns
thHst = 0ns
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
Item Symbol Waveform Conditions
90% 90%
10% 10%
HST
trHst tfHst
∗7
50% 50%
50%
tdHst thHst
HST
HCK1 50%
∗5
HCKn
90% 90%
10%10%
trHckn tfHckn
∗750% 50%
50%50%
HCK1
HCK2
to2Hck to1Hck
WIDE
WIDE rise time
WIDE fall to VCK rise/fall
time
trWide
WIDE fall time
WIDE pulse width
tfWide
tdhWide
twhWide
WIDE
90% 90%
10% 10%
trWide tfWide
∗6
– 11 –
ACX302AK
Vertical Standard Timing
FRP
EN
WIDE
HST
VCK
VST
FRP
EN
WIDE
HST
VCK
VST
NTSC WIDE (in case of EVEN field)
NTSC 4:3 (in case of EVEN field)
∗8
∗8WIDE represents 1F period indicated on the vertical timing.
– 12 –
ACX302AK
EN rise time
EN
WIDE
EN fall time
EN fall to VCK rise/fall
time
EN pulse width
WIDE rise time
WIDE pulse width
trEn
tfEn
tdEn
twEn
trWide
WIDE fall time tfWide
twvWide
WIDE fall to EN fall time tov1Wide
EN rise to WIDE fall time tov2Wide
90%
tfEn
10%
EN
90%
10%
trEn
∗7
VCK 50%
EN 50% 50%
tdEn twEn
WIDE
90% 90%
10% 10%
trWide tfWide
50%
∗7
WIDE
50%50%
EN
to2Wide to1Wide
trWide
•VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
<Vertical Shift Register Driving Waveforms>
VST rise time
VST
VCK
VST fall time
VST data setup time
VST data hold time
VCK rise time
trVst
tfVst
tdVst
thVst
trVck
VCK fall time tfVck
Item Symbol Waveform Conditions
90%90%
VST
trVst tfVst
10%10%
∗7
50%
50%
VST 50% 50%
VCK
tdVst thVst
VCK
90% 90%
10%10%
trVck tfVck
•VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
•VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
•VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
∗8
– 13 –
ACX302AK
Electrical Characteristics (Ta = 25°C, HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V)
1. Horizontal drivers
Item
HCKn input pin capacitance
HST input pin capacitance
Video signal input pin capacitance
Psig input pin capacitance (4:3 display)
Psig input pin capacitance (16:9 display)
Input pin current HCK1
HCK2
HST
RGT
REF
CHckn
CHst
Csig
Cpsig
Cpsig
I Hck1
I Hck2
I Hst
I RGT
I REF
I H25
I H60
HCK1: actual driving
HCK2: actual driving
HST = GND
RGT = GND
REF = VIH/2
—
—
—
—
—
–900
–900
–300
–150
–1200
—
—
80
30
270
16
45
–300
–300
–100
–50
–300
4.0
—
95
45
310
20
50
—
—
—
—
—
4.75
6.00
pF
pF
pF
nF
nF
µA
µA
µA
µA
µA
mA
mA
Symbol Min. Typ. Max. Unit Conditions
2. Vertical drivers
Item
VCK input pin capacitance
VST input pin capacitance
Input pin current VCK
VST
EN
DWN
WIDE
CVck
CVst
I Vck
I Vst
I En
I DWN
I WIDE
I V25
I V60
—
—
–150
–150
–150
–150
–150
—
—
10
10
–50
–50
–50
–50
–50
1.0
—
15
15
—
—
—
—
—
1.5
2.0
pF
pF
µA
µA
µA
µA
µA
mA
mA
Symbol Min. Typ. Max. Unit Conditions
3. Total power consumption of the panel
Item
Total power consumption
of the panel (NTSC) PWR25
PWR60
—
—
60
—
75
96
mW
mW
Symbol Min. Typ. Max. Unit
4. Pin input resistance
Item
Pin – VSS input resistance Rin 0.5 1—MΩ
Symbol Min. Typ. Max. Unit
VCK = GND
VST = GND
EN = GND
DWN = GND
WIDE = GND
HCKn: HCK1, HCK2 (3.0MHz)
(Ta = 25°C)
(Ta = 60°C)
Current consumption
(Ta = 25°C)
(Ta = 60°C)
Current consumption
(Ta = 25°C)
(Ta = 60°C)
– 14 –
ACX302AK
Electro-optical Characteristics (Ta = 25°C, NTSC mode)
Item
25°C
60°C
X
Y
X
Y
X
Y
25°C
60°C
25°C
60°C
25°C
60°C
R – G
B – G
0°C
25°C
0°C
25°C
60°C
1 min.
CR ≥10
θ= 0°
25°C
R
G
B
V90
V50
V10
ON time
OFF time
CR25
CR60
T
Rx
Ry
Gx
Gy
Bx
By
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
V50RG
V50BG
ton0
ton25
toff0
toff25
F
YT1
θT
θB
θL
θR
Rf
CTK
1
2
3
4
5
6
7
8
9
10
11
100
100
7.7
0.595
0.310
0.245
0.580
0.120
0.090
1.30
1.30
1.70
1.70
2.20
2.20
–0.050
0.000
—
—
—
—
—
—
35
50
45
45
—
—
200
200
8.2
0.625
0.340
0.275
0.610
0.150
0.120
1.50
1.50
1.90
1.90
2.40
2.40
–0.080
0.030
40
15
140
50
–60
—
45
60
55
55
0.9
—
—
—
0.655
0.370
0.305
0.640
0.180
0.150
1.70
1.70
2.10
2.10
2.60
2.60
–0.110
0.050
55
25
180
75
–30
10
—
1.5
1.5
—
%
CIE
standards
V
V
ms
dB
s
Degree
(°)
%
%
Contrast ratio
Optical transmittance
Chromaticity
V-T
characteristics
Half tone color reproduction
range
Response time
Flicker
Image retention time
Viewing angle range
Surface reflection ratio
Cross talk
Symbol
Measurement
method
Min. Typ. Max. Unit
– 15 –
ACX302AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V
VVC = 5.5V, VCOM = 5.2V, Vpsig = 5.5 ± 2.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Three types of measurement systems are used as shown below.
(5) R, G and B input signal voltage Vsig
Vsig = 5.5 ± VAC [V] (VAC: signal amplitude)
∗ Measurement system I
∗ Measurement system II
Backlight
3.5mm
LCD panel
Luminance
Meter Measurement
Equipment
Optical fiber
Light Detector
Light receptor lens
LCD panel
∗ Measurement system III
Drive Circuit
Light
Source
Optical fiber
Light
Source
Spectroscope
Surface A∗
Surface A∗
Surface A∗
∗ Surface A: See the Package Outline.
Measurement
Equipment
1. Contrast Ratio
Contrast ratio (CR) is given by the following formula.
CR = L (White)/L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.0V.
Both luminosities are measured by System I.
– 16 –
ACX302AK
2. Optical Transmittance
Optical transmittance (T) is given by the following formula.
T = L (White)/Luminance of Backlight ×100 [%]
L (White) is the same expression as defined in the "Contrast Ratio" section.
Optical transmittance is measured by System I.
3. Chromaticity
Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System Iuses x and y of
the CIE standards as the chromaticity here.
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
90
50
10
V10V50V90
VAC – Signal amplitude [V]
Transmittance [%]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of LCD panels
is characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B, respectively. V50RG and V50BG,
that is to say the differences between V50R and V50G
and between V50B and V50G, are given by the following
formulas respectively.
V50RG = V50R – V50G
V50BG = V50B – V50G
Transmittance [%]
0V50R
VAC – Signal amplitude [V]
50
100
V50B
V50G
V50RG
V50BG
G raster
B raster
R raster
R input G input B input
Raster
R
G
B
0.5
4.0
4.0
4.0
0.5
4.0
4.0
4.0
0.5
W 0.0 0.0 0.0
Signal amplitudes (VAC) supplied to each input
(Unit: V)
– 17 –
ACX302AK
6. Response Time
Response times ton and toff are measured
by System II by applying the input signal
voltages in the figure to the right to each
input pin. These times are defined by the
following formulas.
ton = t1 – tON
toff = t2 – tOFF
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
The relationships between t1, t2, tON and
tOFF are shown in the figure to the right.
4.0V
5.5V
0V
0.5V
Optical transmittance output
waveform 100%
90%
10%
0%
tON t1 tOFF t2
ton toff
Input signal voltage (Waveform applied to measured pixels)
7. Flicker
Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms)
of the panel output signal for gray raster* mode are measured by a DC voltmeter and a spectrum analyzer
in System II.
F (dB) = 20 log {AC component/DC component}
∗R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 ± V50 (V)
where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply the monoscope pattern∗to the LCD panel for 1 minute and then change to a gray scale signal
(Vsig = 5.5 ± VAC (V); VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time for the residual image to disappear.
∗Monoscope pattern input conditions
Vsig = 5.5 ± 4.0 or 5.5 ± 2.0 [V]
(shown in the figure to the right)
Vcom = 5.20V
5.5V
0V
4.0V 2.0V
4.0V
2.0V
Black level
White level
Vsig waveform
– 18 –
ACX302AK
12. Measurement Backlight Specifications
Optical characteristics
Item
Average luminance of effective
illuminating surface
Color temperature (reference value)
Chromaticity coordinates
Standard
2,700 ± 300
8,800
x: 0.285 ± 0.01
y: 0.303 ± 0.01
Unit
cd/m2
K
Remarks
Ta = 25 ± 2°C,
at dimmer = max.
Ta = 25 ± 2°C,
at dimmer = max.
11. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi
(i = 1 to 4) around the black window (Vsig = 4.0V/1V).
W2
W2' W4
W4'
W1 W1'
W3 W3'
9. Definition of Viewing Angle Range
Viewing angle range is measured by System I.
The contrast ratio (CR) is measured at the
angles defined in the figure to the right and the
range where CR ≥10 is taken as the viewing
angle range.
Measure with surface A∗facing upwards.
∗Surface A: See the Package Outline.
θT
θR
θB
θL
Normal (θ = 0°)
Right
Left
Bottom
Top
Surface A
10. Surface Reflection Ratio
Surface reflection ratio (Rf) is given by the following formula.
Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) ×100 [%]
The incident and reflected angles of light are both 0°.
Both luminosities are measured by System III.
∗Surface A: See the Package Outline.
Cross talk value CTK = ×100 [%]
Wi
Wi' – Wi
– 19 –
ACX302AK
R G B
1228
230
1
G
G
G
Gate SW Gate SW Gate SWGate SWGate SWGate SW
R G B R G B R G B R G B R G B
B G B R G B R B R G B R G B R
R G B R G B R G B R G B R G B
B G B R G B R G B R G B R
R G B R G B R G B R G B R G B
B G B R G B R B R G B R G B R
R G B R G B R G B R G B R G B
B G B R G B R B R G B R G B R
G
G
G
G
Active area
884
2
2880
R
R
R
R
R
R
R
R
Description of Operation
1. Color Coding
The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the
display.
– 20 –
ACX302AK
2. Description of LCD Panel Operations
•A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 228 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
•The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display and
16:9 mode pulse elimination display are possible by using the enable pin and simultaneously controlling VCK.
•A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 880 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
•The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
•The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 228 ×880 pixels to
display a picture in a single vertical scanning period.
•Pixel dots are arranged in a delta arrangement, where sets of RGB pixels are positioned shifted by 1.5 dots
against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each
horizontal line against the horizontal sync signal to apply a video signal to each pixel properly.
•The video signal should be input with the polarity-inverted every horizontal cycle.
•The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
BLK
HST
HCK1
HCK2
1 2 3 293
294
295
Horizontal display period (48.9µs)
VD
VST
VCK 1 2
Vertical display period 228H (14.5ms)
227 228
VD
VST
VCK 1 2
Vertical display period 228H (14.5ms)
227 228
(3) Horizontal display period (RGT: high level)
(2) Vertical display period (DWN: low level)
– 21 –
ACX302AK
3. RGB Simultaneous Sampling
The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching
between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching
by an external signal delay circuit is needed before applying the video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuits. These two block
diagrams are as follows.
The ACX302AK has a right/left inversion function. The following phase relationship diagram indicates the
phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be
inverted for the B and G signals.
(1) Sample-and-hold (right scan)
20
21
AC Amp
AC Amp
AC Amp
S/H
S/H
S/H
S/H
S/H
CKB CKG
CKG
CKG
CKR
B
R
G
BLUE
RED
GREEN
ACX302AK
22
HCKn
CKB
CKR
CKG
AC Amp
AC Amp
AC Amp
Delay
Delay
Delay
B
R
G
BLUE
RED
GREEN
20
21
ACX302AK
22
<Phase relationships of delaying sample-and-hold pulses> (right scan)
(2) Delay element (right scan)
– 22 –
ACX302AK
System Configuration
+12.0V +3.0V +12.0V
PSIG
GREEN
BLUE
COM/CS
HCK2
VCK
RED
HCK1
HST
VST
EN
RGT
REF
WIDE
CXA3268AR
Y/color difference
R/G/B
Serial data
Control Circuit
LCD Panel
ACX302AK
DWN
Cext/Rext
VSSG
1µF
Use a Zener
voltage of 2.7V.
(RD2.7UM is
recommended.)
10kΩ
∗ See page 3 for
the value setting.
Cext∗
– 23 –
ACX302AK
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install grounded conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
c) Use ionized air to blow dust off the panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at high temperatures or high humidity, as this may result in panel damage.
Package Outline Unit: mm
– 24 –
ACX302AK
1FPC
2Reinforcing board
3Polarizer
4Shield case(Front)
5Shield case(Rear)
6Double coated adhesive tape
Note1. Tolerance with no indicate(±0.2)
2. SONY logotype
3. Label is stuck hear
0.35 ±0.03
0.5(0.5) P : 0.5±0.02×23=11.5±0.03
Pin1Pin24
Electrode Enlarged(Back)
54.4
±0.5
(Polarizer)
Note 2
Center
(reference)
1
2
38.9
28.35
(3.87) (28.35)
52.725(Active area)
56.7(Window)
31.08
(32.22)
12.8±0.5
78.8
63.3
2.73
37.15 (37.15)
(39.9)
73±0.5 (Polarizer)
74.3(Window)
70.4(Active area)
12.5±0.05
(28.3)
2.2
73.1(Window)
36.55(36.55)
1.75
55.5(Window)
(4.47) 3.33
Front view Rear view
3
5
6
3
6
Note 3
28.35
55.4
(Polarizer)
±0.5
(2.75) (3.35) 2.35
4
72±0.5 (Polarizer)
32
Center
(Reference)
30
±0.5
0.3±0.05
Mass: Approximately 25g
Thickness of the connector