ProASIC3 Flash Family FPGAs
Advanced v0.5 2-29
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values,
respectively. They are 12-bit signals. For more
information on these signals, refer to the "FIFO Flag
Usage Considerations" section.
ESTOP and FSTOP Usage
The ESTOP pin is used to stop the read counter from
counting any further once the FIFO is empty (i.e., the
EMPTY flag goes high). Likewise, the FSTOP pin is used to
stop the write counter from counting any further once
the FIFO is full (i.e., the Full flag goes high).
The FIFO counters in the ProASIC3 device start the count
at 0, reach the maximum depth for the configuration
(e.g., 511 for a 512x9 configuration), and then restart at
0. An example application for the ESTOP, where the read
counter keeps counting, would be writing to the FIFO
once and reading the same content over and over
without doing another write.
FIFO Flag Usage Considerations
The AEVAL and AFVAL pins are used to specify the 12-bit
AEMPTY and AFULL threshold values, respectively. The
FIFO contains separate 12-bit write address (WADDR)
and read address (RADDR) counters. WADDR is
incremented every time a write operation is performed,
and RADDR is incremented every time a read operation is
performed. Whenever the difference between WADDR
and RADDR is greater than or equal to AFVAL, the AFULL
output is asserted. Likewise, whenever the difference
between WADDR and RADDR is less than or equal to
AEVAL, the AEMPTY output is asserted. To handle
different read and write aspect ratios, AFVAL and AEVAL
are expressed in terms of total data bits instead of total
data words. When users specify AFVAL and AEVAL in
terms of read or write words, the ACTgen tool translates
them into bit addresses and configures these signals
automatically. ACTgen configures the AFULL flag, AFULL,
to assert when the write address exceeds the read
address by at least a predefined value. In a 2kx8 FIFO, for
example, a value of 1,500 for AFVAL means that the
AFULL flag will be asserted after a write when the
difference between the write address and the read
address reaches 1,500 (there have been at least 1,500
more writes than reads). It will stay asserted until the
difference between the write and read addresses drops
below 1,500.
The AEMPTY flag is asserted when the difference
between the write address and the read address is less
than a predefined value. In the example above, a value
of 200 for AEVAL means that the AEMPTY flag will be
asserted when a read causes the difference between the
write address and the read address to drop to 200. It will
stay asserted until that difference rises above 200. Note
that the FIFO can be configured with different read and
write widths; In this case the AFVAL setting is based on
the number of write data entries and the AEVAL setting
is based on the number of read data entries. For aspect
ratios of 512x9 and 256x18, only 4,096 bits can be
addressed by the 12 bits of AFVAL and AEVAL, the
number of words must be multiplied by 8 and 16, instead
of 9 and 18. The ACTgen tool automatically uses the
proper values. To avoid half-words being written or read,
which could happen if different read and write aspect
ratios are specified, the FIFO will assert Full or Empty as
soon as at least a minimum of one word cannot be
written or read. For example, if a two-bit word is written
and a four-bit word is being read, FIFO will remain in the
Empty state when the first word is written. This occurs
even if the FIFO is not completely empty, because in this
case a complete word cannot be read. The same is
applicable in the Full state. If a four-bit word is written
and a two-bit word is read, the FIFO is full and one word
is read. The FULL flag will remain asserted because a
complete word cannot be written at this point.
Refer to the ProASIC3/E SRAM/FIFO Blocks application
note for more information.
Advanced I/Os
Introduction
ProASIC3 devices feature a flexible I/O structure,
supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,
and 3.3 V) through a bank-selectable voltage. Table 2-11
on page 2-30, Table 2-12 on page 2-30, and Table 2-18 on
page 2-44 show the voltages and the compatible I/O
standards. I/Os provide programmable slew rates (except
A3P030), drive strengths, weak pull-up, and weak pull-
down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V tolerant.
See the "5 V Input Tolerance" section on page 2-37 for
possible implementations of 5 V tolerance.
All I/Os are in a known state during power-up and any
power-up sequence is allowed without current impact.
Refer to the for more information.
I/O Tile
The ProASIC3 I/O tile provides a flexible, programmable
structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O
tile in selected I/O banks can be used to support high-
performance register inputs and outputs, with register
enable if desired (Figure 2-23 on page 2-32). The
registers can also be used to support the JESD-79C
Double Data Rate (DDR) standard within the I/O
structure (see the "Double Data Rate (DDR) Support"
section on page 2-33 for more information).
As depicted in Figure 2-23 on page 2-32, all I/O registers
share one CLR port. The output register and output
enable register share one CLK port. Refer to the "I/O
Registers" section on page 2-32 for more information.