Intel® 82430FX PCIset Level II
Cache Module
CYM74C430
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 1995
1CYM74C4 30
Features
•Pin-compatible secondary cache module family that ad-
heres to the Intel® CO AS T 1.2 specification
•Asynchronous (CYM74C430) configuration with pres-
ence and configurat ion detect pins
•Ideal for Intel P54C-based systems with the 82430FX
(Triton™) chipset
•Operates at 50, 60, and 66 MHz
•Uses cost-eff e ctive CMOS asynchronous SRAMs.
•160-position Burndy DIMM CELP2X80SC3Z48 connec-
tor
•3.3V compatible inputs/data outputs
Functional Description
This secondary cache module is designed for Intel P54C sys-
tems with the 82430FX (Triton) chip set. CYM74C430 is an
asynchronous 256-Kbyte cache module that provides a low-cost,
high-performance solution using 5V SRAMs with outputs clamped
to 3.3V.
The CYM 74C43 0 is organ ized a s 32K by 64 data wi th an 8K x8 tag
t hat s uppo r ts 3- 2-2-2 re a d s a nd 4 -2 - 2 - 2 wr i t es at 6 6 MHz. Multiple
ground pins and on-board decoupling capacitors ensure high
performance with maximum noise immunity.
All compone nts on the cache module are surface mounted on
a multi-layer epoxy laminate (FR-4) substrate. All inputs and
data outputs are (3.3V) TTL compatible. The contact pins of
the module are plated with 150 micro-inches of nicke l covered
by 30 micro-inches of gold.
Intel is a registered trademark of Intel Corporation. Triton is a trademark of Intel Corporation.
LogicBlockDiagram-CYM74C430
LA[17:5]
CWE0CWE1CWE2CWE3
AAA
DDD
D
CE
OE CE
OE CE
OE CE
OE
CWE4CWE5CWE6CWE7
AAAA
DDDD
CE
OE CE
OE CE
OE CE
OE
COE
CWE[7:4]
D[7:0]
D[15:8]
D[23:16]
D[31:24]
D[39:32]
D[47:40]
D[55:48]
D[63:56]
32Kx 8
32K x 8
A[17:5] ADDRESSLATCH
LE
CALE
A
FCT373C
CAA[4:3]
CAB[4:3]
CWE[3:0]
TWE
8Kx8
TIO[7:0]
CE
OE
WE
AD
CS
PD4 PD3 PD2 PD1 PD0
GND GND GND
NC NC
5V
GND
CY7C1199
CYM74C430
2
Pin Configuration
Top View
Dual Read–Out SIMM (DIMM)
10
9
5
6
7
8
4
1
2
GND
D63
GND
D62
NC
D58
D54
VCC
D61
VCC
D59
D55
D57
GND
D56
NC
D60
3
90
89
85
86
87
88
84
81
82
83
20
19
15
16
17
18
14
11
12
D52
D50
D46
D44
GND
D42
GND
D48
13
30
29
25
26
27
28
24
21
22
D38
D36
D32
D30
D26
D24
GND
D28
D34
GND
23
39
35
36
37
38
34
31
32
D22
NC
GND
NC
D14
D12
D16
D20
NC
33
40
41
42
GND
D10
52
51
47
48
49
50
46
43
44
NC
D8
D6
D4
D0
GND
A3
D2
NC
45
57
58
59
60
56
53
54
A5
GND
A7
55
69
65
66
67
68
64
61
62
GND
CWE6
CWE4
GND
63
70
79
75
76
77
78
74
71
72
CWE2
CWE0
73
80
D53
D51
GND
D49
D47
D45
D41
D43
100
99
95
96
97
98
94
91
92
93
D39
D37
D35
D33
D31
D25
D29
D27
110
109
105
106
107
108
104
101
102
103
D23
D21
VCC
D19
D15
D13
D17
120
119
115
116
117
118
114
111
112
113
D11
121
122
VCC
D9
D7
D5
D3
D1
127
128
129
130
126
123
124
125
GND
A6
A4
GND
140
139
135
136
137
138
134
131
132
133
GND
PD0
CWE5
CAA4
150
149
145
146
147
148
144
141
142
143
GND
GND
VCC
160
159
155
156
157
158
154
151
152
153
TIO0
TIO2
TIO6
TIO4
RSVD
TWE
CAA3
CAB4
NC (GWE)
NC (BWE)
A11
A16
NC
A18
A12
A13
NC
CS
NC (ECS2)
PD1
PD3
D40
D18
NC
GND
TIO1
TIO7
TIO5
TIO3
RSVD
RSVD
COE
CWE7
CWE1
CWE3
CAB3
CALE
RSVD
A8
A10
A17
A9
A14
A15
RSVD
PD2
PD4
NC
GND
GND
VCC
VCC
GND
VCC
GND
CYM74C430
3
Pin Definitions
Sig nal Name Description
VCC 5V Supply
GND Ground
A[18:3] Addresses from processor
CAA[4:3] Lower two address bits for bank 0
CAB[4:3] Lower two address bits for bank 1
CS Chip Select
COE Output Enable
CWE[7:0] Byt e Write Enables
CALE Latch Enable
PD0-PD4Pre sence Detect output pins
D[63:0] Dat a lines from processor
TIO[7:0] Tag data bits
TWE Tag Write Enable signal
NC Sig nal not connected on module
RSVD Reserved
Presence Detect Pins
MODULE PD4PD3PD2PD1PD0
CYM74C430 GND NC GND GND NC
Selectio n Guide
CYM74C430-50 CYM74C430-60 CYM74C430-65
Cache Size 256 KB
System Clock (MHz) 50 60 66
RAM Type Asynchronous 5V with outputs clam ped to 3.3V
Data RAM tAA 20 ns 17 ns 15 ns
Tag RAM tAA 30 ns 20 ns 15 ns
CYM74C430
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Maximum Ratings
(Above which the useful l ife may be impaired. For user guide-
lines, not tested.)
Storage Temperature................................. –55°C to +125°C
Ambient Tem per ature
with Power Applied........................................ –0°C to +70°C
5V Supply Voltage to Ground Potential....... –0.5V to +5.25V
DC Voltage Applied to Outputs
in High Z State.............................................. –0.5V to +4.6V
DC Input Voltage ........................................... –0.5V to +4.6V
Output Current into Outputs (LOW).............................20 mA
Document #: 38-M-00078
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C5V ± 5%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditio n Min. Max. Unit
VIH Input HIGH Voltag e 2.2 VCC + 0.3 V
VIL Input LOW Voltage –0.5 0.8 V
VOH Output HIGH Volt age VCC=Min. IOH = -4 mA 2.4 V
VOL Output LOW Voltage VCC=Min. IOL = 8 mA 0.4 V
ICC VCC Operating Supply Current VCC=Max., IOUT=0 mA, f=fMAX=1/tRC 1600 mA
Orde rin g Inf orm a tio n
Speed
(MHz) Ordering Code Package
Name Package Type Description Operating
Range
50 CYM74C430PM-50C PM37 160-Pin Dual-Readout SIMM Async 256 KB Commercial
60 CYM74C430PM-60C PM37 160-Pin Dual-Readout SIMM Async 256 KB Commercial
66 CYM74C430PM-66C PM37 160-Pin Dual-Readout SIMM Async 256 KB Commercial
Package Diagram
160–Pin Dual–Readout SIMM PM37
