SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Advanced BiCMOS Technology
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
Read and Write Operations Synchronized
to Independent System Clocks
D
Two Separate 512 × 18 Clocked FIFOs
Buffering Data in Opposite Directions
D
IRA and ORA Synchronized to CLKA
D
IRB and ORB Synchronized to CLKB
D
Microprocessor Interface Control Logic
D
Programmable Almost-Full/Almost-Empty
Flag
D
Fast Access Times of 9 ns With a 50-pF
Load and Simultaneous-Switching Data
Outputs
D
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9470401QXA
and 5962-9470401QYA
D
Package Options Include 84-Pin Ceramic
Pin Grid Array (GB) and 84-Pin Ceramic
Quad Flat (HT) Package
AF/AEB
HFB
IRB
GND
B0
B1
VCC
B2
B3
GND
NC
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
AF/AEA
HFA
IRA
GND
A0
A1
VCC
A2
A3
GND
NC
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
HT PACKAGE
(TOP VIEW)
NC
CSA
W/RA
GND
WENA
CLKA
RENA
ORA
NC
B16
A13
A14
A15
GND
A16
A11
ORB
GND
B15
B14
RENB
CLKB
WENB
GND
PENA
B13
B12
B11
W/RB
CSB
PENB
GND
CC
V
A17
B17
GND
RSTA
RSTB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
79 78 77 76 7580 74 72 71 7073 69 68 67 66 65 6484 82 8183
CC
V
CC
V
CC
V
A12
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GB PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
1234567891011
Terminal Assignments
TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME
A1 PENA B11 IRB F9 NC K2 A11
A2 CSA C1 GND F10 B6 K3 GND
A3 W/RA C2 HFA F11 GND K4 VCC
A4 WENA C5 CLKA G1 A5 K5 GND
A5 ORA C6 NC G2 GND K6 A17
A6 VCC C7 VCC G3 A4 K7 GND
A7 ORB C10 HFB G9 B4 K8 VCC
A8 WENB C11 GND G10 GND K9 GND
A9 W/RB D1 A1 G11 B5 K10 B10
A10 CSB D2 A0 H1 A7 K11 B9
A11 AF/AEB D10 B0 H2 GND L1 A10
B1 IRA D11 B1 H10 GND L2 A12
B2 AF/AEA E1 A3 H11 B7 L3 A13
B3 RSTA E2 A2 J1 A8 L4 A14
B4 GND E3 VCC J2 VCC L5 A16
B5 RENA E9 VCC J5 A15 L6 B15
B6 CLKB E10 B2 J6 NC L7 B16
B7 RENB E11 B3 J7 B17 L8 B14
B8 GND F1 A6 J10 VCC L9 B13
B9 RSTB F2 GND J11 B8 L10 B12
B10 PENB F3 NC K1 A9 L11 B11
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
A FIFO memory is a storage device that allows data to be read from its array in the same order it is written. The
SN54ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent
512 × 18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate
empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN54ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs
are active. The A0–A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data is
written to FIFOA–B from port A on the low-to-high transition of CLKA when CSA is low, W/RA is high, WENA
is high, and the IRA flag is high. Data is read from FIFOB–A to the A0–A17 outputs on the low-to-high transition
of CLKA when CSA is low, W/RA is low, RENA is high, and the ORA flag is high.
The state of the B0–B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs
are active. The B0–B17 outputs are in the high-impedance state when either CSB or W/RB is high. Data is
written to FIFOB–A from port B on the low-to-high transition of CLKB when CSB is low, W/RB is high, WENB
is high, and the IRB flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the low-to-high transition
of CLKB when CSB is low, W/RB is low, RENB is high, and the ORB flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable and read operations on memory and are not related to the high-impedance control of the data outputs.
If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the
chip select and write/read select can switch at any time during the cycle to change the state of the data outputs.
The input-ready and output-ready flags of a FIFO are two-stage synchronized to the port clocks for use as
reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the input-ready flag of a port is low, the FIFO receiving input
from the port is full and writes are disabled to its array . When the output-ready flag of a port is low , the FIFO that
outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty
memory is sent to the FIFO output register at the same time its output-ready flag is asserted (high). When the
memory is read empty and the output-ready flag is forced low , the last valid data remains on the FIFO outputs
until the output-ready flag is asserted (high) again. In this way, a high on the output-ready flag indicates new
data is present on the FIFO outputs.
The SN54ABT7819 is characterized for operation over the full military temperature range of –55°C to 125°C.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
ENABLE
&
0
D2
A0 D1
A1 E2
A2 E1
A3 G3
A4 G1
A5 F1
A6 H1
A7 J1
A8
B1
D11
B2
E10
B3
E11
B4
G9
B5
G11
B6
F10
B7
H11
B8
J11
Data
1
K1
A9 L1
A10 K2
A11 L2
A12 L3
A13 L4
A14 J5
A15 L5
A16
17
K6
A17
B9
K11
B10
K10
B11
L11
B12
L10
B13
L9
B14
L8
B15
L6
B16
L7
B17
J7
17
RSTA
PENA PROGRAM ENABLE
A1 RESET FIFOA–B
B3
A4
WENA
2
&
READ
FIFOB–A
OE1
&
ENABLE
&WRITE
FIFOA–B
W/RAA3
CLOCK A
C5
CLKA
B5
RENA
CSA A2
READ
ENABLE
FIFOA–B
&
WRITE
ENABLE
FIFOB–A
&
OE2
INPUT-READY
B1
IRA
OUTPUT-READY
A5
ORA
HALF-FULL
C2
HFA
ALMOST-FULL/EMPTY
B2
AF/AEA
FIFOA–B
PORT A
PORT A
FIFOA–B
B0
D10
0
CLKB
B6
CLOCK B
WENB
A8
RENB
B7
A10
B9
RESET FIFOB–A B10
PROGRAM ENABLE
IRB
B11
INPUT-READY
ORB
A7
OUTPUT-READY
HFB
C10
HALF-FULL
AF/AEB
A11
ALMOST-FULL/EMPTY
FIFOB–A
FIFOB–A
PORT B
PORT B
FIFOB–A
RSTB
PENB
CSB
W/RB
A9
Φ
FIFO 512 × 18 × 2
SN54ABT7819
FIFOA–B
Data
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the GB package.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
A0–A17
HFA
ORA
AF/AEA
IRA
RSTA
CLKA
W/RA
CSA
WENA
18
8
AF/AEB
IRB
WENB
W/RB
CSB
CLKB
RSTB
B0–B17
18
18
8
Flag
Logic
FIFOB–A
Write
Pointer
Read
Pointer
Register
Port-A
Control
Logic
Register
HFB
18
512 × 18
Dual-Port SRAM
FIFOB–A
Port-B
Control
Logic
Read
Pointer
Write
Pointer
Register Register
512 × 18
Dual-Port SRAM
FIFOA–B
Flag
Logic
FIFOA–B
RENA
ORB
RENB
PENA
PENB
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
enable logic diagram (positive logic)
CSA
W/RA
WENA
RENA
WEN FIFOA–B
Output Enable (A0–A17)
REN FIFOB–A
CSB
W/RB
WENB
RENB
WEN FIFOB–A
Output Enable (B0–B17)
REN FIFOA–B
Function Tables
A PORT
SELECT INPUTS
A0 A17
OPERATION
CLKA CSA W/RA WENA RENA
A0
–
A17
OPERATION
X H X X X High Z None
↑L H H X High Z Write A0–A17 to FIFOA–B
↑L L X H Active Read FIFOB–A to A0–A17
B PORT
SELECT INPUTS
B0 B17
OPERATION
CLKB CSB W/RB WENB RENB
B0
–
B17
OPERATION
X H X X X High Z None
↑L H H X High Z Write B0–B17 to FIFOB–A
↑L L X H Active Read FIFOA–B to B0–B17
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME I/O DESCRIPTION
A0–A17 I/O Port-A data. The 18-bit bidirectional data port for side A.
AF/AEA O FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA, or the default value of 128 can
be used for both the almost-empty of fset (X) and the almost-full offset (Y). AF/AEA is high when X or fewer words or
(512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high when FIFOA–B is reset.
AF/AEB O FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB, or the default value of 128 can
be used for both the almost-empty of fset (X) and the almost-full offset (Y). AF/AEB is high when X or fewer words or
(512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high when FIFOB–A is reset.
B0–B17 I/O Port-B data. The 18-bit bidirectional data port for side B.
CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its low-to-high transition
and can be asynchronous or coincident to CLKB.
CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its low-to-high transition
and can be asynchronous or coincident to CLKA.
CSA IPort-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from A0–A17 to
FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the high-impedance state when CSA
is high.
CSB IPort-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from B0–B17 to
FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the high-impedance state when CSB
is high.
HFA O FIFOA–B half-full flag. HFA is high when FIFOA–B contains 256 or more words and is low when FIFOA–B contains
255 or fewer words. HFA is set low after FIFOA–B is reset.
HFB O FIFOB–A half-full flag. HFB is high when FIFOB–A contains 256 or more words and is low when FIFOB–A contains
255 or fewer words. HFB is set low after FIFOB–A is reset.
IRA O Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFOA–B is full
and writes to its array are disabled. IRA is set low during a FIFOA–B reset and is set high on the second low-to-high
transition of CLKA after reset.
IRB O Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFOB–A is full
and writes to its array are disabled. IRB is set low during a FIFOB–A reset and is set high on the second low-to-high
transition of CLKB after reset.
ORA O
Port-A output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFOB–A is
empty and reads from its array are disabled. The last valid word remains on the FIFOB–A outputs when ORA is low .
Ready data is present for the A0–A17 outputs when ORA is high. ORA is set low during a FIFOB–A reset and goes
high on the third low-to-high transition of CLKA after the first word is loaded to an empty FIFOB–A.
ORB O
Port-B output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFOA–B is
empty and reads from its array are disabled. The last valid word remains on the FIFOA–B outputs when ORB is low .
Ready data is present for the B0–B17 outputs when ORB is high. ORB is set low during a FIFOA–B reset and goes
high on the third low-to-high transition of CLKB after the first word is loaded to an empty FIFOA–B.
PENA IAF/AEA program enable. After FIFOA–B is reset and before a word is written to its array, the binary value on A0–A7
is latched as an AF/AEA offset when PENA is low and CLKA is high.
PENB IAF/AEB program enable. After FIFOB–A is reset and before a word is written to its array, the binary value on B0–B7
is latched as an AF/AEB offset when PENB is low and CLKB is high.
RENA I Port-A read enable. A high level on RENA enables data to be read from FIFOB–A on the low-to-high transition of CLKA
when CSA is low, W/RA is low, and ORA is high.
RENB I Port-B read enable. A high level on RENB enables data to be read from FIFOA–B on the low-to-high transition of CLKB
when CSB is low, W/RB is low, and ORB is high.
RSTA IFIFOA–B reset. T o reset FIFOA–B, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must
occur while RSTA is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.
RSTB IFIFOB–A reset. T o reset FIFOB–A, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must
occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME I/O DESCRIPTION
WENA I Port-A write enable. A high level on WENA enables data on A0–A17 to be written into FIFOA–B on the low-to-high
transition of CLKA when W/RA is high, CSA is low, and IRA is high.
WENB I Port-B write enable. A high level on WENB enables data on B0–B17 to be written into FIFOB–A on the low-to-high
transition of CLKB when W/RB is high, CSB is low, and IRB is high.
W/RA I
Port-A write/read select. A high on W/RA enables A0–A17 data to be written to FIFOA–B on a low-to-high transition
of CLKA when WENA is high, CSA is low, and IRA is high. A low on W/RA enables data to be read from FIFOB–A
on a low-to-high transition of CLKA when RENA is high, CSA is low , and ORA is high. The A0–A17 outputs are in the
high-impedance state when W/RA is high.
W/RB I
Port-B write/read select. A high on W/RB enables B0–B17 data to be written to FIFOB–A on a low-to-high transition
of CLKB when WENB is high, CSB is low, and IRB is high. A low on W/RB enables data to be read from FIFOA–B
on a low-to-high transition of CLKB when RENB is high, CSB is low , and ORB is high. The B0–B17 outputs are in the
high-impedance state when W/RB is high.
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AF/AEA
HFA
ORB
IRA
RSTA
CLKB
CLKA
4321
214321
ÏÏÏÏÏ
ÏÏÏÏÏ
Figure 1. Reset Cycle for FIFOA–B†
†FIFOB–A is reset in the same manner.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
IRA
A0–A17
WENA
W/RA
CSA
0
1
CLKA
ÌÌÌ
ÌÌÌ
Word 1†W ord 2†Word 3†Word 4†
†Written to FIFOA–B
Figure 2. Write Timing – Port A
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
IRB
B0–B17
WENB
W/RB
CSB
0
1
CLKB
ÌÌÌ
ÌÌÌ
Word 1‡Word 2‡Word 3‡Word 4‡
‡Written to FIFOB–A
Figure 3. Write Timing – Port B
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÌÌÌÌÌ
ÌÌÌÌÌ
B0–B17
RENB
W/RB
CSB
ORB
CLKB
A0–A17
WENA
W/RA
CSA
CLKA
W1 From FIFOA–B
0
1
1
0
W1
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
321
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu
tpd tpd
tpd
Figure 4. ORB-Flag Timing and First Data-Word Fall-Through When FIFOA–B Is Empty†
†Operation of FIFOB–A is identical to that of FIFOA–B.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
To FIFOA–B
tpd
0
1
0
1
0
1
0
1
A0–A17
W/RA
WENA
CSA
IRA
CLKA
B0–B17
RENB
W/RB
CSB
CLKB
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏ
ÏÏÏ
From FIFOA–B
21
tpd
Figure 5. Write-Cycle and IRA-Flag Timing When FIFOA–B Is Full†
†Operation of FIFOB–A is identical to that of FIFOA–B.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
0
1
A0–A17
RENA
W/RA
CSA
ORA
CLKA
tdis
tpd
ten
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Word 1†W ord 2†Word 3†Word 4†
†Read from FIFOB–A
Figure 6. Read Timing – Port A
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
0
1
B0–B17
RENB
W/RB
CSB
ORB
CLKB
tdis
tpd
ten
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÎÎÎÎ
ÎÎÎÎ
Word 1‡W ord 2‡Word 3‡Word 4‡
‡Read from FIFOA–B
Figure 7. Read Timing – Port B
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
Figure 8. FIFOA – B (HFA, AF/AEA) Asynchronous Flag Timing
CLKA
WENA
IRA
A0–A17
CLKB
RENB
ORB
B0–B17
AF/AEA
HFA
W1 WX+1 WX+2 W256 W257 W512–Y W513–Y W513
W1 W2 WY+1 WY+2 W257 W258 W512–X W513–X
A. CSA, CSB = 0, W/RA = 1, W/RB = 0
C. HFB and AF/AEB function in the same manner for FIFO B – A.
B. X is the almost-empty offset and Y is the almost-full offset for AF/AEA.
NOTES:
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
offset values for AF/AE
The AF/AE flag of each FIFO has two programmable limits: the almost-empty offset value (X) and the almost-full
offset value (Y). They can be programmed from the input of the FIFO after it is reset and before a word is written
to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y) or more words.
T o program the offset values for AF/AEA, PENA can be brought low after FIFOA–B is reset and only when CLKA
is low. On the following low-to-high transition of CLKA, the binary value on A0–A7 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of CLKA
reprograms Y to the binary value on A0–A7 at the time of the second CLKA low-to-high transition.
During the first two CLKA cycles used for offset programming, PENA can be brought high only when CLKA is
low. PENA can be brought high at any time after the second CLKA pulse used for offset programming returns
low. A maximum value of 255 can be programmed for either X or Y (see Figure 9). To use the default values
of X = Y = 128, PENA must be tied high. No data is stored in FIFOA–B while the AF/AEA offsets are programmed.
The AF/AEB flag is programmed in the same manner , with PENB enabling CLKB to program the of fset values
taken from B0–B7.Figure 8
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
YX and YA0–A7
WENA
W/RA
CSA
PENA
IRA
CLKA
RESET
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÎÎ
ÎÎ
34
Figure 9. Programming X and Y Separately for AF/AEA
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . .
Current into any output in the low state, IO 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 VCC V
IOH High-level output current –12 mA
IOL Low-level output current 24 mA
∆t/∆vInput transition rise or fall rate 5 ns/V
TAOperating free-air temperature –55 125 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5
VOH VCC = 5 V, IOH = –3 mA 3 V
VCC = 4.5 V, IOH = –12 mA 2
VOL VCC = 4.5 V, IOL = 24 mA 0.5 0.55 V
IIVCC = 5.5 V, VI = VCC or GND ±1µA
IOZH§VCC = 5.5 V, VO = 2.7 V 50 µA
IOZL§VCC = 5.5 V, VO = 0.5 V – 50 µA
IO¶VCC = 5.5 V, VO = 2.5 V –40 –100 –180 mA
Outputs high 15
ICC VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs low 95 mA
Outputs disabled 15
CiControl inputs VI = 2.5 V or 0.5 V 6 pF
CoFlags VO = 2.5 V or 0.5 V 4 pF
Cio A or B ports VO = 2.5 V or 0.5 V 8 pF
‡All typical values are at VCC = 5 V, TA = 25°C.
§The parameters IOZH and IOZL include the input leakage current.
¶Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 10)
MIN MAX UNIT
fclock Clock frequency 50 MHz
twPulse duration CLKA, CLKB high or low 8 ns
A0–A17 before CLKA↑ and B0–B17 before CLKB↑5
CSA before CLKA↑
and CSB before CLKB↑7.5
W/RA before CLKA↑ and W/RB before CLKB↑7.5
tsu Setup time WENA before CLKA↑ and WENB before CLKB↑5ns
RENA before CLKA↑ and RENB before CLKB↑5
PENA before CLKA↑ and PENB before CLKB↑5
RSTA or RSTB low before first CLKA↑and CLKB↑†5
A0–A17 after CLKA↑ and B0–B17 after CLKB↑0
CSA after CLKA↑ and CSB after CLKB↑0
W/RA after CLKA↑ and W/RB after CLKB↑0
thHold time WENA after CLKA↑ and WENB after CLKB↑0ns
RENA after CLKA↑ and RENB after CLKB↑0
PENA after CLKA low and PENB after CLKB low 3
RSTA or RSTB low after fourth CLKA↑ and CLKB↑†4
†To permit the clock pulse to be utilized for reset purposes
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 10)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN MAX UNIT
fmax CLKA or CLKB 50 MHz
CLKA↑A0–A17 3 12
CLKB↑B0–B17 3 12
CLKA↑IRA 3 12
td
CLKB↑IRB 3 12
ns
t
pd CLKA↑ORA 2.5 12
ns
CLKB↑ORB 2.5 12
CLKA↑
AF/AEA
7 18
CLKB↑
AF/AEA
7 18
tPLH RSTA AF/AEA 3 15 ns
td
CLKA↑
AF/AEB
7 18
ns
t
pd CLKB↑
AF/AEB
7 18
ns
tPLH
RSTB AF/AEB 3 15
ns
t
PLH CLKA↑HFA 7 18
ns
CLKB↑
HFA
7 18
tPHL RSTA
HFA
3 15 ns
CLKA↑HFB 7 18
tPLH CLKB↑HFB 7 18 ns
tPHL RSTB HFB 3 15 ns
CSA
A0 A17
1.5 10
t
W/RA
A0
–
A17
1.5 10
ns
t
en CSB
B0 B17
1.5 10
ns
W/RB
B0
–
B17
1.5 10
CSA
A0 A17
1.5 10
tdi
W/RA
A0
–
A17
1.5 10
ns
t
dis CSB
B0 B17
1.5 10
ns
W/RB
B0
–
B17
1.5 10
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
th
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 7 V
Output
W aveform 2
S1 at Open
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 3 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈0 V
1.5 V 3 V
0 V
1.5 V 1.5 V 0 V
3 V
0 V
1.5 V 1.5 V
tw
Input
3 V 3 V
≈3.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
S1
500 Ω
LOAD CIRCUIT
500 Ω
7 V
From Output
Under Test Test
Point
NOTE A: CL includes probe and jig capacitance.
CL = 50 pF
(see Note A)
tsu
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
Open
Closed
Open
Closed
Open
Open
PARAMETER S1
ten
tdis
tpd
Figure 10. Load Circuit and Voltage Waveforms
SN54ABT7819
512 ×18 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMOR Y
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
typ + 2
typ
typ – 2 0 50 100 150
– Propagation Delay Time – ns
typ + 4
typ + 6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
200 250 300
tpd
CL – Load Capacitance – pF
VCC = 5 V
TA = 25°C
RL = 500 Ω
Figure 12
100
80
60
20
10 15 20 25 30 35 40
– Supply Current – mA
120
140
SUPPLY CURRENT
vs
CLOCK FREQUENCY
160
45 50 65 70
40
55 60
fclock – Clock Frequency – MHz
CC(f)
I
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
TA = 75°C
CL = 0 pF
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9470401QXA ACTIVE CPGA GB 84 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-9470401QX
A
SNJ54ABT7819GB
SNJ54ABT7819GB ACTIVE CPGA GB 84 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-9470401QX
A
SNJ54ABT7819GB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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information and additional product content details.
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the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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of the previous line and the two combined represent the entire Device Marking for that device.
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