MA AALSVI uP Compatible 8 Bit A/D Converter General Description The MAX160 and MX7574 are low cost, micropro- cessor compatible 8 bit analog-to-digital converters which use the successive-approximation technique to achieve conversion times of 4us (MAX160) and 15us (MX7574). The A/Ds are designed to easily interface with micro- processors by appearing as a memory location or I/O port without the need for external interfacing logic. Data outputs use latched, three-state buffer circuitry to allow direct connection to a microprocessor data bus or system input port. Operation is simplified by an on-chip clock, +5V power supply requirement, and low supply current (5mA max). The MAX160 provides major performance improve- ments over the AD7574 in accuracy and speed specifi- cations as well as compatibility with TTL logic levels. Applications Digital Signal Processing High Speed Data Acquisition Telecommunications Process Automation Instrumentation Avionics Functional Diagram Aw Bors Yoo Vree 3 THREE DATA OUT STATE ORIVERS 087-080 SUCCESSIVE APPROXIMATION REGISTER aS INTERFACE }__________ BUS & CONTROL Logic 1 5] m AD CLK Features @ improved Second Source (MAX160) @ Fast Conversion Time: 4us (MAX160) 15us (MX7574) @ No Missing Codes Over Temperature @ Single +5V Supply @ Ratiometric Operation @ No External Clock Necessary @ Easy Interface To Microprocessors Ordering Information PART TEMP. RANGE PACKAGEt ERROR MAX160CPN 0C to+70C ~ Plastic DIP +% LSB MAX160CC/D 0C to +70C ~Dice* +% LSB MAX160CWN 0C to+70C = Small Outline +% Se | MAX160EPN = -40C to +85C~S~ Plastic DIP +%LSB MAX160EWN = -40C to +85C_)~=s Small Outline +% LSB MAX160MJN = -55C to +125C = CERDIP** +%LSB MX7574KN oC to +70C ~~Pllastic DIP +% LSB MX7574JN 0C to+70C ~PPlastic DIP +% LSB MX7574KCWN = 0C to +70C ~ Small Outline 4% LSB MX7574UCWN = 0C to +70C ~ Small Outline +% LSB t All devices 18 lead packages Consult factory for dice specifications. ** Maxim reserves the right to ship Ceramic Packages in lieu of CERDIP packages. Ordering Information continued on last page Pin Configuration Top View MAXIM MAX160 0B7(MSB) [6 | MX7574 MAXIMA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. PZLSZXW/O9LXVWMAX160/MX7574 uP Compatible 8 Bit A/D Converter ABSOLUTE MAXIMUM RATINGS MAX160, MX7574 Supply Voltage, Vpp to AGND Vpp to DGND AGND to DGND Digital Inputs/Outputs (Pins 6-17) .... Analog Inputs (Pins 2-4) Power Dissipation (Any Package) to +70C Derate Above +70C by DGND - 0.3V, Vppt 0.3V OV, +7V Storage Temperature Range OV, +7V Operating Temperature Ranges . -0.3V, Vop MX7574AD/BD/AQ/BQ -20V, +20V MAX160EPN .+.. 670MW MAX160MDN/MJN 8.3mW/C MX7574SD/TD/SQ/TQ MAX160CPN, MX7574JN/KN/JCWN/KCWN ... -65C to +150C 0C to +70C -25C to +85C -40C to +86C -59C to +125C -55C to +125C +300C Stresses above those listed under Absoiute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect the device reliability. ELECTRICAL CHARACTERISTICS MAX160, MX7574 (Vpp = +5V, Vrer = -10V, Unipolar Configuration, Slow Memory Mode using External Clock fo_k = 2.0MHz for MAX160 and 0.5MHz for MX7574 (Fig. 9), Ta = Tain to Tmax, unless specified otherwise.) PARAMETER | symeot | CONDITIONS MIN. TYP, MAX. | UNITS | ACCURACY (feix = 2.0MHz for MAX160 and 0.5MHz for MX7574) Resolution 8 bits . MAX160,MX7574K/B/T +% Relative Accuracy Error MX7574.)/A/S +% LSB . . : . MAX160, M X7574K/B/T +% Differential Non-Linearity MX7574J/A/S +% LSB MAX160, Ta = +25C +3 Full Scale Error (Note 1) MX 7574K/B/T Ta = Tun tO Tyax +4.5 . LSB (Gain Error) Ta = +25C +5 MX7574J/A/S Tp = Train 10 Trax +65 Ta = +25C +20 MAX'60 Ta = Twin to Trax +30 Ta = +25C +30 Offset Error (Note 2) MX7574K/B/T Ta = Twin to Tuax +50 mv Ta = +25C +60 MX 7574J/A/S Ts = Twin to Tax +80 Mismatch Between Bors and Ain +415 of Resistances (Note 3) ~ ANALOG INPUTS Vrer Input Resistance 5 10 15 kQ Ain Input Resistance 10 20 30 kQ Bors Input Resistance 10 20 30 kQ Reference Voltage VRer +5% for specified transfer accuracy -10 Vv Reference Voltage Range (Note 4) 4 -15 Vv : Unipolar Mode 0 \Vreel Nominal Analog Input Range Bipolar Mode -\Vaed +\Vaed Vv LOGIC INPUTS | MAX160; RD, CS 24 Logic Input High Voltage VinH MX7574; RD, CS 3.0 Vv MAX160, MX7574; CLK 3.0 MAX160,MX7574; RD, CS 0.8 Logic Input Low Voltage VINL MAX160; CLK 0.8 Vv MX7574; CLK 0.4 an Ra _ Ta = +25C 4 Logic Input Current lin RD, CS, Vin = 0, Vpo Ta = Twin to Tuax 10 uA : _ Ta = +26C 2 Clock Input High Current Vin = Voo Ta = Tun to Tarax 3 mA _ Ta = +25C 1 Clock Input Low Current Vin = OV Ta = Twin to Tuax 10 pA Input Capacitance (Note 5) Cin RD, CS 5 7 | pF "| 2 MAALWVIuP Compatible 8 Bit A/D Converter ELECTRICAL CHARACTERISTICS MAX160, MX7574 (continued) PARAMETER | symeot | CONDITIONS [| MIN, TYP MAX. | UNITS LOGIC OUTPUTS Logic Output High Voltage Vou BUSY, DBO-DB7 Ispc = 200uA 4.0 Vv Se TEEee [care Logic Output Low Voltage VoL Ta = Tmin to Tuax v MAX160 0.4 MX7574 0.8 Floating State Leakage luke Vow) Veo t : n to Tmax 10 BA Floating State Capacitance (Note 5) DBO-DB7 5 7 pF POWER REQUIREMENTS Power Supply Requirement Voo +5V +5% for specified performance 4.75 5.25 v Power Supply Current lop Ain = OV, ADC in reset condition 1 5 mA Reference Current REF Conversion complete, before reset Vrer/5 V/kQ Note 1: Full scale error is measured after correcting for offset error. Max full-scale change from +25C to Tain or Tmax is +1LSB. Note 2: Maximum offset change from +25C to Twin OF Tmax is +10mvV. Typical offset temperature coefficient is 50V/C. Note 3: Reors/Rain mismatch causes transfer function rotation about positive full scale. The effect is an offset and gain term when using the circuit of Figure 9b. Note 4: Typical value, not guaranteed or subject to test. Note 5: Guaranteed but not tested. Typical Operating Characteristics CONVERSION TIME USING OFFSET ERROR vs. LINEARITY ERROR vs. INTERNAL CLOCK CONVERSION TIME CONVERSION TIME 20 30 30 18 Ta = 28C 18 Voo =|+5 Voge + -10V 2 UNIPOLAR MGDE 0 14 = = we 12 2 ond = = = IN OTHER MDDES Z10 z 10 X = 10 = rad BE 8 S 5 iN =< : NY Z NI 0 a 4 IN RGM MODE ; | 0 -10 -10 0 2 0 7 100 12 150 0 2 4 6 8 W 2 14 0 2 4 6 68 W 2 Reik (kO} - CONVERSION TIME {us} CONVERSION TIME [1.8] (FOR RAM AND SLOW MEMORY MODES} (FOR RAM AND SLOW MEMORY MODES) +5V +5 3kn 3k OBN OBN DBN OBN 3kQ) CL CL 3ka 10pF 1OpF = DGNO OGNO a. High-Z to Voy b. High-Z to Vo, a. Vox to High-Z = OGND b. Vo. to High-Z Figure 1. Load Circuits for Data Access Time Test MAXLM Figure 2. Load Circuits for Data Hold Time Test PLSLXIN/OOLXVINpP Compatible 8 Bit A/D Converter TIMING CHARACTERISTICS (Note 1, 2) MX7574 (Vpp = +5V, Cork = 100pF, Roik = 180k, unless otherwise specified.) PARAMETER SYMBOL CONDITIONS Ta = #25C Ta = Tum Ta= Tmax | units MIN. TYP MAX. | MIN. MAX. | MIN. MAX. STATIC RAM INTERFACE MODE (See Figure 5 and Table 5) CS Pulse Width Requirement tos 100 150 150 ns RD to CS Setup Time twscs 0 0 0 ns GS to BUSY C. = 20pF 50 120 120 180 Propogation Delay (Note 2) tcapo C_ = 100pF 70 150 150 200 ns BUSY to RD Setup Time tase 0 0 0 ns BUSY to CS Setup Time tascs 0 0 0 ns Data Access Time (Note 3) trap ct : 1 00pF to S00 boo 00 ns Data Hold Time (Note 4) temo | xrerware (| 6080 tz | 30120 | 50180 | ns CS to RD Hold Time trHcs 250 200 500 ns Reset Time Requirement 3 3 3 us Conversion Time Using Int CLK tconv See Graph 23 BS Conversion Time Using Ext CLK tconv fotk = 500kFRz 15 15 15 ys ROM INTERFACE MODE (See Figure 6 and Table 6) Data Access Time (Note 3) trap ct : ae to sep 300 00 ns Data Hold Time (Note 4) ten | MxTSTaJ/K/A/E so 80120 | 30120 | 80 180 | ns RDHIGH to BUSY Delay (Note 2) twapp C. = 20pF 700 = 1506 1000 2000 ns BUSY to RD LOW Setup Time tesa (Note 5) Conversion Time Using Int CLK tconv See Graph 25 us SLOW MEMORY INTERFACE MODE (See Figure 7 and Table 7) Data Access Time (Note 3) trap ct = ORF to de 300 an ns Satan Time sows) | two (Maes | ee mL Se] CS to BUSY t C. = 20pF 40 120 120 180 ns Propagation Delay (Note 2) CBPD C, = 100pF 60 150 150 200 Reset Time Requirement 3 3 3 us Conversion Time Using Int Clk tconv See Graph 23 us Conversion Time Using Ext Clk tconv foLk = 500kKHz 46 16 15 us Note 1: Note 2: Note 3: Note 4: Note 5: All input control signals are specified with ta = te = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Busy output crosses 0.8V or 2.4V. Outputs are loaded with circuits in Figure 1 and defined as the time required for an output to cross 0.8 or 2.4V. Outputs are loaded with circuits in Figure 2 and defined as the time required for an output to change 0.5V. RD can go low prior to BUSY = HIGH, but must not return HIGH until BUSY = HIGH. See Table 6. MAXLAA DLSZXW/O9LXVINMAX 160/MX75 74 uP Compatible 8 Bit A/D Converter TIMING CHARACTERISTICS (Note 1, 2) MAX160 (Vpp = +8V, Coik = 100pF, Roi = 22k, unless otherwise specified.) PARAMETER SYMBOL | CONDITIONS Ta = #25C Ta = Tun Ta=Twax_| units MIN. TYP MAX. | MIN. MAX. | MIN. MAX. STATIC RAM INTERFACE MODE (See Figure 5 and Table 5) CS Pulse Width Requirement tes 100 150 150 ns RD to CS Setup Time twses 0 0 0 ns CS to BUSY t C. = 20pF 60 100 100 130 ns Propagation Delay (Note 2) CBPD C, = 100pF 70 110 110 150 BUSY to RD Setup Time tesr 0 0 0 ns BUSY to CS Setup Time tascs 0 0 ns Data Access Time (Note 3) trap ct . Oop oo to too 40 ns Data Hold Time (Note 4) taHD 80 120 120 180 ns CS to RD Hold Time trHcs 250 230 500 ns Reset Time Requirement treseT 15 15 15 us Conversion Time Using Int CLK tconv Ret = 22kn 4 5 6 4 6 4 6 uS Internal Clock Temperature Drift 250 ppm/C Conversion Time Using Ext CLK tconv fork = 2.0MHz 4 4 4 us ROM INTERFACE MODE (See Figure 6 and Table 6) RD HIGH to BUSY Delay (Note 2) tweeo C, = 20pF 800 1200 1200 1200 ns BUSY to RD LOW Setup Time tesa (Note 5) Data Access Time (Note 3) trap c = 70ND oo too 400 uo ns Data Hold Time (Note 4) trHD 80 120 120 180 ns Conversion Time Using Int CLK tconv Reig = 22k 4 5 6 4 6 4 6 us SLOW MEMORY INTERFACE MODE (See Figure 7 and Table 7) | Data Access Time (Note 3) trap a = {on 4 ba too tao ns Data Hold Time (Note 4) tayp 80 120 120 180 ns CS to BUSY teppp | Ch 20PF 60 = 100 100 130 ns Propagation Delay (Note 2) C_ = 100pF 70 110 110 150 Reset Time Requirement 1.5 1.5 1.5 us Conversion Time Using Int CLK tconv Reik = 22k 4 5 6 4 6 4 6 us Conversion Time Using Ext CLK tconv teik = 2,.0MHz 4 4 4 Bs Note 1: All input control signals are specified with tr = tp = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Note 2: Busy output crosses 0.8V or 2.4V. Note 3: Outputs are loaded with circuits in Figure 1 and defined as the time required for an output to cross 0.8 or 2.4V. Note 4: Outputs are loaded with circuits in Figure 2 and defined as the time required for an output to change 0.5V. Note 5: RD can go low prior to BUSY = HIGH, but must not return HIGH until BUSY = HIGH. See Table 6. MA MXLAN 5MAX 160/MX7574 uP Compatible 8 Bit A/D Converter Pin Description PIN | NAME FUNCTION | PIN | NAME | FUNCTION | 4 | Vop Power supply voltage, +5V. ; 1 | DB2 Three-state data output, bit 2. 2 Vaer Reference Input, nominal -10V. 12 | 081 | Three-state data output, bit 1. 3 Bors Bipolar Offset Input, +10V for bipolar 13 | DBO Three-state data output, bit 0 (LSB). mode, connect to Ayn for unipolar mode. | { ' 14. | BUSY | BUSY output, BUSY goes low at the start 4 Ain Analog input, 0 to +10V for unipolar mode, | of a conversion and returns high when the : -10V to +10V for bipolar mode. i conversion is complete. 1 7 i 5 AGND | Analog Ground. | 15 RD READ input, RD must be low to access | data. See Digital Interface section. 6 DB7 Three-state data output, bit 7 (MSB). ! __ , | | 16 CS j{ CHIP-SELECT input. Used for conversion 7 DB6 | Three-state data output, bit 6. ! | ; control or device addressing. See Digital | : i ! Interface section. 8 DB5 | Three-state data output, bit 5. | } | ' 417 CLK {| External clock input/Internal clock / 9 DB4 | Three-state data output, bit 4. | | frequency set input. [ 10 | DB3 i Three-state data output, bit 3. _ 8 DGND i Digital Ground. Detailed Description Converter Operation The MAX160/MX7574 uses the successive approxi- mation technique to convert an unknown analog input to an 8 bit digital output code. The control logic provides easy interface to most microprocessors. Most applications require only passive clock components, a -10V reference, and a +5V power supply. Figure 3 shows the MAX160/MX7574 functional_dia- gram. When a start command is received from CS or RD (see Digital Interface Section), BUSY goes low indicating that the conversion is in progress. Suc- cessive bits, starting with the most significant bit (MSB), are applied to the input of a DAC. The comparator determines whether the addition of the bit causes the DAC output to be larger or smaller than the analog input, Ayy. If the DAC output is greater than Ajn, the trial bit is turned OFF, otherwise it is kept ON. Each successively smaller bit is tried and compared to Ain in this manner until the least significant bit (LSB) decision has been made. When all bits have been tried, BUSY goes high, indicating that the conversion is complete and the successive approximation register contains a valid representation of the analog input. The data can then be read using the RD input (see Digital Interface Section). DAC Circuit Details A thin film R-2R resistor network provides binarily weighted currents for each bit in the internal multi- plying DAC (see Figure 4). N-channel MOS switches are used to steer current to either the summing junction or AGND depending on the DAC digital code. The Ain and Bors input resistors also use series MOS switches (always ON) that match the DAC switches to maintain gain temperature tracking. Ain Bors Voo Ver 613 DATA THREE STATE OUT ORIVERS 0B70B0 SUCCESSIVE APPROXIMATION REGISTER aS INTERFACE }+-_________-___-. BUSY & CONTROL LOGIC i6| 5 m| tS RD CLK Figure 3. MAX160/MX7574 Functional Diagram MAXAILVIuP Compatible 8 Bit A/D Converter SUCCESSIVE APPROXIMATION REGISTER Vaee A R R A Aw Bors 2R rai) 2A 2R aa aR 2R 4 | SUMMING Jt NODE MSB LSB t O87 ons { eS O80 AGND COMPARATOR Figure 4. D/A Converter Used in the MAX 160/MX7574 Table 5. Truth Table, Static Ram Mode [ INPUTS OUTPUTS [ MAX160/MX7574 OPERATION cs RD BUSY DB7-DBO L L H H HI-Z Write Cycle (Start Convert} L LE H HI-Z to DATA Read Cycle (Data Read) , L Sf H DATA to HI-Z Reset Converter H X (Note 1) x HI-Z Not Selected = i. : L | H L HI-Z No Effect (Converter Busy) . L 1 [ L HI-Z No Effect (Converter Busy) | L S7 HI-Z Not Allowed, Conversion Error Note 1: If RD goes LOW to HIGH, the ADC is internally reset, regardless of the state of CS or BUSY. twscs tase MICROPROCESSOR MEMORY WRITE TO NOP OR OTHER OPERATION MAX160/MX7574 INSTRUCTIONS ADDRESS UNTIL BUSY = HIGH _ r- tes CS (PIN 16) AD [PIN 15) fo _f MEMORY READ TO MAX160/MX7574 ADDRESS {cero [CONVERT D87-080 PINS 6-13) BUSY (PIN 14] " {RESET - ft tascs I | Iman teHo DATA HIGH-2 Figure 5, Static RAM Mode Timing Diagram MAAIM PZLSZLXW/O9LXVINMAX 160/MX7574 uP Compatible 8 Bit A/D Converter Table 6. Truth Table, Rom Mode RD (PIN 15} ~\ {~ ADDRESS INPUTS OUTPUTS = MAX160/MX7574 OPERATION cs RD BUSY DB7-DBO L L H HI-Z to DATA Data Read L a L DATA to HI-Z Reset and Start New Conversion 1 L TV. L HI-Z No Effect (Converter Busy) L SL L HI-Z Not Allowed, Conversion Error MEMORY READ TO MEMORY READ TD ota ral MAX160/ MX 7574 NOP OR OTHER INSTRUCTIONS MAX160/MX7574 ADDRESS , tween tcowverT BUSY (PIN 14) (PIN 6-13) L HIGH-Z 067-080 __HIGHZ { DATA trad Figure 6. ROM Mode Timing Diagram (CS Held Low) Table 7. Truth Table, Slow Memory Mode CS & RD (PINS 15 & 16) INPUTS OUTPUTS == MAX160/MX7574 OPERATION CS &RD BUSY DB7-DB0 H H HI-Z Not Selected L HL HI-Z Start Conversion L i L HI-Z Conversion in Progress. uP in WAIT State L Sf HI-Z to DATA Conversion Complete. P READS Data am H DATA to HI-Z Converter Reset and Deselected H H HI-Z Not Selected MICROPROCESSOR MEMORY READ TO MAX160/MX7574 ADDRESS uP COMPLETES | OPERATION (uP IN WAIT STATE WHILE BUSY 1S LOW) MEM READ f_* tconvenT treseT BUSY (PIN 14] teppo 987-BBO _ HIGH-2 _ (PINS 6-13) Figure 7. Slow Memory Mode Timing Diagram (CS and RD Tied Together) : MAXI!uP Compatible 8 Bit A/D Converter Digital Interface The MAX160/MX7574 has three interface modes which are determined by the timing of the CS and RD inputs. Static RAM Interface Mode Table 5 and Figure 5 show the truth table and timing requirements for interfacing the MAX160/MX7574 as a static RAM. A conversion is started by executing a memory WRITE instruction to the MAX160/MX7574 address. Once a conversion is in progress, subsequent WRITE opera- tions have no effect. Data is read by executing a memory READ operation to the A/Ds address. BUSY must be high before a READ is attempted. In other words, the elapsed time between WRITE and READ_must be greater than the conversion time. Once BUSY is HIGH (end of conversion) the data READ can be performed. The data readout is de- structive, since the MAX160/MX7574 is internally reset when RD goes high. Note that CS remaining LOW longer than the hold time (taycs) will initiate a new conversion. ROM Interface Mode Table 6 and Figure 6 show the truth table and timing requirements for interfacing the MAX160/MX7574 as Read Only Memory. In this mode the CS input is not used and is held low. The RD input is derived from the decoded device address. A data READ is initiated by exe- cuting a memory READ instruction to the MAX160/ MxX7574 address location. A conversion automatically starts when RD returns HIGH. Similar to the RAM mode, attempting a READ before BUSY goes HIGH will result in incorrect data being read. The advantage of the ROM mode is its simplicity. The major disadvantage is that the data obtained is poorly defined in time since the conversion is per- formed at the end of a previous READ operation. This problem can be overcome by performing two READ operations back to back and only using the data from the second read. Slow-Memory Interface Mode Table 7 and Figure 7 show the truth table and timing requirements for interfacing the MAX160/MX7574 as slow memory. This mode is intended for processors that can be forced into a WAIT state for periods as long as the MAX160/MX7574 conversion time. In this mode CS and RD are tied together. The decoded device address is used to drive CS/RD. MIAXIMNI The BUSY output is connected to the processor's READY input. A conversion is initiated by executing a_ memory READ to the MAX160/MX7574 address. BUSY then goes LOW and forces the processor into a WAIT state. At the end of the conversion, BUSY returns high and the data is available at the data outputs. The major advantage of the slow memory mode is that it allows the processor to start and end a conversion and read the result with a single READ instruction. Do not attempt a memory WRITE in this mode, since a three-state bus conflict will arise. Interface Application Hints Timing and Control Failure to observe the timing restrictions of Figures 5-7 may cause the MAX160/MX7574 to change inter- face modes. For example, in the RAM mode, if CS is held low for too long, the converter moves into the ROM mode since a new conversion starts. Logic Deglitching in uP Applications Unspecified states in the address _bus can cause glitches at the MAX160/MX7574 CS or RD inputs. Such glitches can cause undesired conversion starts, resets or data reads. The best method for avoiding these problems is to gate the address decode with WR or RD when in the RAM or ROM moges. In the slow memory mode use latched address inputs. initialization After Power-Up To initialize the MAX160/MX7574 at power-up, perform a memory READ to its address location and ignore the data. Clock internal Oscillator The MAX160/MX7574 has in internal asynchronous clock oscillator which starts when a convert command is received and stops at the end of a conversion. The oscillator requires an external resistor and capac- itor connected as shown in Figure 8. The internal oscillator has good initial accuracy and stability over temperature and supply voltage. See Typical Operat- ing Characteristics for typical conversion times versus Revk with Ccik set at 100pF. To prevent false triggering of the internal clock, Rok and Cc_k must be placed close to the CLK pin and coupling from the CS and RD inputs must be minimized. PLSZXW/O9LXVWNMAX 160/MX7574 uP Compatible 8 Bit A/D Converter Voo [+5) OGAD} Yoo CLK) MAXIM MAX160 Mx7574 Rex DEND Figure 8. Connecting Rcoi and CLK to CLK Oscillator Von [+5) < j Veo pcnpf-18 $ RI (6k {2-100k{2] cx? MAXIM MAX160 68 MX7574 EXTERNAL CLOCK IN 1/4 74125 THREE-STATE BUFFER Figure 9. External Clock Operation (Static RAM and Slow Memory Mode) Operation With External Clock For applications where synchronous operation is required or the conversion time must be accurately controlled, an external clock can be used. Figure 9 shows how an external clock is connected. The BUSY output is connected to the three-state enable input of a 74125 buffer. A 500kHz clock provides a conversion time of 15us. The external clock should be used only in the static-RAM or slow-memory modes and not in the ROM mode. Timing constraints for the external clock operation are as follows: STATIC RAM MODE 1, When initiating a conversion, CS should go low on a positive clock edge to provide optimum settling time for the MSB. 2. A data READ can be performed at any time after BUSY = HIGH. SLOW MEMORY MODE 1. When starting a conversion, CS and RD should go low on a positive clock edge to provide optimum settling time for the MSB. 10 Analog Considerations Application Hints Input Loading at Vref, Ain, and Bors To prevent input loading effects due to the finite input resistance of these pins, low impedance driving sources must be used (i.e. op-amp buffers, or low output impedance references). Ratilometric Operation Ratiometric operation is inherent for the multiplying DAC scheme used on the MAX160/MX7574. However, the user must recognize that comparator limitations such as offset voltage, input noise and gain degrade the transfer function at reference voltages less than -10V. Offset Correction Offset error in the transfer function can be trimmed by offsetting the buffer that drives the Ajj input. This can be achieved either by summing a cancellation current into the amplifiers summing junction, or by tapping a voltage divider which sits between Vpp and Vrer and applying the tap voltage to the amplifier's non-inverting input. An example of the latter method can be seen in Figure 12. Analog and Digital Ground It is recommended that the AGND and DGND pins be connected locally to prevent noise injection into the A/D converter. In systems where the AGND-DGND connection is not local, clamp diodes should be connected between AGND and DGND to keep the two ground busses within one diode drop of each __ other. Unipolar Binary Operation : Figures 10 shows the analog circuit connections and nominal transfer characteristic for unipolar operation. Calibration is as follows: Offset lf offset trimming is required, it must be done in the signal conditioning circuitry used to drive the Ain input in Figure 10. See also the offset trim example shown in Figure 12. 1. Apply -39.1mV (1 LSB) to the input of the buffer amplifier used to drive R1 (i.e. +39.1 mV at R1). 2, Adjust the offset potentiometer until 0B7-DB1 are LOW and DB0 flickers. Gain (Full Scale) Offset adjustment must be performed prior to gain adjustment. To trim gain: 1. Apply -9.961V to the input of the buffer that drives R1 (ie. +9,.961V at R1). 2. Adjust trimpot R2 until DB7-DB1 are HIGH and DBO flickers. MAAIL/VIuP Compatible 8 Bit A/D Converter Bipolar (Offset Binary) Operation Figure 11 illustrates the analog circuitry and transfer function for bipolar operation. The output coding is offset binary. Offset correction can be performed at the buffer amplifier used to drive the signal input terminals of the MAX160/MX7574. See Figure 12 for an example of how offset trimming can be performed. Calibration is as follows: 1. Adjust R6 and R7 for minimum resistance across the potentiometers. 2. Apply +10.000V to the buffer amplifier used to drive the signal input (ie. -10.000V at R6). Then trim R6 or R7 (whichever is required) unti! DB7-DB1 are LOW and DBO flickers. 3. Apply OV to the buffer amplifier used to drive the signal input terminals. Then trim the offset circuit of the buffer amplifier until the ADC output flickers between 01111111 and 10000000. 4. Apply +10.000V to the input of the buffer amplifier (i.e. -10.000V as applied to R6). Then trim R2 until DB7-DB1 are LOW and DBO flickers. 5. Apply -9.922V to the input of the bufferamplifier (i.e. +9.922V at the input side of R6). If the ADC output code is Not 11111110 + 1 bit, repeat the calibration procedure. ~15V +5V OUTPUT CODE | RB ; 8 Wi 12k OB MAXIM GAIN TRIM Yoo geno 1 nine R2 2k) Ly Mx584 4 i REFERENCE HEF = inal 3 3) Maxim ae eTuRN . | Bars MAX160 | 0.01 uF AL 1K!) 10% 4 MX7574 \ AWW SIGNAL 0000011 INPUT Sl scan ov TO +1 aononat 0000001 = ooooocaa pop rw bo ANALOG SUPPLY 0 004 008 0.12 0.16 992 996 100 RETURN R1 and R2 can be omitted if gain trim is not required (NPUT VOLTAGE (VOLTS) Approximate bit weights are shown for illustration Figure 10. Unipolar (OV to +10V) Operation and Nominal Transfer Characteristic (Output Code is Straight Binary) +5u Ra 10k!) 1 RB 10ki2 Yoo OGND VaEF +ibV MAXIM *10V borg MAX160 fo ONS YX7574 MAXIM 4 Al 4 hy MX584 PAW>$ SIGNAL REFERENCE | 310K0) = PAA Wk!Y | RE 2ke % AGND OUTPUT CODE 10000100 GAIN TRIM RS ok.) ANALOG SUPPLY RETURN R1 and R2 can be omitted if gain trim is not required L vooood! = 10000010 | DIGITAL SUPPLY RETURN 1000000) + 10000000 OW F r ona F ono) F 07111100 - onan {4 __1 L 1 4 4 400-320-240 -160 -80 0 80 160 240 320 400 (NPUT VOLTAGE (MILLIVOLTS] Approximate bit weights are shawn for illustration Figure 11. Bipolar (-10V to +10V) Operation and Nominal Transfer Characteristic Around Major Carry (Output Code is Offset Binary) MAXI 11 PLSZLXIN/OOLXVANMAX160/MX7574 uP Compatible 8 Bit A/D Converter Bipolar (Complementary Offset Binary) Operation Figure 12 shows the analog connections for offset binary operation. The typical transfer characteristic is also shown. In this bipolar mode, the input signal (-10 to +10V) is conditioned and the A/D basically operates in unipolar mode (0 to +10V). Calibration is as follows (offset adjusted before gain): Offset 1. Apply OV to the analog input shown in Figure 12. 2. Adjust R9 until the converter output flickers be- tween codes 01111111 and 10000000. Gain (Full Scale) 1. Apply -9.922V across the analog input terminals shown in Figure 12. 2. Adjust R2 until DB7-DB1 are HIGH and DBO flickers between HIGH and LOW. -15V A? QUTPUT CODE ANALOG SUPPLY RETURN Note 1: Ai and R2 can be omitted if gain trim is not required. Note 2: R8, R9 and R10 can be omitted if offset trim is not required. Note 3: R6||R8}/R10 = 5k. If R8, R9 and R10 are not used, make Rg = 5k. ake GAIN ADJUST +8V onto 9 } 1 MAXIM 4 ~10 ee onto + 4 MX584 DAK REFERENCE ston : [ OUNOT F T AUT < a | S nS 20k UY a re omnia F 4 RA 20K | RI TOKO A AN 2 Vee + DNF MAXIM DIGITAL SUPPLY igqgoo00 + RI a. MAX160 RETURN - 12) 10% OS AX 7574 oooo001 741 Ar ta ANALOG + RB 27k!) Ain 40000010 INPUT 5 voo00011 | AGND DEFSET 2 FS 20k! 19000100 4 RG s ADJUST | R10 5BK) yo000101 Ll 1 L 1 1 to 4 68kKO & -400-320-240 -160 -80 0 80 160 240 320 400 T INPUT VOLTAGE (MILLIVOLTS) Approximate bit weights are shown for illustration. Figure 12. Bipolar (-10V to +10V) Operation and Nominal Transfer Characteristic Around Major Carry (Output Code is Complimentary Offset Binary} Ordering Information (continued) Chip Topography t+ All devices 18 lead packages PART TEMP RANGE PACKAGEt ~~ ERROR nor MX7574AQ 25C to +85C CERDIP** +% LSB 25CSRM MX7574BQ --25C to +85C CERDIP** +% LSB ner Von clk MX75748Q 55C to +125C = CERDIP** =-% LSB MX7574TQ ~s--55C to +125C ~SsCEERDIIP** = 4 LSB MX7574AD --25C to +85C Ceramic +% LSB MX7874BD 28C to +85C Ceramic +% LSB MX7574SD -5C to +125C Ceramic +% LSB MX7574TD -55C to +125C Ceramic +% LSB ** Maxim reserves the right to ship Ceramic Packages in lieu of CERDIP packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1995 Maxim Integrated Products Printed USA MAAXIAA js a registered trademark of Maxim Integrated Products