M48T35Y-70PC6TR - STMicroelectronics

1/18February 2000

M48T35

M48T35Y

256 Kbit (32Kb x8) TIMEKEEPER® SRAM

■INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL

CIRCUIT and BAT TERY

■BYTEWIDE™ RAM-LIKE CLOCK ACCESS

■BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES and SECONDS

■FREQUENCY TEST OUTPUT for REAL TIME

CLOCK

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE P ROTEC T ION

■WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T35: 4.5V ≤ VPFD ≤ 4.75V

– M48T 35Y : 4.2V ≤ VPFD ≤ 4.5V

■SELF - CONTAI N ED BATT ERY and CRY STAL

in the CAPHAT DIP PACKAGE

■SOIC PAC KAG E PR OV IDES D IR ECT

CONNECTION for a S NAPHA T HOUSING

CONTAINING the BAT TERY and CRYSTAL

■SNAPHAT® HOUSING (BATTERY and

CRYST AL ) is REPL AC EABLE

■PIN and FUNCTION COM PAT IBLE with

JEDEC STANDARD 32Kb x8 SRAMs

Figure 1. Logic Diagram

AI01620B

A0-A14

DQ0-DQ7

VCC

M48T35

M48T35Y

VSS

Table 1. Signal Names

A0-A14 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

EChip Enable

GOutput Enable

WWrite Enable

VCC Supply Voltage

VSS Ground

SOH28 (MH)

SNAPHAT (SH)

Battery

PCDIP28 (PC)

Battery CAPHAT

M48T35, M48T35Y

2/18

Figure 2A. DIP Connect ions

DQ0

A13

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

A14 VCC

AI01621B

14 16

M48T35

M48T35Y

Table 2. Absolute Maximum Ratings (1)

Note: 1. Stres ses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This i s a stress

rating only and functi onal operation of the device at these or any other con di tions above th ose indic at ed in th e operational section

of this spec ification is not implie d. Exposure to t he absolute maximum rating conditio ns fo r extende d period s of time may affe ct

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not t o exceed 150°C f or longer than 30 seconds).

CAUTION: Negative undershoots bel ow –0.3V are not all owed on any pin while i n the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature Grade 1 0 to 70 °C

Grade 6 –40 to 85 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C

TSLD (2) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

Figure 2B. SOIC Connections

AI01622B

DQ0

A13

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

A14 VCC

M48T35Y

DESCRIPTION

The M48T35/35Y TIMEKEEPER® RAM is a 32Kb

x8 non-volatile static RAM and real time clock. The

monolithic chip is availa ble in two spec ial packag-

es to provide a highly integrated battery backed-up

memory and real time clock solution.

The M48T35/ 35Y is a non-volatile pin and funct ion

equivalent to any JEDEC standard 32Kb x8

SRAM. It also easily fits into many ROM, EPROM,

and EEPROM sockets, providing the non-volatility

of PROMs without any requirement for special

write timing or limitations o n the number o f writes

that can be performed.

The 28 pin 600mil DIP CAPHAT houses the

M48T35/35Y silicon with a quartz crystal and a

long life lithium button cell in a single package .

The 28 pin 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

3/18

M48T35, M 48T35Y

nection to a separate SN APHAT hous ing contain-

ing the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process. Inser-

tion of the SNAPHAT housing after reflow pre-

vents pote ntial b attery and crystal dam age d ue t o

the high temperatures required for device s urface-

mounting. The SNA PHAT housing is k eyed t o pre-

vent reverse i nsertion. The SOIC and battery/crys-

tal packages are shipped separ ately in plastic anti-

static tubes or in Tape & Reel form.

For the 28 lead SOI C, the battery/crystal package

(i.e. SNAPHAT) part number is "M4T28-

BR12SH1".

As Figure 3 shows, the static memory array and

the quartz controlled clock oscillator of the

M48T35/35Y are integrated on one silicon chip.

The two circuits are interconnected at the upper

eight memory locations to provide user accessible

BYTEWIDE clock information in the bytes with ad-

dresses 7FF8h-7F FFh.

Table 3. Operating Modes (1)

No te: 1. X = V IH or VIL; V SO = Battery Back -u p Swit ch ov er Volta g e.

2. See Table 7 for details .

Mode VCC E G W DQ0-DQ7 Power

Deselect

4.75V to 5.5V

4.5V to 5.5V

VIH X X High Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High Z Active

Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby

Deselect ≤ VSO X X X High Z Battery Back-up Mode

Figu re 3. Blo ck D ia gra m

AI01623

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

A0-A14

DQ0-DQ7

POWER

M48T35, M48T35Y

4/18

The cl ock locations contain the year, month, date,

day, hour, minute, and second in 24 hour BCD for-

mat. Corrections for 28, 29 (leap year), 30, and 31

day months are made automatically. Byte 7FF8h

is the clock control register. This byte controls user

access to t he clock information and also stores the

clock calibrat ion setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT read/write memory cells.

The M48T35/35Y includes a clock control circuit

which updates the clock bytes with current infor-

mation once per second. The information can be

accessed by t he us er i n t he sa me m anner a s any

other location in the static memory array.

The M48T35/ 35Y also has its ow n Power-fail De-

tect circuit. The control circuitry constantly moni-

tors the single 5V supply for an out of tolerance

condition. When VCC is out of tolerance, the circuit

write protects the SRAM, providing a hig h degree

of data sec urity in t he midst of unpredictable sys-

tem operation brought on by l ow VCC. As VCC falls

below approxim ately 3V, the c ontrol circuitry con-

nects the battery which maintains data and clock

operation until valid power returns.

READ MODE

The M48T35/35Y is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 15 Ad-

dress Inputs defines which one of the 32,768 by tes

of dat a is to be acce sse d. Vali d data w ill be av ail-

able at the Data I/O pins within Address Access

time (tAVQV) after the last address input signal is

stable, providing that the E and G access times

are also satisfied.

If the E and G access times are not met, valid data

will be av ailable a f te r the la t ter of the Ch i p Enable

Access time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven t o an

indeterminate state until tAVQV.

If the Address Inputs are changed while E and G

remain active, output data will remain valid for Out-

put Data Hold time (tAXQX) but will go indetermi-

nate unt i l the next Address Access.

WRITE MODE

The M48T35/35Y is in the Write Mode whenever

W and E are low. The st art of a write is referenced

from the lat ter occurring f alling edge of W or E. A

write is terminated by the ea rlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for a minimum

of tEHAX from Chip Enable or tWHAX from Write En-

able prior to the initiation of another read or write

cycle. Data-in must be valid tDVWH prior to the end

of write and remain valid for tWHDX afterward. G

should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E a nd G, a low on W

will dis able the o ut p ut s tWLQZ after W falls.

Table 4. AC Measu remen t Conditions

Not e that Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Figure 4 . AC Testing Load Circuit

AI01030

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

1.9kΩ

DEVICE

UNDER

TEST

1kΩ

5/18

M48T35, M 48T35Y

Table 5. Capaci tance (1, 2)

(TA = 25 °C)

No te : 1. Effective capacit ance measure d wi t h powe r suppl y at 5V.

2. Sampled only, not 100% tested.

3. Outputs desel ected .

Table 6. DC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

No te : 1. Outputs des el ected.

2. N e gativ e s p i k e s of –1V a l l owed for up to 10 ns o nce per cy cl e.

Table 7. Pow er Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C)

Note: 1. All v oltages referenced to VSS.

2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).

3. Usi ng l arger M 4T 32-BR12SH 6 SNAPHA T top (rec om m ende d for Indu st ri al Tem perature Range - grade 6 de vice).

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 10 pF

CIO (3) Input / Output Capacitance VOUT = 0V 10 pF

Symbol Parameter Test Condition Min Max Unit

ILI (1) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO (1) Output Leakage Current 0V ≤ VOUT ≤ VCC ±5 µA

ICC Supply Current Outputs open 50 mA

ICC1 Supply Current (Standby) TTL E = VIH 3mA

CC2 Supply Current (Standby) CMOS E = VCC – 0.2V 3mA

IL (2) Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 V

Symbol Parameter Min Typ Max Unit

VPFD Power-fail Deselect Voltage M48T35 4.5 4.6 4.75 V

M48T35Y 4.2 4.35 4.5 V

VSO Battery Back-up Switchover Voltage 3.0 V

tDR Expected Data Reten tion Time

(at 25°C) Grade 1 10 (2) YEARS

Grade 6 10 (3) YEARS

M48T35, M48T35Y

6/18

Table 8. Power Down/Up AC Chara cteri stics

(TA = 0 to 70 °C or –40 to 85 °C)

Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/wri te protection not occurring until 200µs after VCC pass-

es VPFD (min) .

2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

3. tREC (min) = 20m s for in dustrial temperatu re grad e (6) device.

Symbol Parameter Min Max Unit

tPD E or W at VIH before Power Down 0µs

tF (1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB (2) VPFD (min) to VSS VCC Fall Time 10 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

REC (3) VPFD (max) to Inputs Recognized 40 200 ms

Figure 5. Power Down/Up Mode AC Waveforms

AI01168C

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF tFB tR

tPD tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tREC

7/18

M48T35, M 48T35Y

Figure 6. Read Mode AC Waveforms.

Note: Write Enab le (W) = High.

AI00925

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A14

DQ0-DQ7

VALID

Table 9. Read Mode AC Characteri stics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Note: 1. CL = 100pF.

2. CL = 5pF .

Symbol Parameter

M48T35 / M48T35Y

Unit-70

Min Max

tAVAV Read Cycle Time 70 ns

tAVQV (1) Address Valid to Output Valid 70 ns

tELQV (1) Chip Enable Low to Output Valid 70 ns

tGLQV (1) Output Enable Low to Output Valid 35 ns

tELQX (2) Chip Enable Low to Output Transition 5 ns

tGLQX (2) Output Enable Low to Output Transition 5 ns

tEHQZ (2) Chip Enable High to Output Hi-Z 25 ns

tGHQZ (2) Output Enable High to Output Hi-Z 25 ns

tAXQX (1) Address Transition to Output Transition 10 ns

M48T35, M48T35Y

8/18

Table 10. Write Mo de AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Note: 1. CL = 5pF.

2. If E goes low simultaneously with W going low , t he output s remai n in the hi gh i m pedance state.

Symbol Parameter

M48T35 / M48T35Y

Unit-70

Min Max

tAVAV Write Cycle Time 70 ns

tAVWL Address Valid to Write Enable Low 0 ns

tAVEL Address Valid to Chip Enable Low 0 ns

tWLWH Write Enable Pulse Width 50 ns

tELEH Chip Enable Low to Chip Enable High 55 ns

tWHAX Write Enable High to Address Transition 0 ns

tEHAX Chip Enable High to Address Transition 0 ns

tDVWH Input Valid to Write Enable High 30 ns

tDVEH Input Valid to Chip Enable High 30 ns

tWHDX Write Enable High to Input Transition 5 ns

tEHDX Chip Enable High to Input Transition 5 ns

tWLQZ (1, 2 ) Write Enable Low to Output Hi-Z 25 ns

tAVWH Address Valid to Write Enable High 60 ns

tAVEH Address Valid to Chip Enable High 60 ns

tWHQX (1, 2) Write Enable High to Output Transition 5 ns

DATA RETENTION MODE

With valid VCC applied, the M48T35/35Y operates

as a conventi onal BYTEWIDE stat i c RAM. Shoul d

the supply voltage de cay, the RAM will automati-

cally power-fail deselect, write protecting itself

when V CC fall s w ithin t he V PFD (max), VPFD (min)

window. All outputs become hig h impedance, and

all inputs are treated as "don't care."

Note: A power failure during a write cyc le may cor-

rupt data at the currently addressed location, but

does not jeopardize the rest of the RAM's content.

At voltages below VPFD (min), the user can be as-

sured the memory will be in a write protected state,

provided the VCC f all time is not less than tF. The

M48T35/35Y may respond to transient noise

spikes on VCC that reach into t he deselect window

during the time the device is sampli ng VCC. There-

fore, decoupling of the power supply lines is rec-

ommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T35/35Y

for an accumulated period of at least 7 years when

VCC is less than VSO. As system power returns

and VCC rises above VSO, the battery is discon-

nected, and the power supply is swit ched to exter-

nal VCC. Write protection continues until VCC

reaches VPFD (min) plus tREC (min). E should be

kept high as V CC rises past VPFD (min) to prevent

inadvertent write cycles prior to processor stabili-

zation. Normal RAM operation can resume tREC

after VCC exceeds VPFD (max).

For more information on Battery Storage Life refer

to the Application Not e AN1012.

9/18

M48T35, M 48T35Y

Figure 7. Write Enable Controlled, Write AC Wavefo rm

Figure 8. Chip Enable Controlled, Write AC Waveforms

AI00926

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A14

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI00927

tAVAV

tEHAX

tDVEH

A0-A14

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

M48T35, M48T35Y

10/18

CLOCK OPERATIONS

Reading the Clock Updates to the TIMEKEEPER

registers should be halted before clock data is

read to prevent reading data in transition. Because

th e BiPORT T IM EKEEPER cell s i n th e R AM ar ra y

are only data registers, and not the actual clock

counters, updating the registers can be halted

without disturbing the clock itself.

Updating is halted when a ’1’ is written to the

READ bit, D6 in the Control Register 7FF8h. As

long as a ’1’ remains in that position, updating is

halted. After a halt is issued, the registers reflect

the coun t; that is, t he day, dat e, and t he t im e that

were current at the moment the halt command was

issued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second af ter the bit

is reset to a ’0’.

Setting the Clock

Bit D7 of the Control Register 7FF8h is the WRITE

bit. Setting the WRITE bit to a ’1’, like the READ

bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct day,

date, and time data in 24 hour BCD format (see

Table 11). Resetting the WRITE bit to a ’0’ then

transfers the values of all time registers 7FF9h-

7FFFh to the actual TIMEKEEPER counters and

allows normal operati on to resume.The FT bit and

the bits marked as ’0’ in Table 11 mus t be written

to ’0’ to allow fo r normal T IMEKEEPER and RAM

operation. After the WRITE bit is reset, the next

clock update will occur within one second.

See the Application Note AN923 "TIMEKEEPER

rolling into the 21st century" on the for information

on Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillat or can be turned off to

minimize current drain on the battery. The STOP

bit is the MSB of t he seconds regi ster. Setting it to

a ’1’ stops the oscillator. The M48T35/35Y is

shipped from STMicroelectronics with the STOP

bit set to a ’ 1’. When reset to a ’0’ , the M48T35/35Y

oscillator starts within 1 second.

Ca librat ing t he C lock

The M48T35/35Y is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not to exceed 35 ppm

(parts per million) oscillator frequency error at

25 °C, which equates to about ±1.53 minutes per

month. With the calibration bits properly set, the

accuracy of each M48T35 /35Y im proves to better

than ±4 ppm at 25 °C. The oscillation rate of any

crystal changes with temperature (see Figure 10).

Table 11. Register Ma p

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh 10 Years Year Year 00-99

7FFEh 0 0 0 10 M Month Month 01-12

7FFDh 0 0 10 Date Date: Day of Month Date 01-31

7FFCh 0 FT CEB CB 0 Day of Week Century/Day 00-01/01-07

7FFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

7FFA h 0 10 Minutes Minutes Minutes 00-59

7FF9h ST 10 Seconds Seconds Seconds 00-59

7FF8h W R S Calibration Control

Key s: S = Sign Bit

FT = Frequency Test Bit (M ust be se t t o ‘ 0’ upon power for normal operation)

R = Re ad Bit

W = Wri te Bit

ST = Stop Bit

0 = Must be set to ze ro

CEB = Century Enable Bit

CB = Century Bit

Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or fr om ‘1’ to ‘0’ at the turn of the century (depend ent upon the initial value set).

When CEB is set to ‘0’, CB will not toggle.

Th e WRITE Bi t does not need to be set to write to CEB and CB.

11/18

M48T35, M 48T35Y

Two methods are available for ascertaining how

much calibration a given M48T35/35Y may re-

quire. The first involves simply setting the clock,

letting it run for a month and comparing it to a

known accurate reference (like WWV broadcasts).

While that may seem crude, it al lows the designer

to give the end user the ability to calibrate his clock

as his environm ent may require, even after the fi-

nal product is packaged in a non-user serviceable

enclosure.

All the designer has to do is provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) bit, the sevent h-most s ignificant bit in the Day

ister is a ’0’ (Os cillator Running), DQ0 will toggle at

512Hz during a read of t he Sec onds Register. Any

deviation from 512 Hz indicates the degree and di-

rection of oscillator frequency shift at the test tem-

perature. For example, a reading of 512.01024 Hz

would indicate a +20 pp m oscillator frequen cy er-

ror, requiring a –10 (WR001010) to be l oaded into

the Calibration Byte for correction. Note that set-

ting or chang ing the Calibration Byte does not af-

fect the Frequency test output frequency.

The FT bit MUST be reset to '0' for normal clock

operations to resume. T he FT bit is automatically

Reset on power-up.

For more i nformation on cali bration, see the A ppli-

cation Note AN934 "TIMEKEEPER Calibration".

Most clock chips compensate for crystal frequency

and temperat ure shift error with cumb erso me trim

capacitors. The M48T35/35Y design, however,

employs pe riodic counter correction. The calibra-

tion circuit adds or subtrac ts counts from the oscil -

lator divider circuit at the divide by 256 stage, as

shown in Figure 9. The number of t imes pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five Calibration bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control Register 7FF8h. These

bits can be set to represent any value between 0

and 31 in binary f orm . Bit D5 is a Sign bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes i n t he cycle may , onc e

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minute s in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, e ach calibration step ha s the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibrat ion registe r. Ass um ing that

the oscillator is in fact running at exactly 32,768

Hz, each of the 31 increments in the Calibration

byte would represent +10.7 or –5.35 seconds per

month which corres ponds to a total range of +5. 5

or –2.75 minutes per month.

Figure 9. Clock Calibration

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T35, M48T35Y

12/18

POWER SUPPLY DECOUPLING an d

UNDERSHOOT PROT ECTION

ICC transients, i ncluding those produced by output

switching, can produce voltage fluctuations, re-

sulting in spi kes on the VCC bus. These transien ts

can be reduced if capacitors are used to store en-

ergy, which stabilizes the VCC bus. The energy

stored in the bypass c apaci tors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A bypass ca-

pacitor value of 0.1µF (as shown in Figure 11) is

recommended in order to provide the needed fil-

tering.

In addition to transients that are caused by normal

SRAM operation, power cy cling can generate neg-

ative voltage spikes on V CC that drive it to v alues

below VSS by as much as one V olt. These nega-

tive spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, it is recommended to con-

nect a schottky diode from VCC to VSS (cathode

connected to VCC, ano de to VSS). Schot tky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 10. Crysta l Accuracy Acro ss Temp eratur e

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T0)2 ± 10%

Fppm

T0 = 25 °C

Figure 11. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

13/18

M48T35, M 48T35Y

Table 12. Ordering Information Scheme

No te : 1. The M48T35 p art is offered with t he PCDI P28 (i.e. CAPHAT) pac kage onl y.

2. The SOIC pack age (SOH 28) req ui res the battery package (SNAPHAT) whi ch is ordered separat el y under the part num ber

"M4TXX-BR12SH 1" in plast i c t ube or "M4TXX- BR 12SH1TR" in Tape & Reel f orm.

3. Avail able in S OIC package only .

Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-cell bat-

tery.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

Example: M48T35Y -70 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

35 (1) = VCC = 4.75V to 5.5V; VPFD = 4.5V to 5.5V

35Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V

Speed

-70 = 70ns

Package

PC = PCDIP28

MH (2) = SOH28

Temperature Range

1 = 0 to 70 °C

6 (3) = –40 to 85 °C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Table 13. Revision History

Date Revision Details

November 1999 First Issue

02/07/00 tDR Description changed (Table 7)

M48T35, M48T35Y

14/18

Table 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380

A1 0.38 0.76 0.015 0.030

A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110

e3 29.72 36.32 1.170 1.430

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N 28 28

Figure 12. PCDIP28 - 28 pi n Plastic DIP, battery CAPHAT, Package Outline

Drawing is not to scale.

PCDIP

B1 B e1

15/18

M48T35, M 48T35Y

Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT,

Package Mechanical Dat a

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

Figure 13. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline

Drawing is not to scale.

SOH-A

LA1 α

M48T35, M48T35Y

16/18

Table 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Figure 14. M 4T 28-BR12SH SN AP HAT H o u si n g for 48 mAh Battery & Crystal, Package Outline

Drawing is not to scale.

SHTK

A1 A

17/18

M48T35, M 48T35Y

Table 17. M4T28-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Figure 15. M4T28-BR12SH SNAPHA T Housing for 120 m Ah Battery & Crystal, Package Outline

Drawing is not to scale.

SHTK

A1 A

M48T35, M48T35Y

18/18

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