REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes in accordance with NOR 5962-R185-97. - cs 97-02-24
Monica L. Poelking
B
Changes in accordance with NOR 5962-R439-97. – rc 97-08-18
Ray m ond Monnin
C Add AC tests at VDD = 10 V and 15 V and footnot e 4/ for those AC tests in table
I. Update boilerplat e to MIL-PRF-38535 requirements. Editorial changes
throughout. – jak
03-11-18
Thomas M. Hess
REV
SHEET
REV C C C C C C C C C C C C C C C C
SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
REV STA TUS REV C C C C C C C C C C C C C C
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Joseph A. Kerby
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Thanh V. Nguyen
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
95-10-13
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, CMOS, NOR GATE,
MONOLITHIC SILICON
AMSC N/A REVISION LEVEL
C SIZE
A CAGE CO DE
67268
5962-95826
SHEET
1 OF
30
DSCC FORM 2233
APR 97 5962-E434-03
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimit ed.
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2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 R 95826 01 V X C
Federal RHA Device Device Case Lead
stock class designator type class outline finish
designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 4000B Radiation hardened, CMOS, dual 3-input NOR gate
plus inverter
02 4001B Radiation hardened, CMOS, quad 2-input NOR gate
03 4002B Radiation hardened, CMOS, dual 4-input NOR gate
04 4025B Radiation hardened, CMOS, triple 3-input NOR gate
05 4001BN Radiation hardened, CMOS, quad 2-input NOR gate
with neutron irradiated die
06 4002BN Radiation hardened, CMOS, dual 4-input NOR gate
with neutron irradiated die
07 4025BN Radiation hardened, CMOS, triple 3-input NOR gate
with neutron irradiated die
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class Device requirements documentation
M Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q, V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
C CDIP2-T14 14 Dual-in-line
X CDFP3-F14 14 Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VDD).................................................................................. -0.5 V dc to +20 V dc
DC input voltage range (VIN)................................................................................ -0.5 V dc to VDD + 0.5 V dc
DC input current, any one input (IIN).................................................................... ±10 mA
Device dissipation per output transistor .............................................................. 100 mW
Storage temperature range (TSTG)....................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds) .......................................................... +265°C
Thermal resistance, junction-to-case (ΘJC):
Case outline C................................................................................................... 24°C/W
Case outline X................................................................................................... 30°C/W
Thermal resistance, junction-to-ambient (ΘJA):
Case outline C................................................................................................... 74°C/W
Case outline X................................................................................................... 116 °C/W
Junction temperature (TJ).................................................................................... +175°C
Maximum package power dissipation at TA = +125°C (PD): 4/
Case outline C................................................................................................... 0.68 W
Case outline X................................................................................................... 0.43 W
1.4 Recommended operating conditions.
Supply voltage range (VDD).................................................................................. +3.0 V dc to +18 V dc
Case operating temperature range (TC).............................................................. -55 °C to +125°C
Input voltage range (VIN)...................................................................................... +0.0 V to VDD
Output voltage range (VOUT)................................................................................ +0.0 V to VDD
Radiation features:
Total dose ......................................................................................................... 1 x 105 Rads (Si)
Single event phenomenon (SEP) effective
linear energy threshold (LET) no upsets (see 4.4.4.5).................................... > 75 MeV/(cm2/mg) 5/
Dose rate upset (20 ns pulse)........................................................................... > 5 x 108 Rads (Si)/s 5/
Dose rate latch-up............................................................................................. > 2 x 108 Rads (Si)/s 5/
Dose rate survivability....................................................................................... > 5 x 1011 Rads (Si)/s 5/
Neutron irradiated (device types 05, 06, and 07).............................................. > 1 x 1014 neutrons/cm2
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages are referenced to VSS.
3/ The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of
-55°C to +125°C unless otherwise noted.
4/ If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on
ΘJA) at the following rate:
Case outline C....................................................................................................... 13.5 mW/°C
Case outline X....................................................................................................... 8.6 mW/°C
5/ Guaranteed by design or process but not tested.
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APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in
the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth tables. The truth tables shall be as specified on figure 2.
3.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3.
3.2.5 Load circuit and switching waveforms. The load circuit and switching waveforms shall be as specified on figure 4.
3.2.6 Radiation test connections. The irradiation test connections shall be as specified in table III herein.
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APR 97
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 36 (see MIL-PRF-38535, appendix A).
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DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Limits
Unit
Test Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device
type
Group A
subgroups Min Max
1, 3 1/ 0.25 VDD = 5.0 V, VIN = 0.0 V or VDD 2 1/ 7.5
1, 3 1/ 0.5 VDD = 10 V, VIN = 0.0 V or VDD 2 1/ 1.5
1, 3 1/ 0.5 VDD = 15 V, VIN = 0.0 V or VDD 2 1/ 3.0
1 0.5 VDD = 20 V, VIN = 0.0 V or VDD 2 50.0
M, D, P, L, R 2/ 1 2.5
Supply current IDD
VDD = 18 V, VIN = 0.0 V or VDD
All
3 0.5
µA
1 0.53
2 1/ 0.36
VDD = 5.0 V, VIN = 0.0 V or VDD
VO = 0.4 V
3 1/ 0.64
1 1.4
2 1/ 0.9
VDD = 10 V, VIN = 0.0 V or VDD
VO = 0.5 V 3 1/ 1.6
1 3.5
2 1/ 2.4
Low level output
current (sink) IOL
VDD = 15 V, VIN = 0.0 V or VDD
VO = 1.5 V
All
3 1/ 4.2
mA
1 -0.53
2 1/ -0.36
VDD = 5.0 V, VIN = 0.0 V or VDD
VO = 4.6 V
3 1/ -0.64
1 -1.8
2 1/ -1.15
VDD = 5.0 V, VIN = 0.0 V or VDD
VO = 2.5 V
3 1/ -2.0
1 -1.4
2 1/ -0.9
VDD = 10 V, VIN = 0.0 V or VDD
VO = 9.5 V 3 1/ -1.6
1 -3.5
2 1/ -2.4
High level output
current (source) IOH
VDD = 15 V, VIN = 0.0 V or VDD
VO = 13.5 V
All
3 1/ -4.2
mA
See footnotes at end of table.
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DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics – Continued.
Limits Unit
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device
type
Group A
subgroups Min Max
VDD = 5 V, no load 1/ 1, 2, 3 4.95
VDD = 10 V, no load 1/ 1, 2, 3 9.95
Output voltage, high VOH
VDD = 15 V, no load 3/
All
1, 2, 3 14.95
VDD = 5 V, no load 1/ 1, 2, 3 0.05
VDD = 10 V, no load 1/ 1, 2, 3 0.05
Output voltage, low VOL
VDD = 15 V, no load
All
1, 2, 3 0.05
V
VDD = 5 V, VOH > 4.5 V, VOL < 0.5 V 1, 2, 3 1.5
VDD = 10 V, VOH > 9.0 V, VOL < 1.0 V 1/ 1, 2, 3 3.0
Input voltage, low VIL
VDD = 15 V, VOH > 13.5 V, VOL < 1.5 V
All
1, 2, 3 4.0
VDD = 5 V, VOH > 4.5 V, VOL < 0.5 V 1, 2, 3 3.5
VDD = 10 V, VOH > 9.0 V, VOL < 1.0 V 1/ 1, 2, 3 7.0
Input voltage, high VIH
VDD = 15 V, VOH > 13.5 V, VOL < 1.5 V
All
1, 2, 3 11.0
V
VIN = VDD or GND, VDD = 20 V 1 -100
VIN = VDD or GND, VDD = 20 V 2 -1000
Input leakage current,
low IIL
VIN = VDD or GND, VDD = 18 V 3 -100
VIN = VDD or GND, VDD = 20 V 1 100
VIN = VDD or GND, VDD = 20 V 2 1000
Input leakage current,
high IIH
VIN = VDD or GND, VDD = 18 V
All
3 100
nA
VDD = 10 V, ISS = -10 µA All 1 -0.7 -2.8
Negative threshold
voltage VNTH M, D, P, L, R 2/ All 1 -0.2 -2.8
V
Negative threshold
voltage, delta ∆VNTH VDD = 10 V, ISS = -10 µA
M, D, P, L, R 2/ All 1
±1.0 V
VSS = 0.0 V, IDD = 10 µA All 1 0.7 2.8
Positive threshold
voltage VPTH M, D, P, L, R 2/ All 1 0.2 2.8
V
Positive threshold
voltage, delta ∆VPTH VSS = 0.0 V, IDD = 10 µA
M, D, P, L, R 2/ All 1
±1.0 V
Input capacitance CIN
1/ Any input, See 4.4.1c All 4 7.5 pF
VDD = 2.8 V, VIN = VDD or GND 7
VDD = 20 V, VIN = VDD or GND 7
VDD = 18 V, VIN = VDD or GND 8A
M, D, P, L, R 2/ 7
VDD = 3.0 V, VIN = VDD or GND 8B
Functional tests
M, D, P, L, R 2/
All
7
VOH >
VDD/2 VOL <
VDD/2 V
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Limits Unit
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device
type
Group A
subgroups Min Max
9 250
VDD = 5 V, VIN = VDD or GND
10, 11 338
M, D, P, L, R 2/
All
9 338
ns
VDD = 10 V 1/ All 9 120 ns
Propagation delay time,
input to output tPHL,
tPLH
4/
VDD = 15 V 1/ All 9 90 ns
9 200 VDD = 5 V, VIN = VDD or GND All 10, 11 270 ns
VDD = 10 V 1/ All 9 100 ns
Transition time tTHL,
tTLH
4/ VDD = 15 V 1/ All 9 80 ns
1/ These tests are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which affect these characteristics.
2/ Devices supplied to this drawing meet all levels M, D, P, L, and R of irradiation. However, this device is only tested at the
"R" level. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
3/ For accuracy, voltage is measured differentially to VDD. Limit is 0.050 V max.
4/ CL = 50 pF, RL = 200 kΩ, input rise and fall times (tr, tf) < 20 ns.
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Device types 01 02 and 05 03 and 06 04 and 07
Case outlines C and X
Terminal number Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
NC
A
B
C
H = A+B+C
VSS
G
L = G
K = D+E+F
D
E
F
VDD
A
B
J = A+B
K = C+D
C
D
VSS
E
F
L = E+F
M = G+H
G
H
VDD
J = A+B+C+D
A
B
C
D
NC
VSS
NC
E
F
G
H
K = E+F+G+H
VDD
A
B
D
E
F
K = D+E+F
VSS
C
J = A+B+C
L = G+H+I
I
H
G
VDD
NC = No connection
FIGURE 1. Terminal connections.
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Device type 01
Inputs Outputs
A, D B, E C, F H, K
L L L H
H L L L
L H L L
H H L L
L L H L
H L H L
L H H L
H H H L
NOTE: Inverter not shown.
Device types 02 and 05
Inputs Outputs
A, D, E, and H B, C, F, and G J, K, L, and M
L L H
H L L
L H L
H H L
Device types 03 and 06
Inputs Outputs
A, H B, G C, F D, E J, K
L L L L H
H L L L L
L H L L L
H H L L L
L L H L L
H L H L L
L H H L L
H H H L L
L L L H L
H L L H L
L H L H L
H H L H L
L L H H L
H L H H L
L H H H L
H H H H L
Device types 04 and 07
Inputs Outputs
A, D, and I B, E, and H F, C, and G J, K, and L
L L L H
H L L L
L H L L
H H L L
L L H L
H L H L
L H H L
H H H L
FIGURE 2 Truth tables.
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FIGURE 3. Logic diagrams.
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FIGURE 3. Logic diagrams – Continued.
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FIGURE 4. Load circuit and switching waveforms.
STANDARD
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B or as modified in the device manufacturer’s Quality Management (QM) plan.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535, including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth tables in figure 2. For device classes
Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c. Subgroup 4 (CIN measurement) shall be measured only for initial qualification and after process or design changes
which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of
1 MHz. Tests shall be sufficient to validate the limits defined in table I herein.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
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TABLE IIA. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883, method
5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device class M Device class Q Device class V
Interim electrical
parameters (see 4.2)
1, 7, 9
1, 7, 9
1, 7, 9
Final electrical
parameters (see 4.2)
1, 2, 3, 7, 8, 9, 10, 11
1/
1, 2, 3, 7, 8, 9, 10, 11
1/
1, 2, 3, 7, 8, 9, 10, 11
2/ 3/
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7, 8, 9, 10, 11
1, 2, 3, 4, 7, 8, 9, 10, 11
1, 2, 3, 4, 7, 8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11 3/
Group D end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroups 1 and 7.
2/ PDA applies to subgroups 1, 7, 9, and deltas.
3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta
limits shall be completed with reference to the zero hour electrical parameters (see table I).
TABLE IIB. Burn-in and operating life test, Delta parameters (+25°C).
Parameters Symbol Delta limits
Supply current IDD ± 0.1 µA
Output current (sink), VDD = 5.0 V IOL ± 20%
Output current (source)
VDD = 5.0 V, VOUT = 4.6 V
IOH ± 20%
TABLE III. Irradiation test connections 1/.
Device types Open Ground VDD = 10.0 V ± 0.5 V
01
1, 2, 6, 9, 10 7 3, 4, 5, 8, 11, 12, 13, 14
02, 05
3, 4, 10, 11 7
1, 2, 5, 6, 8, 9, 12, 13, 14
03, 06
1, 6, 8, 13 7
2, 3, 4, 5, 9, 10, 11, 12, 14
04, 07 6, 9, 10 7 1, 2, 3, 4, 5, 8, 11, 12, 13, 14
1/ Each pin except VDD and GND will have a resistor of 47 kΩ ± 5% for irradiation testing.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method
1005 of MIL-STD-883.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein.
c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883,
method 1019, and as specified herein.
4.4.4.1.1 Accelerated aging testing. Accelerated aging testing shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall
be the pre-irradiation end-point electrical parameter limits at 25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron irradiation. Neutron irradiation for devices 05, 06, and 07 shall be conducted in wafer form using a neutron
fluence of approximately 1x1014 neutrons/cm2.
4.4.4.3 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test
method 1020 of MIL-STD-883 and as specified herein (see 1.4 herein). Tests shall be performed on devices, SEC, or approved
test structures at technology qualification and after any design or process changes that may affect the RHA capability of the
process.
4.4.4.4 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of
MIL-STD-883 and herein (see 1.4 herein).
a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
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4.4.4.5 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.4 herein). SEP testing shall
be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by
the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup
characteristics. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 106 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates that differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 microns in silicon.
e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for the latchup measurements.
g. Test four devices with zero failures.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Mi crocircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
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6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from
the device manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microc ircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962 R 95826 01 V 9 A
Federal RHA Device Device Die Die
Stock class designator type class code Details
designator (see A.1.2.1) (see A.1.2.2) designator (see A.1.2.4)
(see A.1.2.3)
Drawing Number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels.
A dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type Generic number Circuit function
01 4000B Radiation hardened, CMOS, dual 3-input NOR gate
plus inverter
02 4001B Radiation hardened, CMOS, quad 2-input NOR gate
03 4002B Radiation hardened, CMOS, dual 4-input NOR gate
04 4025B Radiation hardened, CMOS, triple 3-input NOR gate
05 4001BN Radiation hardened, CMOS, quad 2-input NOR gate
with neutron irradiated die
06 4002BN Radiation hardened, CMOS, dual 4-input NOR gate
with neutron irradiated die
07 4025BN Radiation hardened, CMOS, triple 3-input NOR gate
with neutron irradiated die.
A.1.2.3 Device class designator.
Device class Device requirements documentation
Q or V Certification and qualification to the die requirements of MIL-PRF-38535.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die types Figure number
01 A-1
02, 05 A-2
03, 06 A-3
04, 07 A-4
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die types Figure number
01 A-1
02, 05 A-2
03, 06 A-3
04, 07 A-4
A.1.2.4.3 Interface materials.
Die types Figure number
01 A-1
02, 05 A-2
03, 06 A-3
04, 07 A-4
A.1.2.4.4 Assembly related information.
Die types Figure number
01 A-1
02, 05 A-2
03, 06 A-3
04, 07 A-4
A.1.3 Absolute maximum ratings. See paragraph 1.3 for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 for details.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
A.2 APPLICABLE DOCUMENTS
A.2.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following
specifications, standard, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications
and Standards specified in the solicitation, form a part of this drawing to the extent specified herein.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARD
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
HANDBOOK
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
(Copies of the specification, standard, and handbook required by manufacturers in connection with specific acquisition
functions should be obtained from the contracting activity or as directed by the contracting activity).
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figures A-1, A-2,
A-3, and A-4.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in A.1.2.4.2 and on figures A-1, A-2, A-3, and A-4.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figures A-1, A-2,
A-3, and A-4.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figures A-1,
A-2, A-3, and A-4.
A.3.2.5 Truth tables. The truth tables shall be as defined in paragraph 3.2.3 herein
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in A.1.2 herein. The certification mark shall be a “QM” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 QUALITY ASSURANCE PROVISIONS
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in
accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The
modifications in the QM plan shall not affect the form, fit or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, test method 5007.
b) 100% wafer probe (see paragraph A.3.4 herein).
c) 100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, test method
2010 or the alternate procedures allowed in MIL-STD-883, test method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured
(see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing
of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraph 4.4.4
herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan
or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined with
MIL-PRF-38535 and MIL-STD-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA
and have agreed to this drawing.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o DIE PHYSICAL DIMENSIONS
Die size: 1397 x 1727 microns.
Die thickness: 20 ± 1 mils.
o DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
NOTE: Pad numbers reflect terminal numbers when placed in case outlines C, X (see figure 1).
FIGURE A-1
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o INTERFACE MATERIALS
Top metallization: Al 11.0kÅ - 14.0kÅ
Backside metallization: None.
Glassivation
Type: PSG
Thickness: 10.4kÅ - 15.6kÅ
Substrate: Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate potential: Floating or tied to VDD.
Special assembly
instructions: Bond pad #14 (VDD) first.
FIGURE A-1 – Continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o DIE PHYSICAL DIMENSIONS
Die size: 1397 x 1727 microns.
Die thickness: 20 ± 1 mils.
o DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
NOTE: Pad numbers reflect terminal numbers when placed in case outlines C, X (see figure 1).
FIGURE A-2
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o INTERFACE MATERIALS
Top metallization: Al 11.0kÅ - 14.0kÅ
Backside metallization: None.
Glassivation
Type: PSG
Thickness: 10.4kÅ - 15.6kÅ
Substrate: Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate potential: Floating or tied to VDD.
Special assembly
instructions: Bond pad #14 (VDD) first.
FIGURE A-2 – Continued.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o DIE PHYSICAL DIMENSIONS
Die size: 1397 x 1727 microns.
Die thickness: 20 ± 1 mils.
o DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
NOTE: Pad numbers reflect terminal numbers when placed in case outlines C, X (see figure 1).
FIGURE A-3
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o INTERFACE MATERIALS
Top metallization: Al 11.0kÅ - 14.0kÅ
Backside metallization: None.
Glassivation
Type: PSG
Thickness: 10.4kÅ - 15.6kÅ
Substrate: Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate potential: Floating or tied to VDD.
Special assembly
instructions: Bond pad #14 (VDD) first.
FIGURE A-3 – Continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o DIE PHYSICAL DIMENSIONS
Die size: 1524 x 1753 microns.
Die thickness: 20 ± 1 mils.
o DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
NOTE: Pad numbers reflect terminal numbers when placed in case outlines C, X (see figure 1).
FIGURE A-4
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95826
o INTERFACE MATERIALS
Top metallization: Al 11.0kÅ - 14.0kÅ
Backside metallization: None.
Glassivation
Type: PSG
Thickness: 10.4kÅ - 15.6kÅ
Substrate: Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate potential: Floating or tied to VDD.
Special assembly
instructions: Bond pad #14 (VDD) first.
FIGURE A-4 – Continued.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 03-11-18
Approved sources of supply for SMD 5962-95826 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R9582601VCC 3/ CD4000BDMSR
5962R9582601VXC 3/ CD4000BKMSR
5962R9582601V9A 3/ CD4000BHSR
5962R9582602VCC 34371 CD4001BDMSR
5962R9582602VXC 34371 CD4001BKMSR
5962R9582602V9A 34371 CD4001BHSR
5962R9582603VCC 3/ CD4002BDMSR
5962R9582603VXC 3/ CD4002BKMSR
5962R9582603V9A 3/ CD4002BHSR
5962R9582604VCC 34371 CD4025BDMSR
5962R9582604VXC 34371 CD4025BKMSR
5962R9582604V9A 3/ CD4025BHSR
5962R9582605VCC 3/ CD4001BDNSR
5962R9582605VXC 34371 CD4001BKNSR
5962R9582605V9A 3/ CD4001BHNSR
5962R9582606VCC 3/ CD4002BDNSR
5962R9582606VXC 3/ CD4002BKNSR
5962R9582606V9A 3/ CD4002BHNSR
5962R9582607VCC 3/ CD4025BDNSR
5962R9582607VXC 3/ CD4025BKNSR
5962R9582607V9A 3/ CD4025BHNSR
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ No longer available from an approved source of supply.
Vendor CAGE Vendor name
number and address
34371 Intersil Corporation
2401 Palm Bay Blvd.
P.O. Box 883
Melbourne, FL 32902-0883
The information contained herein is disseminated for convenience only and
the Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
