9FGV1005 PhiClockTM Evaluation Board User Guide Introduction The evaluation board is designed to help the customer evaluate the 9FGV1005 device. When the board is connected to a PC running IDT Timing CommanderTM software through USB, the device can be configured and programmed to generate different combinations of frequencies. Board Overview Use Figure 1 and Table 1 to identify: power supply jacks, USB connector, input and output frequency SMA connectors. Figure 1. Evaluation Board Overview 10 9 8 7 6 11 12 1 (c)2018 Integrated Device Technology, Inc. 2 1 3 4 5 February 28, 2018 9FGV1005 PhiClockTM Evaluation Board User Guide Table 1. Evaluation Board Pins and Functions Label Number Name On-board Connector Label 1 I2C Interface Connector J2 Function Alternative I2C interface connector for Aardvark. IDT Timing Commander can also use Aardvark. 2 USB Connector J6 Connect this USB to your PC to run IDT Timing Commander. The board can be powered from the USB port. 3 Output Power Supply Jack J3 Connect to 1.8V, 2.5V or 3.3V for the output voltage of the device. 4 Core Power Supply Jack J4 Connect to 1.8V, 2.5V or 3.3V for the core voltage of the device. 5 Ground Jack J5 Connect to ground of power supply. 6 Differential Output 0 S3 and S4 Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. 7 Differential Output 1 S7 and S10 Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. VDD_REFP1, VDDO_0, VDDO_1, four-way headers used to select a power supply voltage. Connect the center pin to one of the 4 surrounding pins to select a voltage or a source. 8 Power Supply Voltage Selector E1, E2, E3 9 Power Supply Voltage Selector E4 VDDA0, four-way headers used to select a power supply voltage. Connect the center pin to one of the 4 surrounding pins to select a voltage or a source. 10 Reference Output 0 S1 Reference or buffered output from the crystal. I2C bus enable access registers. 11 SEL_I2C# JP3 12 SCL, SDA/SEL0, SEL1 JP1, JP2 OTP bank CFG0 used to initialize RAM configuration registers. OTP bank CFG used to initialize RAM configuration registers. Board Power Supply The evaluation board uses jumpers E1-E4 to set the power supply voltages for various VDD pins. The 4-way jumpers can select 3 different voltages from regulators that use power from the USB port. Selection #2 is the jack for connecting a bench power supply. E1: Power supply for the REF outputs. The E1 voltage also determines the LVCMOS output levels of the REF0 and REF1 outputs. E2: Power supply for the OUT0 output driver. E3: Power supply for the OUT1 output driver. E4: Power supply for the analog (VDDA) and digital (VDDD) core VDD pins. See 9FGV1005 Evaluation Board Schematics (Figure 4-Figure 7) for detailed information. (c)2018 Integrated Device Technology, Inc. 2 February 28, 2018 9FGV1005 PhiClockTM Evaluation Board User Guide Interfacing with a Computer to Run Timing Commander As shown in Figure 2, jumpers JP1 and JP2 are installed to use the FTDI chip U6 for connecting to the computer with the USB port J6. The U6 chip translates USB to I2C. When using Aardvark, remove jumpers JP1 and JP2 and connect the Aardvark to connector J2. Default I2C device address for the 9FGV1005 is 0x68. Miscellaneous interfaces can connect to J2 pin 1 for the Serial Clock and to J2 pin 3 for the Serial Data signal. J2 pin 2 can be used as ground, but any other ground pin will also work. When OTP in the 9FGV1005 devices is burned with multiple configurations, JP1 and JP2 can be applied in JP3 position respectively. Connect JP3 (SEL_I2C#) to VDDO and power-up the 9FGV1005 in Hardware Select mode and SEL0/1. This enables changing between 4 configurations. Figure 2. Connecting to a Computer via USB Port J6 On-board Crystal A 25MHz crystal is installed on the board and is used as the reference frequency. The board can also be modified to insert an external reference clock into the XIN pin using SMA connector S11. When using an external reference clock, additional components need to be assembled and the crystal needs to be removed. Output Terminations Each differential output has a pair of SMA connectors to connect to a 50 coax. It is recommended to combine the two signals using a balun or splitter/combiner device when measuring jitter or phase noise. The circuit at the SMA connectors is shown in Figure 3. (c)2018 Integrated Device Technology, Inc. 3 February 28, 2018 9FGV1005 PhiClockTM Evaluation Board User Guide Figure 3. SMA Connectors Circuit The circuit is designed for maximum flexibility when testing all possible logic types. Default assembly uses a 0.1F capacitor in place of R14 and R16, and the short across R14 and R16 is cut. No other devices are assembled. This simple AC-coupled configuration allows for testing phase noise and jitter of all possible logic types. The circuit can be modified for custom tests. TP3 is a position to place a differential FET probe. Operating Instructions 1. Set all jumpers for power supply choices (E1-E4), interface choices (JP1 and JP2), and set the U2 switches. 2. Connect an interface: USB or I2C. 3. In the case of an I2C interface, also connect external power supply to jacks J3, J4 and J5. 4. Start Timing Commander for either USB or Aardvark. a. Start new configuration or load TCS file for existing configuration. b. Choose PhiClock personality. c. For Aardvark, click to select Aardvark "Connection Interface". d. For a new configuration, prepare all settings. e. Click f. Click to connect to the 9FGV1005 device. Top right should turn green. to write all settings to the 9FGV1005 device. g. It should now be possible to measure clocks on outputs. h. While connected, each change to the settings will be written to the 9FGV1005 immediately and can be observed at the clock outputs. (c)2018 Integrated Device Technology, Inc. 4 February 28, 2018 A B C GND C60 10uF J1 HEADER 2 {2} SEL0_SCL SEL0_SCL SEL1_SDA OTP_VPP 5 OUT0C SE Trace 5 inches/50ohm Support LVCMOS/PCIEX/LVDS OUT0T SE Trace 5 inches/50ohm 10 3 4 6 15 1 XIN_CLKIN REF0 2 XO 1 R4 33 2 {2} SEL1_SDA vREF0_SEL_I2CB C61 0.1uF XO {2} XIN_CLKIN {2} cut-able trace option: 1) Use SMA: don't cut; no load cap 2) No SMA: cut VDDDp 1 2 D 4 U9 NC ^SEL0/SCL ^SEL1/SDA OTP_VPP vREF0_SEL_I2CB XIN/CLKIN XO EPAD1 2 5 1 1 2pF 2 C4 1 C3 2pF CM0 50_NP R55 2 R54 50_NP GND 17 EPAD2 18 EPAD3 19 EPAD4 20 R16 0_NP 1 50_NP 0_NP R14 2 R15 14 VDDO0 GND S4 1 S3 1 0 R9 2 1 1 1 1 GND 3 4 5 5 4 3 4 2 OUT0T 3 OUT0C IO4 GND3 IO2 GND1 TP3 GND 3 1 OUT1C SE Trace 5 inches/50ohm OUT1T SE Trace 5 inches/50ohm 10K 2pF 2 1 C10 2pF 2 1 CM1 50_NP R57 2 1 1 C7 5pF C1 2 R56 50_NP 2 vREF0_SEL_I2CB vREF0_SEL_I2CB_SW 1 R2 SE Trace 5 inches/50ohm OUT1C VDDO1 VDDO0 OUT1T OUT0C OUT0T VDDREFp {2} vREF0_SEL_I2CB_SW GND OUT1B 11 0 R8 2 VDDO1 OUT1 0 OUT0B R6 2 7 13 12 0 VDDDp VDDAp R5 2 OUT0 9 8 VDDREF VDDD VDDA 16 5 9FGV1005_LTG16 OUT1# OUT1 VDDO1 OUT0# OUT0 VDDO0 VDDREF VDDD VDDA 3 2 2 2 IO GND R25 0_NP R22 1 50_NP 0_NP R19 1 2 R1 0_NP 1 GND Date: Size B Title S10 1 GND 3 4 5 4 2 OUT1T OUT1C IO4 GND3 IO2 GND1 TP4 GND 3 1 Thursday, December 22, 2016 Document Number EVB 9FGV1005 REV A 3 4 5 5 4 3 GND 2 GND S1 S7 1 REF0 TP1 cut-able trace 1 9FGV1005 2 2 2 4 1 1 2 2 1 1 2 2 2 2 (c)2018 Integrated Device Technology, Inc. 1 2 2 1 1 2 5 1 Sheet 1 1 of 4 Rev 1 A B C D 9FGV1005 PhiClockTM Evaluation Board User Guide Schematics Figure 4. 9FGV1005 Evaluation Board Schematic - page 1 February 28, 2018 A B C D S11 GND 3 1 1 4 R26 0_NP XINRCONN SMA STRAIGHT cut-able trace R29 1 XO 25MHz GND ESR GND X1 50_NP 2 {1} 100pF_NP C13 2 1 6 cut trace if LD1 populated A) USB_I2C or AARDVARK set JP1[1:2], JP2 [1:2] set J3[2:3] opt 1) USB_I2C: populate R33, R32 for SCL/SDA pull up opt 2) AARDVARK_I2C 2.1. Aardvark internal pullup populate R30,R31, no R32,R33 2.2. No internal Aardvark pull up polulate R30,R31,R32,R33 B) User I2C with pull up board set JP3[2:3] use pin2 JP1 as SCK use pin2 JP2 as SDA 5 {1} 4 XIN_CLKIN_X1 XIN_CLKIN Unpopulate C13 when Crystal is used as input reference 3 4 5 GND 2 2 1 2 1K R33 SDA_pUp LD1 Green 1K R32 VDDDp LABEL: REF0_SELI2C# 1 2 1 2 4 JP3 {2,4} 2 2 SCL {2,4} 0 R31 1 0 R30 1 GND JP1 JP2 SCL_pUp 1 2 3 VDDDp SDA_pUp SDA GND VDDD Update silk screen JP3 3 GND JP1_pdwn GND JP2_pdwn HW SEL1 3 1 R27 R28 1 10K 10K GND 2 GND SEL1_SDA 2 SEL0_SCL {1} {1} 2 4 6 8 10 GND AARDVARK_I2C {1} HEADER 5X2 label: A_SCL 1 3 label: A_SDA 5 7 9 J2 vREF0_SEL_I2CB_SW HW SEL0 1 2 3 (c)2018 Integrated Device Technology, Inc. 1 2 3 5 2 2 Date: Size B Title EVB 9FGV1005 REV A Thursday, December 22, 2016 Document Number 1 Sheet 1 2 of 4 Rev 1 A B C D 9FGV1005 PhiClockTM Evaluation Board User Guide Figure 5. 9FGV1005 Evaluation Board Schematic - page 2 February 28, 2018 A B C D GND C38 10uF USB_5V USB_5V Power Jack Black J5 Power Jack Red 1 2 3 GND 0.1uF C46 5 C47 10uF USB_5V 0.01uF 6 5 REG_CP3 4 USB_5V GND(CP) EN CP IN IN IN(CP) OUT OUT C21 0.1uF GND FB SET OUT(FB) GND GND GND U3 LP38789 {3,4} GND1 GND2 10uF 0.1uF GND C20 C19 1 VDD_J GND_J VDD_J C37 1 2 1 2 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 2 1 2 3 6 5 GND(CP) EN CP IN IN IN(CP) U5 LP38789 R36 21K_1% REG_CP5 4 GND 1 13 14 15 16 17 18 19 20 21 7 8 9 10 12 11 GND FB SET OUT(FB) GND R40 1 2 2 1 4 R34 1 23.2K_1% 2 R66 10uF C39 4 FB2 R67 1K_NP REG_D5 GND VDDO_3.3V GND C40 REG_CP4 10uF C48 0.01uF C41 10uF USB_5V 0.1uF GND 0.1uF C27 VDDDp GND 0.1uF C24 VDDAp GND(CP) EN CP IN IN IN(CP) U4 LP38789 GND FB SET OUT(FB) OUT OUT Locate near DUT power pin GND 6 5 4 1 2 3 10uF C26 BLM18AG601SN1D C25 FB3 10uF C23 0.1uF BLM18AG601SN1D C22 2.2 2 R31_C31 VDDA_VDDD GND R63 1K_NP R39 4 VDDO_2.5V VDDA_p REG_D3 REG_SET5 13.3K_1% 7 8 9 10 12 11 R62 E4 10.5K_1% R35 REG_SET3 OUT OUT 2 1 HEADER 2 J7 VDDO_1.8V VDDO_3.3V 5 2 VDDO_1.8V3 1 2 2 1 2 R32_C45 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 13 14 15 16 17 18 19 20 21 3 1 2 1 1 2 1 2 J4 R36_C56 1 2 1 2 1 VDDAP_VDDDP1 2 15K_1% 1 R38 7 8 9 10 12 11 J3 3 VDDO_J 16.2K_1% R37 REG_SET4 2 R64 GND VDDO_2.5V Power Jack Red 3 R33_C48 2 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 13 14 15 16 17 18 19 20 21 POT_25K_NP 1 2 3 1 2 1 7 POT_25K_NP 1 2 R65 1K_NP REG_D4 GND 10uF C42 C14 0.1uF POT_25K_NP C15 10uF 1 5 E3 1 1 2 1 VDDO_2.5V VDDO_2.5V VDDO_2.5V Date: Size B Title C16 0.1uF Thursday, December 22, 2016 Document Number EVB 9FGV1005 REV A GND C31 0.1uF C32 10uF C29 10uF C17 10uF GND GND GND 1 Sheet 3 of Locate near DUT power pin BLM18AG601SN1D VDDO_1 FB5 C28 0.1uF VDDO_2 GND FB4 BLM18AG601SN1D VDDO_0 VDDO_1 GND FB1 BLM18AG601SN1D VDD_REFp VDD_REFP1 LABEL ON EACH RESPECTIVE PIN OF HEADERS: 1.8V, 2.5V, 3.3V Header Alignment: Single pin header above and below the center pin of 3-pin header so that center pin can be jumped with the surrounding 4 pins, shown as left 4 2 VDDO_3.3V 5 VDDO_J VDDO_1.8V 3 4 2 VDDO_3.3V 5 VDDO_J VDDO_1.8V3 VDDO_3.3V 4 E2 E1 2 VDDO_1.8V 3 VDDO_J 2 1 2 1 2 3 1 2 1 1 1 2 1 2 1 2 1 2 (c)2018 Integrated Device Technology, Inc. 2 5 4 C33 0.1uF Rev 1 VDDO1 C30 0.1uF VDDO0 C18 0.1uF VDDREFp A B C D 9FGV1005 PhiClockTM Evaluation Board User Guide Figure 6. 9FGV1005 Evaluation Board Schematic - page 3 February 28, 2018 A B C D {3} TP24 GND USB_5V 1 GND 2 USB_6 3 5 GND USB_7 USB_5 2 4 USB_4 1 USB PORT GND D+ D- VBUS J6 C53 47uF C805A R41 1 0 2 C52 27 R45 GND 1.5K USB_3 33pF GND 4 VCC2232 GND 10K USB_8 47 2 1 48 4 R50 44 VCC2232 43 5 7 8 6 TEST EEDATA EESK EECS RESET# XTOUT XTIN RSTOUT# USBDP USBDM 3V3OUT U6 0.1uF C56 470 USB_15 FB9 BLM18AG601SN1D R43 XTOUT 0.047uF C57 3V3_USB VCC2232_3V USB_2 XTIN C59 LD2 Green GND Y1 6MHz 2 4 USB_13 R42 1K USB_1 0.1uF 2 10uF R48 C55 1 33pF C58 1 R44 27 300ohm 2A FB10 USB_14 mod1: connect C55 p1 to C52 p1 USB_12 300ohm 2A FB8 1 USB_11 2 1 2 TP23 1 2 1 2 1 2 1 2 TP23: Label TP23 / 5V INPUT R41: provide USB 5 V to Regulators 1 2 1 2 1 2 3 42 VCC VCC GND 24 23 22 21 20 19 17 16 41 26 30 29 28 27 40 39 38 37 36 35 33 32 10 15 13 12 11 3V3_USB0 1 R49 3V3_USB1 1 10K R51 10K 2 3V3_USB 2 1 USB_10 R47 R46 1 USB_9 3 2 On Layout, make EPAD to easy connect to GND FT2232_LQFP48 PWREN# SI/WUB UNUSED8 UNUSED9 UNUSED10 UNUSED11 UNUSED0 UNUSED1 UNUSED2 UNUSED3 UNUSED4 UNUSED5 UNUSED6 UNUSED7 SI/WUA GPIOH0 GPIOH1 GPIOH2 GPIOH3 TCK/SK TDI/DO TDO/DI TMS/CS GPIOL0 GPIOL1 GPIOL2 GPIOL3 3V3_USB 0 2 0 2 Title SCL {2} Date: Size B Thursday, December 22, 2016 Document Number 1 Sheet NS/MOUNTING HOLE MTH#6_4 EVB 9FGV1005 REV A SDA {2} 10uF C54 NS/MOUNTING HOLE MTH#6_3 GND NS/MOUNTING HOLE 0.1uF MTH#6_2 NS/MOUNTING HOLE MTH#6_1 1 C51 2 2 0.1uF 2 1 3 C50 1 14 31 VCCIOA VCCIOB 46 AVCC AGND GND GND GND GND 45 9 18 25 34 8 EPAD1 EPAD2 EPAD3 EPAD4 (c)2018 Integrated Device Technology, Inc. 49 50 51 52 5 4 of LOGO_IDT1 IDT FIDUCIAL 4 FID3 Fiducial FIDUCIAL FID2 Fiducial FIDUCIAL FID1 Fiducial Rev 1 A B C D 9FGV1005 PhiClockTM Evaluation Board User Guide Figure 7. 9FGV1005 Evaluation Board Schematic - page 4 February 28, 2018 9FGV1005 PhiClockTM Evaluation Board User Guide Ordering Information Orderable Part Number Description EVK9FGV1005 Evaluation board with all differential outputs AC coupled. Revision History Revision Date Description of Change February 28, 2018 Updated numbering and labeling in Evaluation Board Pins and Functions table and Evaluation Board Overview diagram. November 28, 2017 Initial release. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved. 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