1©2018 Integrated Device Technology, Inc. February 28, 2018
Introduction
The evaluation board is designed to help the customer evaluate the 9FGV1005 device. When the board is connected to a PC running IDT
Timing Commander™ software through USB, the device can be configured and programmed to generate different combinations of
frequencies.
Board Overview
Use Figure 1 and Table 1 to identify: power supply jacks, USB connector, input and output frequency SMA connectors.
Figure 1. Evaluation Board Overview
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9FGV1005 PhiClock™ Evaluation Board User Guide
2©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Board Power Supply
The evaluation board uses jumpers E1–E4 to set the power supply voltages for various VDD pins. The 4-way jumpers can select 3
different voltages from regulators that use power from the USB port. Selection #2 is the jack for connecting a bench power supply.
E1: Power supply for the REF outputs. The E1 voltage also determines the LVCMOS output levels of the REF0 and REF1 outputs.
E2: Power supply for the OUT0 output driver.
E3: Power supply for the OUT1 output driver.
E4: Power supply for the analog (VDDA) and digital (VDDD) core VDD pins.
See 9FGV1005 Ev aluatio n Board Sche matics (Figure 4–Figure 7) for detailed information.
Table 1. Evaluation Board Pins and Functions
Label Number Name On-board Connector Label Function
1I
2C Interface Connector J2 Alternative I2C interface connector for Aardvark.
IDT Timing Commander can also use Aardvark.
2 USB Connector J6
Connect this USB to your PC to run IDT Timing
Commander.
The board can be powered from the USB port.
3 Output Power Supply Jack J3 Connect to 1.8V, 2.5V or 3.3V for the output voltage of
the device.
4 Core Power Supply Jack J4 Connect to 1.8V, 2.5V or 3.3V for the core voltage of the
device.
5 Ground Jack J5 Connect to ground of power supply.
6 Differential Output 0 S3 and S4 Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
7 Differential Output 1 S7 and S10 Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
8Power Supply Voltage
Selector E1, E2, E3
VDD_REFP1, VDDO_0, VDDO_1, four-way headers
used to select a power supply voltage. Connect the
center pin to one of the 4 surrounding pins to select a
voltage or a source.
9Power Supply Voltage
Selector E4
VDDA0, four-way headers used to select a power supply
voltage. Connect the center pin to one of the 4
surrounding pins to select a voltage or a source.
10 Reference Output 0 S1 Reference or buffered output from the crystal.
11 SEL_I2C# JP3
I2C bus enable access registers.
OTP bank CFG0 used to initialize RAM configuration
registers.
12 SCL, SDA/SEL0, SEL1 JP1, JP2 OTP bank CFG used to initialize RAM configuration
registers.
3©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Interfacing with a Computer to Run Timing Commander
As shown in Figure 2, jumpers JP1 and JP2 are installed to use the FTDI chip U6 for connecting to the computer with the USB port J6.
The U6 chip translates USB to I2C.
When using Aardvark, remove jumpers JP1 and JP2 and connect the Aardvark to connector J2. Default I2C device address for the
9FGV1005 is 0x68.
Miscellaneous interfaces can connect to J2 pin 1 for the Serial Clock and to J2 pin 3 for the Serial Data signal. J2 pin 2 can be used as
ground, but any other ground pin will also work.
When OTP in the 9FGV1005 devices is burned with multiple configurations, JP1 and JP2 can be applied in JP3 position respectively.
Connect JP3 (SEL_I2C#) to VDDO and power-up the 9FGV1005 in Hardware Select mode and SEL0/1. This enables changing between
4 configurations.
Figure 2. Connecting to a Computer via USB Port J6
On-board Crystal
A 25MHz crystal is installed on the board and is used as the reference frequency. The board can also be modified to insert an external
reference clock into the XIN pin using SMA connector S11. When using an external reference clock, additional components need to be
assembled and the crystal needs to be removed.
Output Terminations
Each differential output has a pair of SMA connectors to connect to a 50Ω coax. It is recommended to combine the two signals using a
balun or splitter/combiner device when measuring jitter or phase noise. The circuit at the SMA connectors is shown in Figure 3.
4©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Figure 3. SMA Connectors Circuit
The circuit is designed for maximum flexibility when testing all possible logic types. Default assembly uses a 0.1μF capacitor in place of
R14 and R16, and the short across R14 and R16 is cut. No other devices are assembled. This simple AC-coupled configuration allows for
testing phase noise and jitter of all possible logic types. The circuit can be modified for custom tests. TP3 is a position to place a
differential FET probe.
Operating Instructions
1. Set all jumpers for power supply choices (E1–E4), interface choices (JP1 and JP2), and set the U2 switches.
2. Connect an interface: USB or I2C.
3. In the case of an I2C interface, also connect external power supply to jacks J3, J4 and J5.
4. Start Timing Commander for either USB or Aardvark.
a. Start new configuration or load TCS file for existing configuration.
b. Choose PhiClock personality.
c. For Aardvark, click to select Aardvark “Connection Interface”.
d. For a new configuration, prepare all settings.
e. Click to connect to the 9FGV1005 device. Top right should turn green.
f. Click to write all settings to the 9FGV1005 device.
g. It should now be possible to measure clocks on outputs.
h. While connected, each change to the settings will be written to the 9FGV1005 immediately and can be observed at the clock outputs.
5©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Schematics
Figure 4. 9FGV1005 Eva luation Board Schematic – page 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
9FGV1005
SE Trace 5 inches/50ohm
SE Trace 5 inches/50ohm
SE Trace 5 inches/50ohm
SE Trace 5 inches/50ohm
SE Trace 5 inches/50ohm
Support LVCMOS/PCIEX/LVDS
cut-able trace
cut-able trace option:
1) Use SMA: don't cut; no load cap
2) No SMA: cut
OUT0T
OUT0C
OUT1T
OUT1C
REF0
VDDAp
VDDO1
VDDO0
VDDREFp
GND
VDDDp
GND
VDDDp
GND
GND
GND
GND
GND
GND
GND
GND
GND
XO
{2}
XIN_CLKIN
{2}
SEL1_SDA{2}
SEL0_SCL
{2}
vREF0_SEL_I2CB_SW{2}
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TP4
IO2
2IO4
4
GND1 1
GND3 3
C61
0.1uF
12
U9
9FGV1005_LTG16
^SEL0/SCL
3
XIN/CLKIN
1
XO
2
OTP_VPP
6
VDDD 5
^SEL1/SDA
4
VDDA 14
VDDREF 16
vREF0_SEL_I2CB
15
NC
10
VDDO1 13
OUT1 12
OUT1# 11
OUT0# 7
OUT0 8
VDDO0 9
EPAD1
17
EPAD2
18
EPAD3
19
EPAD4
20
R8 0
12
C60
10uF
1
2
C3
2pF
R5 0
12
R54
50_NP
12
1
2
R1
0_NP
1
2
C1
5pF
S7
1
2
3
4
5
TP3
IO2
2IO4
4
GND1 1
GND3 3
1
2
R25
0_NP
S4
1
2
3
4
5
S1
1
2
3
4
5
R9 0
12
1
2
R16
0_NP
R15
50_NP
12
R4 33
1 2
R22
50_NP
12
R6 0
12
R57
50_NP
12
1
2
C10
2pF
S3
1
2
3
4
5
S10
1
2
3
4
5
1
2
J1
HEADER 2
R55
50_NP
12
R56
50_NP
12
1
2
R14
0_NP
1
2
C7
2pF
TP1
IO
1
GND
2
1
2
R19
0_NP
1
2
C4
2pF
R2 10K
1 2
vREF0_SEL_I2CB
XO
SEL1_SDA
vREF0_SEL_I2CB
OUT0T
OUT0C
OUT1T
OUT1C
vREF0_SEL_I2CB_SW
VDDO0
VDDO1
VDDREF
OUT0
VDDA
OUT0T
OUT0C
OUT1T
OUT1C
SEL0_SCL
VDDD
XIN_CLKIN
REF0
CM0
CM1
OUT1
OUT1B
OUT0B
OTP_VPP
6©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Figure 5. 9FGV1005 Eva luation Board Schematic – page 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LABEL:
REF0_SELI2C#
AARDVARK_I2C
Unpopulate C13 when Crystal is used as
input reference
SCL_pUp
SDA_pUp
HW SEL1
HW SEL0
cut-able trace
ESR
cut trace if LD1 populated
GND
GND
GND
VDDD
A) USB_I2C or AARDVARK
set JP1[1:2], JP2 [1:2]
set J3[2:3]
opt 1) USB_I2C:
populate R33, R32 for SCL/SDA pull up
opt 2) AARDVARK_I2C
2.1. Aardvark internal pullup
populate R30,R31, no R32,R33
2.2. No internal Aardvark pull up
polulate R30,R31,R32,R33
B) User I2C with pull up board
set JP3[2:3]
use pin2 JP1 as SCK
use pin2 JP2 as SDA
Update silk screen JP3
label: A_SDA
label: A_SCL
VDDDp
VDDDp
GND
GND
GNDGND
GND
GND
GND
GND
XIN_CLKIN {1}
XO {1}
vREF0_SEL_I2CB_SW {1}
SEL0_SCL {1}
SEL1_SDA {1}
SDA {2,4}
SCL {2,4}
Title
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24Thursday, December 22, 2016
R33
1K
12
JP2
1
2
3
R27 10K
1 2
C13
100pF_NP
12
JP3
1
2
3
S11 SMA STRAIGHT
1
2
3
4
5
R30 0
1 2
J2
HEADER 5X2
2
4
6
8
10
1
3
5
7
9
X1
25MHz
1
3
2 4
R32
1K
12
R26
0_NP
1 2
LD1
Green
JP1
1
2
3
R29 50_NP
1 2
R28 10K
1 2
R31 0
1 2
XINRCONN XIN_CLKIN_X1
JP2_pdwn
JP1_pdwn
SDA_pUp
7©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Figure 6. 9FGV1005 Eva luation Board Schematic – page 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Locate near
DUT power pin
LABEL ON EACH RESPECTIVE PIN OF
HEADERS: 1.8V, 2.5V, 3.3V
Header Alignment:
Single pin header above
and below the center pin
of 3-pin header so that
center pin can be jumped
with the surrounding 4
pins, shown as left
Locate near
DUT power pin
VDDO_J
GND GND
GND
VDD_J VDDAp
VDDDp
GND GND
GND
GND
VDDREFp
VDDO0
VDDO1
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
USB_5V {3,4}
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34Thursday, December 22, 2016
FB4
BLM18AG601SN1D
J4
Power Jack Red
FB2
BLM18AG601SN1D
E2
3
2
5
4
1
E1
3
2
5
4
1
C41
10uF
C47
10uF
R40 13.3K_1%
1 2
R39
23.2K_1%
12
J5
Power Jack Black
C18
0.1uF
12
C14
0.1uF
12
R66
POT_25K_NP
1 3
2
R36 21K_1%
1 2
VDDO_1
C15
10uF
C48
10uF
GND1
C29
10uF
VDD_REFP1
VDDAP_VDDDP1
1
2
J7
HEADER 2
GND2
R64
POT_25K_NP
1 3
2
E3
3
2
5
4
1
C33
0.1uF
12
C20
10uF
J3
Power Jack Red
R34 2.2
1 2
C23
10uF
C30
0.1uF
12
U3
LP38789
IN
1
IN
2
IN(CP)
3
CP
4
EN
5
GND(CP)
6
GND 7
FB 8
SET 9
OUT(FB) 10
OUT 11
OUT 12
EPAD
13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
EPAD
20
EPAD
21
C22
0.1uF
12
C31
0.1uF
12
E4
3
2
5
4
1
C42
10uF
C39
10uF
U4
LP38789
IN
1
IN
2
IN(CP)
3
CP
4
EN
5
GND(CP)
6
GND 7
FB 8
SET 9
OUT(FB) 10
OUT 11
OUT 12
EPAD
13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
EPAD
20
EPAD
21
C19
0.1uF
12
R62
POT_25K_NP
1 3
2
R67
1K_NP
1 2
C28
0.1uF
12
R38 15K_1%
1 2
R37
16.2K_1%
12
C21
0.1uF
12
C27
0.1uF
12
R63
1K_NP
1 2
FB1
BLM18AG601SN1D
C40
0.01uF
12
R35
10.5K_1%
12
C26
10uF
C46
0.1uF
12
C16
0.1uF
12
R65
1K_NP
1 2
C37
0.01uF
12
C25
0.1uF
12
C17
10uF
VDDO_2
FB5
BLM18AG601SN1D
C32
10uF
C38
10uF
U5
LP38789
IN
1
IN
2
IN(CP)
3
CP
4
EN
5
GND(CP)
6
GND 7
FB 8
SET 9
OUT(FB) 10
OUT 11
OUT 12
EPAD
13
EPAD
14
EPAD
15
EPAD
16
EPAD
17
EPAD
18
EPAD
19
EPAD
20
EPAD
21
C24
0.1uF
12
FB3
BLM18AG601SN1D VDDO_J
VDDO_J
VDDO_J
GND_J
VDD_J R31_C31
USB_5V VDDO_1.8V
VDDO_1
VDD_REFp
VDDO_0
USB_5V
R32_C45
USB_5V
R33_C48
USB_5V VDDO_3.3V
R36_C56
GND
VDDO_2.5V
VDDO_3.3V
VDDO_1.8V
VDDO_2.5V
VDDO_3.3V
VDDO_1.8V
VDDO_2.5V
VDDO_3.3V
VDDO_1.8V
VDDO_2.5V
VDDO_2.5V
VDDO_3.3V
VDDO_1.8V
VDDA_VDDD
VDDA_p
REG_CP3
REG_SET3
REG_D3
REG_CP4
REG_SET4
REG_D4
REG_CP5
REG_SET5
REG_D5
8©2018 Integrated Device Technology, Inc. February 28, 2018
9FGV1005 PhiClock™ Evaluation Board User Guide
Figure 7. 9FGV1005 Eva luation Board Schematic – page 4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
On Layout, make EPAD to easy connect to GND
mod1: connect C55 p1 to C52 p1
TP23: Label TP23 / 5V INPUT
R41: provide USB 5 V to Regulators
GND
VCC2232_3V
GND
GND
GND
GND
GND
GND
GND
GND
SDA {2}
SCL {2}
USB_5V{3}
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1
2
C52 10uF
FB9
BLM18AG601SN1D
C57
0.047uF
12
MTH#6_1
NS/MOUNTING HOLE
FB10
300ohm 2A
R47 0
1 2
R51
10K
1 2
R41
0
1 2
LD2
Green
MTH#6_3
NS/MOUNTING HOLE
FB8
300ohm 2A
C58
33pF
TP23
R43
470
12
R42
1K
12
R45
27
12
R49
10K
1 2
U6
FT2232_LQFP48
EESK
1
EEDATA
2
VCC 3
RESET#
4
RSTOUT#
5
3V3OUT
6
USBDP
7
USBDM
8
GND
9
SI/WUA 10
GPIOH3 11
GPIOH2 12
GPIOH1 13
VCCIOA 14
GPIOH0 15
GPIOL3 16
GPIOL2 17
GND
18
GPIOL1 19
GPIOL0 20
TMS/CS 21
TDO/DI 22
TDI/DO 23
TCK/SK 24
GND
25
SI/WUB 26
UNUSED11 27
UNUSED10 28
UNUSED9 29
UNUSED8 30
VCCIOB 31
UNUSED7 32
UNUSED6 33
GND
34
UNUSED5 35
UNUSED4 36
UNUSED3 37
UNUSED2 38
UNUSED1 39
UNUSED0 40
PWREN# 41
VCC 42
XTIN
43
XTOUT
44
AGND
45
AVCC 46
TEST
47
EECS
48
EPAD1
49
EPAD2
50
EPAD3
51
EPAD4
52
C53
47uF
C805A
12
Fiducial
FID3
FIDUCIAL
Y1
6MHz
12
R44
27
12
R46 0
1 2
MTH#6_2
NS/MOUNTING HOLE
TP24
Fiducial
FID2
FIDUCIAL
C56
0.1uF
12
R50
10K
12
C54 10uF
C51 0.1uF
1 2
C59
33pF
Fiducial
FID1
FIDUCIAL
C50 0.1uF
1 2
R48
1.5K
1 2
MTH#6_4
NS/MOUNTING HOLE
C55
0.1uF
1 2
J6
USB PORT
VBUS 1
D- 2
D+ 3
GND 4
IDT
LOGO_IDT1
USB_9
3V3_USB
3V3_USB0
3V3_USB1
3V3_USB
XTIN
VCC2232
USB_15
3V3_USB
USB_6
USB_5
USB_4
USB_7
VCC2232
USB_10
XTOUT
USB_13
USB_3
USB_14
USB_12
USB_2
USB_8
USB_1
USB_11
9©2018 Integrated Device Technology, Inc. February 28, 2018
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9FGV1005 PhiClock™ Evaluation Board User Guide
Ordering Information
Revision History
Orderable Part Number Description
EVK9FGV1005 Evaluation board with all differential outputs AC coupled.
Revision Date Description of Change
February 28, 2018 Updated numbering and labeling in Evaluation Board Pins and Functions table and Evaluation Board
Overview diagram.
November 28, 2017 Initial release.
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to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
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