© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 5
1Publication Order Number:
MC74LVXT4052/D
MC74LVXT4052
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4052 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The LVXT4052 is similar in pinout to the high−speed HC4052A
and the metal−gate MC14052B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
TTL levels.
This device has been designed so the ON resistance (RON) is more
linear over input voltage than the RON of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
•Select Pins Compatible with TTL Levels
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Analog Power Supply Range (VCC − VEE) = *3.0 V to )3.0 V
•Digital (Control) Power Supply Range (VCC − GND) = 2.5 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
•Low Noise
•Designed to Operate on a Single Supply with VEE = GND, or Using
Split Supplies up to ±3.0 V
•Break−Before−Make Circuitry
•These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
M SUFFIX
CASE 966
SOIC−16
D SUFFIX
CASE 751B
LVXT4052G
AWLYWW
LVXT4052
ALYWG
1
16
1
16
1
16
LVXT4052 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
LVXT
4052
ALYWG
G
MC74LVXT4052
http://onsemi.com
2
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
Figure 1. Pin Connection and Marking Diagram
(Top View)
Figure 2. Logic Diagram
Double−Pole, 4−Position Plus Common Off
FUNCTION TABLE
L
L
H
H
X
L
H
L
H
X
Control Inputs
ON ChannelsEnable
Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Y0
Y1
Y2
Y3
NONE
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y
3
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.
ORDERING INFORMATION
Device Package Shipping†
MC74LVXT4052DG SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVXT4052DR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVXT4052DTG TSSOP−16* 96 Units / Rail
MC74LVXT4052DTR2G TSSOP−16* 2500 Tape & Reel
MC74LVXT4052MG SOEIAJ−16
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74LVXT4052
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
ÎÎÎÎÎ
ÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎÎ
ÎÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
*7.0 to )0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
*0.5 to )7.0
*0.5 to )7.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VEE *0.5 to VCC )0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
VIN
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
*0.5 to 7.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Current, Into or Out of Any Pin
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
$20
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎÎ
ÎÎÎÎÎ
TSTG
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature Range
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
*65 to )150
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎÎ
ÎÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
260
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎÎ
ÎÎÎÎÎ
TJ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Junction Temperature under Bias
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
)150
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
JA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Thermal Resistance SOIC
TSSOP
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
143
164
ÎÎÎ
ÎÎÎ
ÎÎÎ
°C/W
ÎÎÎÎÎ
ÎÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air, SOIC
TSSOP
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
500
450
ÎÎÎ
ÎÎÎ
mW
ÎÎÎÎÎ
ÎÎÎÎÎ
MSL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Moisture Sensitivity
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Level 1
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
FR
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Flammability Rating Oxygen Index: 30% − 35%
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
UL 94−V0 @ 0.125 in
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VESD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
u2000
u200
u1000
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
ILATCHUP
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Latchup Performance Above VCC and Below GND at 125°C (Note 4)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
$300
ÎÎÎ
ÎÎÎ
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
ÎÎÎÎÎ
ÎÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎ
ÎÎÎÎ
*6.0
ÎÎÎÎ
ÎÎÎÎ
GND
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2.5
2.5
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
6.0
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
VIN
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Note 5) (Referenced to GND)
ÎÎÎÎ
0
ÎÎÎÎ
6.0
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎÎ
ÎÎÎÎ
*55
ÎÎÎÎ
ÎÎÎÎ
125
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall Time VCC = 3.0 V $ 0.3 V
(Channel Select or Enable Inputs) VCC = 5.0 V $ 0.5 V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
0
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
100
20
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns/V
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
NORMALIZED FAILURE RATE
TIME, YEARS
TJ = 130_C
TJ = 120_C
TJ = 110_C
TJ = 100_C
TJ = 90_C
TJ = 80_C
MC74LVXT4052
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4
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Symbol Parameter Condition
VCC
V
Guaranteed Limit
Unit
*55 to 25°Cv85°Cv125°C
VIH Minimum High−Level Input Volt-
age,
Channel−Select or Enable Inputs
3.0
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL Maximum Low−Level Input Volt-
age,
Channel−Select or Enable Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IIN Maximum Input Leakage Current,
Channel−Select or Enable Inputs
VIN = 6.0 or GND 0 V to 6.0 V $0.1 $1.0 $1.0 A
ICC Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND
6.0 4.0 40 80 A
DC ELECTRICAL CHARACTERISTICS − Analog Section
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Test Conditions
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC
V
ÎÎÎ
ÎÎÎ
ÎÎÎ
VEE
V
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎ
ÎÎ
ÎÎ
Unit
ÎÎÎÎÎ
ÎÎÎÎÎ
*55 to 25°C
ÎÎÎ
ÎÎÎ
v85_C
ÎÎÎÎ
ÎÎÎÎ
v125_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
RON
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum “ON” Resistance
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VIN = VIL or VIH
VIS = ½ (VCC − VEE)
|IS| = 2.0 mA (Figure 4)
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
3.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0
0
*3.0
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
86
37
26
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
108
46
33
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
120
55
37
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
RON
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Difference in “ON” Re-
sistance Between Any Two
Channels in the Same Package
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VIN = VIL or VIH
VIS = ½ (VCC − VEE)
|IS| = 2.0 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
3.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
0
0
*3.0
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
15
13
10
ÎÎÎ
ÎÎÎ
ÎÎÎ
20
18
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
20
18
15
ÎÎ
ÎÎ
ÎÎ
Ioff Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 3)
5.5
+3.0
0
−3.0
0.1
0.1
0.5
0.5
1.0
1.0
A
Maximum Off−Channel
Leakage Current,
Common Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 4)
5.5
+3.0
0
−3.0
0.2
0.2
2.0
2.0
4.0
4.0
Ion Maximum On−Channel
Leakage Current,
Channel−to−Channel
Vin = VIL or VIH;
Switch−to−Switch =
VCC or GND; (Figure 5)
5.5
+3.0
0
−3.0
0.2
0.2
2.0
2.0
4.0
4.0
A
AC CHARACTERISTICS (Input tr = tf = 3 ns)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Test Conditions
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC
V
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VEE
V
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Unit
ÎÎÎÎÎ
ÎÎÎÎÎ
*55 to 25_C
ÎÎÎ
ÎÎÎ
ÎÎÎ
v85_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v125_C
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Typ*
tBBM Minimum Break−Before−Make
Time
VIN = VIL or VIH
VIS = VCC
RL = 300 CL = 35 pF
(Figures 12 and 13)
3.0
4.5
3.0
0.0
0.0
*3.0
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
*Typical Characteristics are at 25_C.
MC74LVXT4052
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5
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Symbol Parameter
VCC
V
VEE
V
Guaranteed Limit
Unit
*55 to 25°Cv85°Cv125°C
Min Typ Max Min Max Min Max
tPLH,
tPHL
Maximum Propagation Delay, Channel−Select
to Analog Output
(Figures 16 and 17)
2.5
3.0
4.5
3.0
0
0
0
*3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
*3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
*3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
CPD Power Dissipation Capacitance (Figure 18) (Note 6)
Typical @ 25°C, VCC = 5.0 V, VEE = 0V
45 pF
CIN Maximum Input Capacitance, Channel−Select or Enable Inputs 10 pF
CI/O Maximum Capacitance Analog I/O
(All Switches Off) Common O/I
Feedthrough
10
10
1.0 pF
6. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol Parameter Condition
VCC
V
VEE
V
Typ
Unit
25°C
BW Maximum On−Channel Bandwidth or Minimum
Frequency Response
VIS = ½ (VCC − VEE)
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 7)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
*3.0
80
80
80
80
MHz
VISO Off−Channel Feedthrough Isolation f = 1 MHz; VIS = ½ (VCC − VEE)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figures 8 and 9)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
*3.0
*70
*70
*70
*70
dB
VONL Maximum Feedthrough On Loss VIS = ½ (VCC − VEE)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figure 11)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
*3.0
*2
*2
*2
*2
dB
QCharge Injection VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 , CL= 1000 pF, Q = CL * VOUT
(Figure 10)
5.0
3.0
0.0
*3.0
9.0
12
pC
THD Total Harmonic Distortion THD + Noise fIS = 1 MHz, RL = 10 K, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 19)
6.0
3.0
0.0
*3.0
0.10
0.05
%
MC74LVXT4052
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6
Figure 4. On Resistance, Test Set−Up
PLOTTER
MINI
COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
DEVICE
UNDER TEST
GND
ANALOG IN COMMON OUT
GND
*)
Figure 5. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 6. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 7. Maximum On Channel Bandwidth, Test Set−Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VIH
NC
A
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
VEE
VEE
ON
OFF
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50 K
100 K
VIS
A
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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7
Figure 8. Maximum Off Channel Feedthrough Isolation, Test Set−Up
Figure 9. Maximum Common−Channel Feedthrough Isolation, Test Set−Up
OFF
ON
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50 K
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
VISO(dB) = 20 log (VT1/VR1)
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
VISOC(dB) = 20 log (VT1/VR1)
ON
50 K
OFF
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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Figure 10. Charge Injection, Test Set−Up
ON/OFF
7
8
VCC
VOUT
OFF/ON
9−11
CL*
VIH
VIL
*Includes all probe and jig capacitance.
16
Bias Channel Selects to
test each combination of
analog inputs to common
analog output.
6
Enable
VEE
VIN RIS
VIS
VOUT VOUT
Q = CL * VOUT
Figure 11. Maximum On Channel Feedthrough On Loss, Test Set−Up
OFF
ON
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 20 dB
VONL(dB) = 20 log (VT1/VR1)
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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9
Figure 12. Break−Before−Make, Test Set−Up Figure 13. Break−Before−Make Time
ON
OFF
6
7
8
VCC
VEE
9−11
Tek 11801B
DSO
COM INPUT
16
RLCL
VIN
50
VIN
80%
VCC
tBBM
80% of
VOH
Figure 14. Propagation Delays, Channel Select
to Analog Out
Figure 15. Propagation Delay, Test Set−Up
Channel Select to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
50%
ON/OFF
6
7
8
16
VCC
CL*
CHANNEL SELECT
TEST
POINT
COMMON
OFF/ON
ANALOG I/O
VCC
ON/OFF
6
7
8
ENABLE
VCC
ENABLE 90%
50%
10%
tftr
VCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC
1 K
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
GND
GND
O/I
Channel Selects connected
to VIN and appropriately
configured to test each switch.
VOH
*Includes all probe and jig capacitance.
Figure 16. Propagation Delays, Enable to
Analog Out
Figure 17. Propagation Delay, Test Set−Up
Enable to Analog Out
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Figure 18. Power Dissipation Capacitance, Test Set−Up
ON/OFF
12
VCC
NC
OFF/ON
10 −11,
13 −14 Channel
Select
15
VIL
VCC
A
Figure 19. Total Harmonic Distortion, Test Set−Up
6
7
89−11
HP3466
DMM
16
50 K
)V
COM
HP3466
DMM
)V
COM
HP E3630A
DC Pwr Supply
COM )20 V *20 V
HP 339
Distortion Measurement Set
Analyzer
Input COM
Oscillator
Output COM
RLCL
ON
OFF
Channel Selects connected
to DC bias supply or ground
and appropriately configured
to test each switch.
MC74LVXT4052
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11
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = )5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swing is determined by the
supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is five volts. Therefore,
using the configuration of Figure 21, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VEE − GND = 0 to *6 volts
VCC − GND = 2.5 to 6 volts
VCC − VEE = 2.5 to 6 volts
and VEE v GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
ANALOG
SIGNAL
Figure 20. Application Example
ON
6
7
8
16
+3.0 V
ANALOG
SIGNAL
+3.0 V
−3.0 V
+3.0 V
−3.0 V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 3.0 V
DIGITAL SIGNALS
−3.0 V
Figure 21. Application Example
ANALOG
SIGNAL
ON
6
7
8
16
+5 V
ANALOG
SIGNAL
+5 V
GND
+5 V
GND
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5 V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
VEE
Figure 22. External Germanium or Schottky Clipping Diodes
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12
Figure 23. Function Diagram, LVXT4052
12 X0
14 X1
15 X2
11 X3
1Y0
5Y1
2Y2
4Y3
3Y
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
10
A
9
B
6
ENABLE
13 X
MC74LVXT4052
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13
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
MC74LVXT4052
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PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
MC74LVXT4052/D
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