Programmable Delay Lines senies: PDU-53 100K ECL Interfaced (3 BIT) 16 Pins DIP Features: a 3-BIT Programmable @ Accurate Timing = Completely 100K ECL Interfaced Specifications: = Min. input pulse width: 3 ns or 15% of total delay whichever is greater. = Min. PRR: 8 ns or 2 x pulse width . . ain | i : 7 : whichever is greater. reat pulse width input pulse voltage @ Delay variation: Monotonic in one direction. = Input PRR: : Su oly voltage (Vee): Programmed delay tolerance: 5% or 40 ps 100ns ye ge Wee): whichever is greater. . : & Input pulse rise- : a : = Inherent delay (Too): 2.2 ns. ' pe pulse rise-time Ameren temperature(Ta) Address to output prop. delay (Tsua): 2.9 ns max. a Power supply voltage: 5V + .7V. m Power supply current: 150 ma. = Temperature coefficient: 100 PPM/C. = Operating temp. range: 0C to +85C. TOPCO fe = Storage temp. range: 65C to + 150C. + m DC parameters: See ECL-100K Logic Table on Page 6. may. fos 4 QUO NOOOU [S_ le.870+ 010 >| 380 MAX. sf a TYP. 100 TYP.>} e ADDRES Delay Total increment Programmed Part No. (ps) Delay (ps) 1 2 3 PDU-53-100 100+ 50 700 PDU-53-200 200+ 60 1,400 foro 12] 14) 15) --5 PDU-53-250 250+ 60 1,750 ' PDU-53-400 400+ 80 2,800 13! ! Vee o+-* 1 PDU-53-500 500 + 100 3,500 46! ; PDU-53-750 750 + 100 5,250 4 PDU-53-1000 1,000 + 200 7,000 INO+{>j_ piGiTAL DELAY F-{>+0 OUT PDU-53-1200 1,200 + 200 8,400 3| } O-+-* I PDU-53-1500 1,500 + 200 10,500 GRD t I PDU-53-2000 2,000 + 400 14,000 Le ee ee ne ce ee ee | PDU-53-2500 2,500 + 400 17,500 PDU-53-3000 3,000 + 500 21,000 Test Conditions: No pull-up resistors used internally on input & output. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 m (973) 773-2299 m Fax (973) 773-9672 38