ISL9216IRZ-T - Intersil Corporation

FN6488.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL9216, ISL9217

8 to 12 Cell Li-Ion Battery Overcurrent

Protection and Analog Front End Chip Set

The ISL9216 and ISL9217 chipset provides overcurrent

protection and voltage monitoring for multi-cell li-ion battery

packs consisting of 8 to 12 cells . When used together, these

devices provide integrated overcu rrent protection circuitry,

short circuit protection, an internal voltage regulator, internal

cell balancing switches, cell voltage level shifters, and drive

circuitry for external FET devices that control pack charge

and discharge. Leve l shifting of the analog output voltage

from the upper cells and communication between the chips

is handled automatically.

Overcurrent and short circuit thresholds reside in internal

RAM registers and are selected independently via software

using an I2C serial interface. Detection and time-out delays

can be individually varied using internal registers.

Using an internal analog multiplexer, the device provides

monitoring of cell voltage by a separate microcontroller with

A/D converter. Software on this microcontroller implements

all battery control functionality, except for overcurrent and

short circuit shutdown.

Applications

• Power Tools

• Battery Backup Systems

•E-bikes

• Portable Test Equipment

• Medical Systems

• Hybrid Vehicle

• Military Electronics

Features

• Software selectable overcurrent protection levels and

variable protect detection/release times

- 4 Discharge overcurrent thresholds

- 4 Short circuit thresholds

- 4 Charge overcurrent thresholds

- 8 Overcurrent delay times (Charge)

- 8 Overcurrent delay times (Discharge)

- 2 Short circuit delay times (Discharge)

• Automatic FET turn-off and cell balance disable on

reaching external (battery) or internal (IC) temperature

limit

• Automatic over-ride of cell balance on reaching internal

(IC) temperature limit

• Fast short circuit pack shutdown

• Can use current sense resistor, FET rDS(ON), or Sense

FET for overcurrent detection

• Four battery backed software controlled flags

• Allows thre e di fferent FET co ntrols:

- Back-to-back N-Channel FETs for charge and discharge

control

- Single N-Channel FET for discharge control

- N-Channel FET for discharge, with separate, optional

(smaller) back-to-back FET for charge

• Chips cascade for packs of 8 to 12 cells

• Integrated charge/discharge FET drive circuitry with

200µA (typ) turn on current and 150mA (typ) discharge

FET turn off current

• 10% accurate 3.3V voltage regulator (35mA out with

external NPN transistor having current gain of 70)

• Cell voltage monitor accurate to within 25mV

• Monitored cell voltage output stable in 100µs

• Internal cell balancing FETs handle up to 200mA of

balancing current for each cell (with the number of cells

being balanced limited by the maximum power dissipation

of 400mW)

•Simple I

2C host interface

• Sleep operation with programmable negative edge or

positive edge wake-up

• <10µA sleep mode

• Pb-free (RoHS compliant)

Ordering Information

PART NUMBER

(Note) PART

MARKING PACKAGE

(Pb-Free) PKG.

DWG. #

ISL9216IRZ* ISL9216 IRZ 32 Ld 5x5 QFN L32.5x5B

ISL9217IRZ* 921 7IRZ 24 Ld 4x4 QFN L24.4x4D

*Add “-T” suffix for tape and reel. Please refer to TB347 for details

on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach

materials and 100% matte tin plate PLUS ANNEAL - e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temper atures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet November 2, 2007

2FN6488.1

November 2, 2007

Pinouts

ISL9217 (UPPER)

(24 LD 4X4 QFN)

TOP VIEW

ISL9216 (LOWER)

(32 LD 5X5 QFN)

TOP VIEW

VC7/VCC

SCL

SDAO

WKUP

RGC

RGO

SDAI

VSS

CB1

24 23 22 21 20 19

789101112

CB4

VCELL3

CB3

VCELL2

CB2

VCELL1

CB6

VCELL5

CB5

CB7

VCELL4

VCELL6

32 31 30 29 28 27 26 25

9 10111213141516

TEMP3V

RGC

WKUP

SCLHV

RGO

SCL

SDAOHV

SDA

VMON

CFET

DFET

CSENSE

DSENSE

DSREF

TEMPI

CB2

VCELL2

CB3

VCELL3

VCELL1

CB1

VSS

CB4

SDAIHV

VC7/VCC

WKUPR

VCELL4

HVI2C

VCELL6

VCELL5

CB5

ISL9216, ISL9217

3FN6488.1

November 2, 2007

Functional Diagram

3.3VDC

REGULATOR

VSS

VC7/VCC

CSENSE

DSENSE

SDA

CB5

CB4

VCELL6

VCELL5

VCELL4

RGO

CB3

VCELL3

CB2

VCELL2

CB1

VCELL1

DSREF

TEMPI TEMP3V

SCL

REGISTERS RGC

HVI2CSDAIHVSCLHV

POWER

CONTROL

DFET

CFET

MUX

VMON

BACKUP

SUPPLY

CONTROL

LOGIC

LEVEL

CIRCUITS

BALANCE

CELL

SHIFTERS/

CELL

VOLTAGES

WKUPR

LEVEL/SHIFTERS

I2C I/F

OSC

TEMPERATURE

SENSOR,

INT/EXT

COMPARATOR,

EXT TEMP

OVERCURRENT

PROTECTION

CIRCUITS

(THRESHOLD

DETECT AND

TIMING)

FET CONTROL

CIRCUITRY

WKUP

3.3VDC

REGULATOR

VSS

VC7/VCC

CB7

CB5

CB6

CB4

VCELL6

VCELL5

VCELL4

RGO

CB3

VCELL3

CB2

VCELL2

CB1

VCELL1

SCL

REGISTERS

RGC

WKUP

POWER

CONTROL

MUX

BACKUP

SUPPLY

CONTROL

LOGIC

LEVEL

CIRCUITS

BALANCE

CELL

SHIFTERS/

CELL

VOLTAGES

SDAO SDAI

I2C I/F

OSC

INTERNAL

TEMPERATURE

SENSOR/

COMPARATOR

SDAOHV

ISL9217

ISL9216

ISL9216, ISL9217

4FN6488.1

November 2, 2007

Pin Descriptions

SYMBOL DESCRIPTION

VC7/VCC Battery Cell 7 Voltage Input/VCC Supply. This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also

provides the operating voltage for the IC circuitry.

VCELLN Battery Cell N Voltage Input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the

positive terminal of CELLN and the negative terminal of CELLN+1.

CBN Cell Balancing FET Control Output N. This internal FET diverts a fraction of the current around a cell while the cell is being charged

or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function is generally

used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an

external controller.

VSS Ground. This pin connects to the most negative terminal in the battery string.

DSREF Discharge Current Sense Reference (ISL9216 only). This input provides a separate reference poin t for the charge and discharge

current monitoring circuits. with a separate reference connection, it is possible to minimize errors that result from voltage drop s on the

ground lead when the load is drawing large currents. If a separate reference is not necessary, connect this pin to VSS.

DSENSE Discharge Current Sense Monitor (ISL9216 only). This input monitors the discharge current by monitoring a voltage. It can monitor

the voltage across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The voltage on this

pin is measured with reference to DSREF.

CSENSE Charge Current Sense Monitor (ISL9216 only). This input monitors the charge current by monitoring a voltage. It can monitor the

voltage across a sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage on this pin is

measured with reference to VSS.

DFET Discharge FET Control (ISL9216 only). The ISL9216 controls the gate of a discharge FET through this pin. The power FET is a N-

Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9216

can also turn off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition

on any of the battery cells, it will turn off the FET off by controlling this output with a control bit.

CFET Charge FET Control (ISL9216 only). The ISL9216 controls the gate of a charge FET through this pin. The power FET is a N-Channel

device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9216 can also

turn off the FET in the event of an overcurrent condition. If the microcontroller detects an overvoltage condition on any of the battery

cells, it will turn off the FET off by controlling this output with a control bit.

VMON Discharge Load Monitorin g (ISL9216 only). In the event of an overcurrent or short circuit condition, the microcontroller can enable

a series diode and resistor that connects between the VMON pin and VSS. When FETs open because of an overcurrent or short circuit

condition, and the load remains, the voltage at VMON will be near the VCC voltage. When the load is released, the voltage at VMON

drops below a threshold indicating that the overcurrent or short circuit condition is resolved. At this point, the LDFAIL flag is cleared

and operation can resume.

AO Analog Multiplexer Output. The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature

sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register.

TEMP3V T emperature Monitor Output Control (ISL9216 only). This pin outputs a voltage to be used in a divider that consists of a fixed resistor

and a thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO

voltage through a PMOS switch only during a measurement of the temperature, otherwise the output is off. The TEMP3V output can

be turned on continuously with a special control bit.

Microcontroller Wake-up Control. This pin is also turned on when any of the DSC, DOC, or COC bits are set. This can be used to

wake-up a sleeping microcontroller to respond to overcurrent conditions with its own control mechanism.

TEMPI Temperature Monitor Input (ISL9216 only). This pin inputs the voltage across a thermistor to determine the temperature of the cells.

When this input voltage drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the

AO output pin through an analog multiplexer so the temperature of the cells can be monitored by the microcontroller.

RGO Regulated Output Voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin

to provide a regulated 3.3V . The voltage at this pin provides feedback for the regulator and power for many of the ISL9216 and ISL9217

internal circuits. For the ISL9216, this output also provides the 3.3V output voltage for the microcontroller and other external circuits.

RGC Regulated Ou tput Control. This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to

provide a regulated 3.3V. The RGC output provides the control signal to provide the 3.3V regulated voltage on the RGO pin.

WKUP Wake-up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake-up is edge triggered) and the

condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive).

• WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin

voltage > threshold.

• WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin

voltage < threshold.

ISL9216, ISL9217

5FN6488.1

November 2, 2007

WKUPR W ake-up Upper Device Signal (ISL9216 only). This output wakes up the ISL9217 (upper device) when the output is turned on by the

microcontroller. Once the upper device is awake, this output can be turned off.

SDA Serial Data (ISL9216 only). This is the bi-directional data line for an I2C interface.

SCL Serial Clock. This is the clock line for an I2C communication link.

SDAI Serial Data Input (ISL9217 only). This pin is a uni-directional I2C serial data input from the ISL9216 to the cascaded ISL9217 device.

This pin connects to the ISL9216 SDAOHV pin.

SDAO Serial Data Output (ISL9217 only). This pin is a uni-directional I2C serial data output to the ISL9216 from the cascaded ISL9217

device. This pin connects to the ISL9216 SDAIHV pin.

SDAIHV Serial Data Input (ISL9216 only). This pin is a uni-directional I2C serial data input from the cascaded ISL9217 device to the ISL9216.

This pin connects to the ISL9217 SDAO pin.

SDAOHV Serial Dat a Output (ISL9216 only). This pin is a uni-directional serial data output from the ISL9216 to the cascaded ISL9217 device.

This pin connects to the ISL9217 SDAI pin.

SCLHV Serial Clock Output (ISL9216 only). This pin sends clock pulses from the lower device (ISL9216) to the upper device (ISL9217) for

communication between cascaded devices

HVI2CHV I2C Reference Voltage (ISL9216 only). This is a reference voltage for the ISL9216 to facilitate the communication link between

cascaded devices. Tie this pin on the ISL9216 to the RGO pin of the ISL9217.

Pin Descriptions (Continued)

SYMBOL DESCRIPTION

ISL9216, ISL9217

6FN6488.1

November 2, 2007

ISL9216, ISL9217

Absolute Maximum Ratings Thermal Information

Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V

Cell Voltage, VCELL

VCELLN to (VCELLN-1), VCELL1-VSS . . . . . . . . . . . .-0.5V to 5V

Terminal Voltage, VTERM1

(SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO,

TEMP3V, SDAI, SDAO) . . . . . . . . . . . . VSS - 0.5 to VRGO + 0.5V

Terminal Voltage

VTERM2 (CFET, VMON). . . . . . . . . . . . . . . . . VSS - 22.0V to VCC

VTERM3 (WKUP) . . . . . . . . . . . . . .VSS - 0.5V to VCC(VCC <27V)

VTERM4 (RGC). . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to 5V

VTERM5, (SDAOHV, SDAIHV, SCLHV)

. . . . . . . . . . . . . . . . . . . . . . . . VCELL5 - 0.5V to VHVI2C + 0.5V

VTERM6, (all other pins). . . . . . . . . . . . VSS - 0. 5V to VCC + 0.5V

Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)

32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 31 2

24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 32 2

Continuous Package Power Dissipation . . . . . . . . . . . . . . . .400mW

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Voltage

VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to 30.1V

VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V

VCELLN-(VCELLN-1) . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to 4.3V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Operating Spec ifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating

Conditions, Unless Otherwise Specified.

DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Operating Voltage VCC 9.2 31 V

Power-up Condition 1 VPORVCC VCC voltage (Note 3) 4 9.2 V

Power-up Condition 2 Threshold VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and

VCELL3 - VCELL2 (rising) (Note 3) 1.1 1.7 2.3 V

Power-up Condition 2 Hysteresis VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and

VCELL3 - VCELL2 (falling) (Note 3) 70 mV

3.3V Regulated Voltage VRGO 0μA < IRGC < 350μA 3.0 3.3 3.6 V

3.3VDC Voltage Regulator Control

Current Limit IRGC (Control current at output of RGC.

Recommend NPN with gain of 70+) 0.35 0.50 mA

VCC Supply Current IVCC1 Power-up defaults, WKUP pin = 0V. 400 510 µA

RGO Supply Current IRGO1 300 410 µA

VCC Supply Current IVCC2 LDMONEN bit = 1, VMON floating, CFET = 1,

DFET = 1, WKPOL bit = 1, VWKUP = 10V,

[AO3:AO0] bit s = 06H .

400 700 µA

RGO Supply Current IRGO2 450 650 µA

VCC Supply Current IVCC3 Default register settings, except SLEEP

bit = 1. WKUP pin = VCELL1 10 µA

RGO Supply Current IRGO3 1µA

VCELL Input Current - VCELL1 IVCELL1 AO3:AO0 = 0000H 14 µA

VCELL Input Current - VCELL5 IVCELL1 AO3:AO0 = 0000H (ISL9216 Only) 20 µA

VCELL Input Current - VCELLN IVCELLN AO3:AO0 = 0000H 10 µA

OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS (ISL9216 only)

Overcurrent Detection Threshold

(Discharge) Voltage Relative to DSREF

(Default in Boldface)

VOCD VOCD = 0.10V (OCDV1, OCDV0 = 0, 0) 0.08 0.10 0.12 V

VOCD = 0.12V (OCDV1, OCDV0 = 0, 1) 0.10 0.12 0.14 V

VOCD = 0.14V (OCDV1, OCDV0 = 1, 0) 0.12 0.14 0.16 V

VOCD = 0.16V (OCDV1, OCDV0 = 1, 1) 0.14 0.16 0.18 V

7FN6488.1

November 2, 2007

Overcurrent Detection Threshold

(Charge) Voltage Relative to DSREF

(Default in Boldface)

VOCC VOCC = 0.10V (OCCV1, OCCV0 = 0, 0) -0.12 -0.10 -0.07 V

VOCC = 0.12V (OCCV1, OCCV0 = 0, 1) -0.14 -0.12 -0.09 V

VOCC = 0.14V (OCCV1, OCCV0 = 1, 0) -0.16 -0.14 -0.11 V

VOCC = 0.16V (OCCV1, OCCV0 = 1, 1) -0.18 -0.16 -0.13 V

Short Current Detection Threshold

(Discharge) Voltage Relative to DSREF

(Default in Boldface)

VSC VOC = 0.20V (SCDV1, SCDV0 = 0, 0) 0.15 0.20 0.25 V

VOC = 0.35V (SCDV1, SCDV0 = 0, 1) 0.30 0.35 0.40 V

VOC = 0.65V (SCDV1, SCDV0 = 1, 0) 0.60 0.65 0.70 V

VOC = 1.20V (SCDV1, SCDV0 = 1, 1) 1.10 1.20 1.30 V

Load Monitor Input Threshold

(falling edge) VVMON LDMONEN bit = “1” 1.1 1.45 1.8 V

Load Monitor Input Threshold

(hysteresis) VVMONH LDMONEN bit = “1” 0.25 mV

Load Monitor Current IVMON 20 40 60 µA

Short Circuit Time-out tSCD Internal short circuit detection delay

(SCLONG bit = ‘0’) 90 190 290 µs

Internal short circuit detection delay

(SCLONG bit = ‘1’) 510 15ms

Over Discharge Current Time-out

(Default in Boldface) tOCD tOCD = 160ms (OCDT1, OCDT0 = 0, 0 and

DTDIV = 0) 80 160 240 ms

tOCD = 320ms (OCDT1, OCDT0 = 0, 1 and

DTDIV = 0) 160 320 480 ms

tOCD = 640ms (OCDT1, OCDT0 = 1, 0 and

DTDIV = 0) 320 640 960 ms

tOCD = 1280ms (OCDT1, OCDT0 = 1, 1 and

DTDIV = 0) 640 1280 1920 ms

tOCD = 2.5ms (OCDT1, OCDT0 = 0, 0 and

DTDIV = 1) 1.25 2.50 3.75 ms

tOCD = 5ms (OCDT1, OCDT0 = 0, 1 and

DTDIV = 1) 2.5 5 7.5 ms

tOCD = 10ms (OCDT1, OCDT0 = 1, 0 and

DTDIV = 1) 510 15ms

tOCD = 20ms (OCDT1, OCDT0 = 1, 1 and

DTDIV = 1) 10 20 30 ms

Over Charge Current Time-out

(Default in Boldface) tOCC tOCC = 80ms (OCCT1, OCCT0 = 0, 0 and

CTDIV = 0) 40 80 120 ms

tOCC = 160ms (OCCT1, OCCT0 = 0, 1 and

CTDIV = 0) 80 160 240 ms

tOCC = 320ms (OCCT1, OCCT0 = 1, 0 and

CTDIV = 0) 160 320 480 ms

tOCC = 640ms (OCCT1, OCCT0 = 1, 1 and

CTDIV = 0) 320 640 960 ms

tOCC = 2.5ms (OCCT1, OCCT0 = 0, 0 and

CTDIV = 1) 1.25 2.50 3.75 ms

tOCC = 5ms (OCCT1, OCCT0 = 0, 1 and

CTDIV = 1) 2.5 5 7.5 ms

tOCC = 10ms (OCCT1, OCCT0 = 1, 0 and

CTDIV = 1) 510 15ms

tOCC = 20ms (OCCT1, OCCT0 = 1, 1 and

CTDIV = 1) 10 20 30 ms

Operating Spec ifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating

Conditions, Unless Otherwise Specified. (Continued)

DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

ISL9216, ISL9217

8FN6488.1

November 2, 2007

OVER-TEMPERATURE PROTECTION SPECIFICATIONS

Internal Temperature Shutdown

Threshold TINTSD 115 °C

Internal Temperature Hysteresis THYS Temperature drop needed to restore

operation after an over-temperature

shutdown.

105 °C

Internal Over-T emperature Turn-on Delay

Time TITD 128 ms

External Temperature Output Cur rent IXT Current output capability at TEMP3V pin

(ISL9216 only) 1.2 mA

External Temperature Limit Threshold TXTF Voltage at VTEMPI (ISL9216 only);

Relative to: . (Falling edge)

-20 0 +20 mV

External Temperature Limit Hysteresis TXTH Voltage at VTEMPI (ISL9216 only). 60 110 160 mV

External Temperature Monitor Delay tXTD Delay between activating the external

sensor and the internal over-temp

detection. (ISL9216 only)

1ms

External Temperature Autoscan On Time tXTAON TEMP3V is ON (3.3V) (ISL9216 only) 5 ms

External Temperature Autoscan Off Time tXTAOFF TEMP3V output is off. (ISL9216 only) 635 ms

ANALOG OUTPUT SPECIFICATIONS

Cell Monitor Analog Output Voltage

Accuracy VAO6A [VCELL1 - (VSS)]/2 - AO

[VCELLN - (VCELLN-1)]/2 - AO for N = 1 to 5.

(ISL9216 only)

-25 30 mV

VAO6B VCELL6 - AO.

(ISL9216 only) -42 58 mV

VAO7A [VCELL1 - (VSS)]/2 - AO

[VCELLN - (VCELLN-1)]/2 - AO for N = 1 to 5.

(ISL9217 only)

-20 25 mV

VAO7B [VCELLN - (VCELLN-1)]/2 - AO for N = 6 to 7.

(ISL9217 only) -32 43 mV

Cell Monitor Analog Output External

Temperature Accuracy VAOXT External temperature monitoring accuracy.

Voltage error at AO when monitoring TEMPI

voltage (measured with TEMPI = 1V)

-10 10 mV

Internal Temperature Monitor Output

Voltage Slope VINTMON Internal temperature monitor voltage

change -3.5 mV/°C

Internal Temperature Monitor Output TINT25 Output at +25°C 1.31 V

AO Output Stabilization Time tVSC From SCL falling edge at data bit 0 of

command to AO output stable within 0.5%

of final value. AO voltage steps from 0V to

2V. (Note 6)

0.1 ms

CELL BALANCE SPECIFICATIONS

Cell Balance Transistor rDS(ON) RCB (Note 5) 5 Ω

Cell Balance Transistor Current ICB 200 mA

Operating Spec ifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating

Conditions, Unless Otherwise Specified. (Continued)

DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

VTEMP3V

------------------------------

ISL9216, ISL9217

9FN6488.1

November 2, 2007

WAKE-UP/SLEEP SPECIFICATIONS

Device WKUP Pin Voltage Threshold

(WKUP pin active HIGH rising edge) VWKUP1 WKUP pin rising edge (WKPOL = 1)

Device wakes up and sets WKUP flag

HIGH. (ISL9216 only)

3.5 5.0 6.5 V

Device WKUP Pin Hysteresis

(WKUP pin active HIGH) VWKUP1H WKUP pin falling edge hysteresis

(WKPOL = 1) sets WKUP flag LOW (does

not automatically enter sleep mode)

(ISL9216 only)

100 mV

Internal Resistor on WKUP RWKUP Resistance from WKUP pin to VSS

(WKPOL = 1) (ISL9216 only) 130 230 330 kΩ

Device WKUP Pin Voltage Threshold

(WKUP pin active LOW - Falling Edge) VWKUP2 WKUP pin falling edge (WKPOL = 0)

Device wakes up and sets WKUP flag

HIGH.

VCELL1 - 2.6 VCELL1 - 2.0 VCELL1 - 1.2 V

Device WKUP Pin Hysteresis

(WKUP pin active LOW) VWKUP2H WKUP pin rising edge hysteresis

(WKPOL = 0) sets WKUP flag LOW (does

not automatically enter sleep mode)

200 mV

Device Wake-up Delay tWKUP Delay after voltage on WKUP pin crosses

the threshold (rising or falling) before

activating the WKUP bit.

20 40 60 ms

FET CONTROL SPECIFICATIONS (For VCELL1, VCELL2, VCELL3 voltages from 2.8V to 4.3V - ISL9216 only)

Control Outputs Response Time

(CFET, DFET) tCO Bit 0 to start of control signal (DFET)

Bit 1 to start of control signal (CFET) 1.0 µs

CFET Gate Voltage VCFET No load on CFET VCELL3 - 0.5 VCELL3 V

DFET Gate Voltage VDFET No load on DFET VCELL3 - 0.5 VCELL3 V

FET Turn-on Current (DFET) IDF(ON) DFET voltage = 0 to VCELL3 - 1.5V 80 130 400 µA

FET Turn-on Current (CFET) ICF(ON) CFET voltage = 0 to VCELL3 - 1.5V 80 200 400 µA

FET Turn-off Current (DFET) IDF(OFF) DFET voltage = VDFET to 1V 100 180 mA

DFET Resistance to VSS RDF(OFF) VDFET <1V (When turning off the FET) 11 Ω

SERIAL INTERFACE CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

SCL Clock Frequency fSCL 100 kHz

SCL Falling Edge to SDA Output Data

Valid tAA From SCL falling crossing VIH(min), until

SDA exits the VIL(max) to VIH(min) window . 3.5 µs

Time the Bus Must be Free Before Start of

New Transmission tBUF SDA crossing VIH(min) during a STOP

condition to SDA crossing VIH(min) during

the following START condition.

4.7 µs

Clock LOW Time tLOW Measured at the VIL(max) crossing. 4.7 µs

Clock HIGH Time tHIGH Measured at the VIH(min) crossing. 4.0 µs

Start Condition Setup Time tSU:STA SCL rising edge to SDA falling edge. Both

crossing the VIH(min) level. 4.7 µs

Start Condition Hold Time tHD:STA From SDA falling edge crossing VIL(max) to

SCL falling edge crossing VIH(min). 4.0 µs

Input Data Setup Time tSU:DAT From SDA exiting the VIL(max) to VIH(min)

window to SCL rising edge crossing

VIL(min).

250 ns

Input Data Hold Time tHD:DAT From SCL rising edge crossing VIH(min) to

SDA entering the VIL(max) to VIH(min)

window.

300 ns

Stop Condition Setup Time tSU:STO From SCL rising edge crossing VIH(min) to

SDA rising edge crossing VIL(max). 4.0 µs

Operating Spec ifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating

Conditions, Unless Otherwise Specified. (Continued)

DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

ISL9216, ISL9217

10 FN6488.1

November 2, 2007

Stop Condition Hold Time tHD:STO From SDA rising edge to SCL falling edge.

Both crossing VIH(min). 4.0 µs

Data Output Hold Time tDH From SCL falling edge crossing VIL(max)

until SDA enters the VIL(max) to VIH(min)

window. (Note 4)

0ns

SDA and SCL Rise Time tRFrom VIL(max) to VIH(min). 1000 ns

SDA and SCL Fall Time tFFrom VIH(min) to VIL(max). 300 ns

Capacitive Loading of SDA or SCL Cb Total on-chip and off-chip 400 pF

SDA and SCL Bus Pull-up Resistor - Off

Chip ROUT Maximum is determined by tR and tF.

For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ

For Cb = 40pF, max is about 15kΩ to 20kΩ

1kΩ

Input Leakage Current (SCL, SDA, SDAI,

SDAO, SCLHV, SDAIHV, SDAOHV) ILI -10 10 µA

Input Buffer LOW Voltage (SCL, SDA,

SDAI) VIL1 Voltage relative to VSS of the device. -0.3 VRGO x 0.3 V

Input Buffer HIGH Voltage (SCL, SDA,

SDAI) VIH1 Voltage relative to VSS of the device. VRGO x 0.7 VRGO + 0. 1V V

Input LOW Voltage (SDAIHV) VIL2 SDAIHV pulled up to HCI2C. (ISL9216 only) VCELL5 - 0.3 VVCELL5 +

[VHVI2C -

VVCELL5] x 0.3

Input HIGH Voltage (SDAIHV) VIH2 SDAIHV pulled up to HCI2C. (ISL9216 only) VVCELL5 +

[VHVI2C -

VVCELL5] x

0.7

VHVI2C + 0.1V V

Output Buffer LOW V o ltage (SDA, SDAO) VOL1 IOL = 1mA

(voltage relative to VSS of the device) 0.4 V

Output Buffer LOW Voltage (SDAOHV) VOL2 IOL = 1mA VVCELL5 + 0.5 V

SDA, SCL, SDAI Input Buffer Hysteresis I2CHYST

(Note 4) Sleep bit = 0 0.05*VRGO V

NOTES:

3. Power-up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified.

4. The device provides an internal hold time of at least 300ns for the SDA signal to br idge the unidentified region of the falling edge of SCL.

5. Limits established by characterization and are not production tested.

6. Maximum output capacitance = 15pF

Operating Spec ifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating

Conditions, Unless Otherwise Specified. (Continued)

DESCRIPTION SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

ISL9216, ISL9217

11 FN6488.1

November 2, 2007

Wake-up Timing (WKPOL = 0)

Wake-up Timing (WKPOL = 1)

Change in Voltage Source, FET Control

VWKUP2 VWKUP2H

tWKUP tWKUP

<tWKUP

WKUP PIN

WKUP BIT

VWKUP1 VWKUP1H

tWKUP tWKUP

<tWKUP

WKUP PIN

WKUP BIT

AO tVSC tVSC

BIT

DFET (ISL9216 ONLY)

tCO

SDA

SCL

BIT

tCO

DATA

BIT

CFET (ISL9216 ONLY)

tCO

BIT

3BIT

ISL9216, ISL9217

12 FN6488.1

November 2, 2007

Automatic Temperature Scan (ISL9216 only)

Discharge Overcurrent/Short Circuit Monitor (ISL9216 only) (Assumes DENOCD and DENSCD bits are ‘0’)

AUTO TEMP CONTROL

(INTERNAL ACTIVATION)

TEMP3V PIN

TMP3V/13

DELAY TIME = 1ms

635ms

MONITOR TIME = 5ms 3.3V

XOT BIT

EXTERNAL OVER-TEMPERATURE

DELAY TIME = 1ms

FET SHUTDOWN AND CELL BALANCE TURN-OFF

MONITOR TEMP DURING THIS

HIGH IMPEDANCE

TIME PERIOD

THRESHOLD

TEMPERATURE

(IF ENABLED)

VSC

VOCD

tSCD tOCD tSCD

DOC BIT

DSC BIT

TEMP3V

VDSENSE

OUTPUT

3.3V

‘1’

‘0’

DFET

OUTPUT

µC TURNS ON DFET

12V

ISL9216, ISL9217

13 FN6488.1

November 2, 2007

Charge Overcurrent Monitor (ISL9216 only) (Assumes DENOCC bit is ‘0’)

Serial Interface Timing Diagrams

Bus Timing

Symbol Table

VOCC

tOCC

COC BIT

TEMP3V

VCSENSE

OUTPUT

3.3V

‘1’

‘0’

CFET

OUTPUT

µC TURNS ON CFET

12V

tSU:STO

tHIGH

tSU:STA

tHD:STA

tHD:DAT

tSU:DAT

tFtLOW

tBUF

tDH

tAA

SDA INPUT

SDA OUTPUT

SCL

This timing shows the communication with the ISL9216. Communication with the ISL9217 (through the ISL9216) adds some lag time, however,

overall the communication with the ISL9217 meets the same timing requirements as communication with the ISL9216.

WAVEFORM INPUTS OUTPUTS

Must be

steady Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

ISL9216, ISL9217

14 FN6488.1

November 2, 2007

Registers TABLE 1. REGISTERS

ADDR REGISTER READ/WRITE 7 6 5 4 3210

00H Configur ation

Status Read only CU

Cascade U CL

Cascade L Reserved WKUP

WKUP pin

Status

Reserved Reserved Reserved Reserved

01H Operating Status

(Note 9) Read only Reserved Reserved XOT

Ext over

temp

IOT

Int over

Temp

LDFAIL

Load Fail

(VMON)

DSC

Short

Circuit

DOC

Discharge

COC

Charge OC

02H Cell Balance Read/Write CB7ON CB6ON/

WKUPR CB5ON CB4ON CB3ON CB2ON CB1ON Reserved

Cell balance FET control bits (plus WKUP of ISL9217 in cascade)

03H Analog Out Read/Write UFLG1

User Flag 1 UFLG0

User Flag 0 Reserved Reserved AO3 AO2 AO1 AO0

Analog output select bits

04H FET Control Read/Write SLEEP

Force

Sleep

(Note 10)

LDMONEN

Turn on

VMON

connection

Reserved Reserved Reserved Reserved CFET

Turn on

Charge

FET

(Note 11)

DFET

Turn on

Disharge

FET

(Note 11)

05H Discharge Set Read/Write

(Write only if

DISSETEN bit

set)

DENOCD OCDV1 OCDV0 DENSCD SCDV1 SCDV0 OCDT1 OCDT0

Turn off

automatic

OCD

control

Configure Overcurrent

Discharge Threshold Turn off

automatic

SCD control

Configure Short Circuit

Discharge Threshold Configure Overcurrent

Discharge Time-out

06H Charge Set Read/Write

(Write only if

CHSETEN bit

set)

DENOCC OCCV1 OCCV0 SCLONG

Long Short-

circuit delay

CTDIV

Divide

charge

time by 32

DTDIV

Divide

discharge

time by 64

OCCT1 OCCT0

Turn off

automatic

OCC

control

Configure Overcurrent

Charge Threshold Configure Overcurrent

Charge Time-out

07H Feature Set Read/Write

(Write only if

FSETEN bit

set)

ATMPOFF

Turn off

automatic

external

temp scan

DIS3

Disable 3.3V

reg. (device

requires

external

3.3V)

TMP3ON

Temp 3.3V

keep on

DISXTSD

Disable

external

thermal

shutdown

DISITSD

Disable

internal

thermal

shutdown

POR

Force POR DISWKUP

Disable

WKUP pin

WKPOL

Wake-up

Polarity

08H Write Enable Read/Write FSETEN

Enable

Feature

Set writes

CHSETEN

Enable

Charge Set

writes

DISSETEN

Enable

Discharge

Set writes

UFLG3

User Flag 3 UFLG2

User Flag 2 Reserved Reserved Reserved

09H:

FFH Reserved NA RESERVED

NOTES:

7. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.

8. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, 6, 7, and 8: write a reserved bit

with the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.

9. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.

10. This SLEEP bit is cleared on initial power-up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when

WKPOL = ”0”), and by writing a “0” to the location with an I2C command.

11. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns

off the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET

drive output circuit (though not the actual voltage at the output pin).

12. The shaded registers are not used in the ISL9217 device. Shaded status registers return ‘0’ when read. Shaded “read/write” registers can be read

and written, but they provide no functionality. When writing to the shaded areas in the ISL9217, the locations must be written as “0”.

ISL9216, ISL9217

15 FN6488.1

November 2, 2007

Status Registers TABLE 2. CONFIGURATION STATUS REGISTER (ADDR: 00H)

BIT FUNCTION DESCRIPTION

7CU

Cascade U Indicates the device is an ISL9217. This bit is set in hardware and cannot be changed.

6CL

Cascade L Indicates the device is an ISL9216. This bit is set in hardware and cannot be changed.

5SA Reserved for ISL9208 devices.

4WKUP

W ake-up Pin S tatus This bit is set and reset by hardware.

When ‘WKPOL’ is HIGH,

’WKUP’ HIGH = WKUP pin > Threshold voltage

‘WKUP’ LOW = WKUP pin < Threshold voltage

When ‘WKPOL’ is LOW

’WKUP’ HIGH = WKUP pin < Threshold voltage

‘WKUP’ LOW = WKUP pin > Threshold voltage

3 RESERVED Reserved for future expansion.

2 RESERVED Reserved for future expansion.

1 RESERVED Reserved for future expansion.

0 RESERVED Reserved for future expansion.

TABLE 3. OPERATING STATUS REGISTER (ADDR : 01H)

BIT FUNCTION DESCRIPTION

7 RESERVED Reserved for future expansion.

6 RESERVED Reserved for future expansion.

5XOT

Ext Over-temp

(ISL9216 only)

This bit is set to “1” when the external thermistor indicates an over-temperature condition. If the temperature condition

has cleared, this bit is reset when the register is read.

4IOT

Int Over-temp This bit is set to “1” when the internal thermistor indicates an over-temperature condition. If the temperature condition

has cleared, this bit is reset when the register is read.

3 LDFAIL

Load Fail (VMON)

(ISL9216 only)

When the function is enabled, this bit is set to “1” by hardware when a discharge overcurrent or short circuit condition

occurs and the load remains heavy. When the load fail condition is cleared or under a light load, the bit is reset when the

2DSC

Short Circuit

(ISL9216 only)

This bit is set by hardware when a short circuit condition occurs during discharge. When the discharge short circuit

condition is removed, the bit is reset when the register is read.

1DOC

Discharge OC

(ISL9216 only)

This bit is set by hardware when an overcurrent condition occurs during discharge. When the discharge overcurrent

condition is removed, the bit is reset when the register is read.

0COC

Charge OC

(ISL9216 only)

This bit is set by hardware when an overcurrent condition occurs during charge. When the charge overcurrent condition

is removed, the bit is reset when the register is read.

ISL9216, ISL9217

16 FN6488.1

November 2, 2007

Control Registers TABLE 4. CELL BALANCE CONTROL REGISTER (ADDR: 02H)

CONTROL REGISTER BITS

BALANCE

BIT 7

CB7ON

BIT 6

CB6ON

WKUPR BIT 5

CB5ON BIT 4

CB4ON BIT 3

CB3ON BIT 2

CB2ON BIT 1

CB1ON

x xxxxx1Cell1 ON

x xxxxx0Cell1 OFF

xxxxx1xCell2 ON

xxxxx0xCell2 OFF

xxxx1xxCell3 ON

xxxx0xxCell3 OFF

x xx1xxxCell4 ON

x xx0xxxCell4 OFF

x x1xxxxCell5 ON

x x0xxxxCell5 OFF

x 1 x x x x x Cell6 ON/WKUPR On (Note 13)

x 0 x x x x x Cell6 OFF/WKUPR OFF (Note 13)

1 x x x x x x Cell7 ON (ISL9217 only)

0 x x x x x x Cell7 OFF (ISL9217 only)

Bit 0 RESERVED Reserved for future expansion

NOTE:

13. WKUPR Pin refers to the ISL9216

ISL9216, ISL9217

17 FN6488.1

November 2, 2007

TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)

BITS FUNCTION DESCRIPTION

7UFLG1

User Flag 1 General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.

6UFLG0

User Flag 0 General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.

5:4 RESERVED Reserved for future expansion

BIT 3

AO3 BIT 2

AO2 BIT 1

AO1 BIT 0

AO0 OUTPUT VOLTAGE

0 0 0 0 No Output (low power state)

0 0 0 1 VCELL1

0 0 1 0 VCELL2

0 0 1 1 VCELL3

0 1 0 0 VCELL4

0 1 0 1 VCELL5

0 1 1 0 VCELL6

0 1 1 1 VCELL7

1 0 0 0 External Temperature

1 0 0 1 Internal Temperature

1x1 xReserved

11x xReserved

TABLE 6. FET CONTROL REGISTER (ADDR: 04H)

BIT FUNCTION DESCRIPTION

7 SLEEP

Force Sleep Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET outputs, the cell balance

outputs and the voltage regulator. This also resets the CFET, DFET, and CB7ON:CB1ON bits. The SLEEP bit is

automatically reset to “0” when the device wakes up. This does not reset the AO3:AO0 bits.

6LDMONEN

Turn on VMON

connection

(ISL9216 only)

Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON circuit. As such, the

microcontroller has full control of the operation of this circuit.

5:2 RESERVED Reserved for future expansion.

1CFET

(ISL9216 only) Setting this bit to “1” turns on the charge FET.

Setting this bit to “0” turns off the charge FET.

This bit is automatically reset in the event of a charge overcurrent condition, unless the automatic response is disabled

by the DENOCC bit.

0DFET

(ISL9216 only) Setting this bit to “1” turns on the discha rge FET.

Setting this bit to “0” turns off the discharge FET.

This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the

automatic response is disabled by the DENOCD or DENSCD bits.

ISL9216, ISL9217

18 FN6488.1

November 2, 2007

Configuration Registers

The device is configured for specific application req uiremen ts using the Configuration Registers. The configuration register

consists of SRAM memory. This memory is powered by the RGO output. In a sleep condition, an internal switch powers the

contents of these registers from the VCELL1 input.

TABLE 7. DISCHARGE SET CONFIGUR ATION REGISTER (ADDR: 05H)

SETTING FUNCTION

Bit 7 DENOCD

Turn off automatic OCD control

(ISL9216 only)

When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.

When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.

In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.

Bit 6

OCDV1 Bit 5

OCDV0 Discharge Overcurrent Threshold

(ISL9216 only)

00 V

OCD = 0.10V

01 V

OCD = 0.12V

10 V

OCD = 0.14V

11 V

OCD = 0.16V

Bit 4 DENSCD

Turn off automatic SCD control

(ISL9216 only)

When set to ‘0’, a discharge short circuit condition turns off the FETs.

When set to ‘1’, a discharge short circuit condition will not automatically turn off the FETs.

In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.

Bit 3

SCDV1 Bit 2

SCDV0 Discharge Short Circuit Threshold

(ISL9216 only)

00 V

SCD = 0.20V

01 V

SCD = 0.35V

10 V

SCD = 0.65V

11 V

SCD = 1.20V

Bit 1

OCDT1 Bit 0

OCDT0 Discharge Overcurrent Time-out

(ISL9216 only)

00 t

OCD = 160ms (2.5ms if DTDIV = 1)

01 t

OCD = 320ms (5ms if DTDIV = 1)

10 t

OCD = 640ms (8ms if DTDIV = 1)

11 t

OCD = 1280ms (16ms if DTDIV = 1)

ISL9216, ISL9217

19 FN6488.1

November 2, 2007

TABLE 8. CHARGE/TIME SCALE CONFIGURATION REGISTER (ADDR: 06H)

SETTING FUNCTION

Bit 7 DENOCC

Turn off automatic OCC control

(ISL9216 only)

When set to ‘0’, a charge overcurrent condition automatically turns off the FETs.

When set to ‘1’, a charge overcurrent condition will not automatically turn off the FETs.

In either case, this condition sets the COC bit, which also turns on the TEMP3V output.

Bit 6

OCCV1 Bit 5

OCCV0 Charge Overcurrent Threshold

(ISL9216 only)

00 V

OCD = 0.10V

01 V

OCD = 0.12V

10 V

OCD = 0.14V

11 V

OCD = 0.16V

Bit 4 SCLONG

Short circuit long delay

(ISL9216 only)

When this bit is set to ‘0’, a short circuit needs to be in effect for 100µs before a shutdown

begins. When this bit is set to ‘1’. a short circuit needs to be in effect for 10ms before a

shutdown begins.

Bit 3 CTDIV

Divide charge time by 32

(ISL9216 only)

When set to “1”, the charge overcurrent delay time is divided by 32.

Bit 2 DTDIV

Divide discharge time by 64

(ISL9216 only)

When set to “1”, the discharge overcurrent delay time is divided by 64.

Bit 1

OCCT1 Bit 0

OCCT0 Charge Overcurrent Time-out

(ISL9216 only)

00 t

OCC = 80ms (2.5ms if CTDIV=1)

01 t

OCC = 160ms (4ms if CTDIV=1)

10 t

OCC = 320ms (8ms if CTDIV=1)

11 t

OCC = 640ms (16ms if CTDIV=1)

TABLE 9. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H)

BIT FUNCTION DESCRIPTION

7 ATMPOFF

Turn off automatic external temp scan

(ISL9216 only)

When set to ‘1’ this bit disables the automatic temperature scan. When set to ‘0’, the temperature

is turned on for 5ms in every 640ms.

6DIS3

Disable 3.3V reg Setting this bit to “1” disables the internal 3.3V regulator. Setting this bit to “1” requires that there

be an external 3.3V regulator connected to the RGO pin.

5TMP3ON

Temp 3.3V keep on Setting this bit to “1” keeps ON the 3.3V output to the external temperature sensor.

4 DISXTSD

Disable external thermal shutdown

(ISL9216 only)

Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in

response to an out of limit external temperature. While the automatic response is disabled, the

microcontroller can initiate a shutdown based on the XOT flag.

3 DISITSD

Disable internal thermal shutdown Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in

response to an out of limit internal temperature. While the automatic response is disabled, the

microcontroller can initiate a shutdown based on the IOT flag.

2POR

Force POR Setting this bit to “1” forces a POR condition. This resets all internal registers to zero.

1 DISWKUP

Disable WKUP pin Setting this bit to “1” disables the WKUP pin function.

CAUTION: Setting this pin to ‘1’ prevents a wake-up condition. If the device then goes to sleep, it

cannot be waken without a communication link that resets this bit, or by power cycling the device.

0WKPOL

Wake-up Polarity Setting this bit to “1” sets the device to wake-up on a rising edge at the WKUP pin.

Setting this bit to “0” sets the device to wake-up on a falling edge at the WKUP pin.

CAUTION: Setting this pin to ‘1’ in the ISL9217 prevents a wake-up condition. If the device then

goes to sleep, it cannot be waken without power cycling the device.

ISL9216, ISL9217

20 FN6488.1

November 2, 2007

.TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H)

BIT FUNCTION DESCRIPTION

7 FSETEN

Enable discharge set writes When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the

Feature Set register (Addr: 07H). Default on initial power-up is “0”.

6 CHSETEN

Enable charge set writes

(ISL9216 only)

When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the

Feature Set register (Addr: 06H). Default on initial power-up is “0”.

5 DISSETEN

Enable discharge set writes

(ISL9216 only)

When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents

writes to the Feature Set register. Default on initial power-up is “0”.

4UFLG3

User Flag 3 General purpose flag usable by microcontroller software. This bit is battery backed up, even when

RGO turns off.

3UFLG2

User Flag 3 General purpose flag usable by microcontroller software. This bit is battery backed up, even when

RGO turns off.

2 RESERVED Reserved for future expansion.

1 RESERVED Reserved for future expansion.

0 RESERVED Reserved for future expansion.

FIGURE 1. BATTERY CONNECTION OPTIONS

NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

12 CELLS

CB7

CB6

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

8 CELLS

CB7

CB6

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

11 CELLS

CB7

CB6

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB5

CB4

CB3

CB2

CB1

9 CELLS

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

10 CELLS

CB7

CB6

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB5

CB4

CB3

CB2

CB1

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

VSS

CB7

CB6

CB5

CB4

CB3

CB2

CB1 AO

ISL9216, ISL9217

21 FN6488.1

November 2, 2007

Device Description

Design Theory

Instructed by the microcontroller, the ISL9216 and ISL9217

chip set performs cell voltage monitoring and cell balancing

operations. The ISL9216 has automatic overcurrent and

short circuit monitoring, and shut-down with built-in

selectable time delays. The ISL9216 also provides automatic

turn off of the power FETs and cell balancing FETs in an

over-temperature condition. All automatic functions of the

ISL9216 can be turned off and the microcontroller can

manage the operations through software.

Battery Connection

The ISL9216 and ISL9217 support packs of 8 to 12 series

connected Li-ion cells. Connectio n guidelines for each cell

combination are shown in Figure 1.

System Power-Up/Pow er- Down

The ISL9216 and ISL9217 power-up when the voltages on

their VCELL1, VCELL2, VCELL3, and VCC pins all ex ceed

their POR threshold. At this time, the devices each wake-up

and turn on their RGO output.

The regulator circuit provides 3.3VDC at pin RGO. It does

this by using a control voltage on the RGC pin to dri v e an

external NPN transistor (See Figure 2). For the ISL9216, the

transistor should have a beta of at least 70 to provide ample

current to the device and external circuits and should have a

VCE of greater than 60V (preferably highe r) for a 12 ce ll

pack. For the ISL9217, the transistor selection is not as

critical because it will likely not drive any extern al circuits,

however, it should be rated with a VCE greater than 50V.

The voltage at the emitter of the NPN transistor is monitored

and regulated to 3.3V by the control signal RGC. RGO also

powers most of the ISL9216 and ISL9217 internal circuits. A

500Ω resistor is recommended in the collector of each NPN

transistor to minimize initial current surge when the regulator

turns on.

Once powered up, the devices remain in a wake-up state

until put to sleep by the microcontroller (typically when the

cells drop too low in voltage) or until the VCELL1, VCELL2,

VCELL3, or VCC voltages drop below their POR threshold.

WKUP Pin Operation

There are two ways to design a wake-up of the ISL9216. In

an active LOW connection (WKPOL = ’0’ - default), the

device wakes up when a charger is connected to the pack.

This pulls the WKUP pin low when compared to a reference

based on the VCELL1 voltage. In an active HIGH connection

(WKPOL = ‘1’) the device wakes up when then WKUP pin is

pulled high by a connection through an external switch. See

Figure 3.

Once the ISL9216 wakes up, the RGO power s up the

microcontroller. The microcontroller then wakes up the

ISL9217 by setting the WKUPR bit in the ISL9216. The

WKUPR pin of the ISL9216 connects to the ISL9217 WKUP

pin. When the ISL9216 WKUPR bit is set to “1”, the ISL9217

WKUP pin pulls low and the ISL9217 wakes up. Because of

this operation, it is important that the WKPOL bit of the

ISL9217 remain in the default state (ISL9217 WKPOL = 0).

Protection Functions

In the default, recommended condition, the ISL9216

automatically responds to discharge overcurrent, discharge

short circuit, charge overcurrent, internal over-temperature,

and external over-temperature. The designer can set

optional over-ri de conditions that allow the response to be

dictated by the microcontroller. These are discussed in the

following section.

RGC

RGO

VSS

VCC

FIGURE 2. VOLTAGE REGULATOR CIRCUITS

RGC

RGO

VSS

VCC

3.3V

GND

500 500

ISL9216

FIGURE 3. WAKE-UP CONTROL CIRCUITS

VSS

330k*

* INTERNAL RESISTOR

ONLY CONNECTED WHEN

WKPOL = 1.

WKUP

WKPOL

WKUP

(STATUS)

(CONTROL)

WAKE-UP

CIRCUITS

ISL9216, ISL9217

22 FN6488.1

November 2, 2007

OVERCURRENT SAFETY FUNCTIONS

The ISL9216 continually monitors the discharge current by

monitoring the voltage at the CSENSE and DSENSE pins. If

that voltage exceeds a selected value for a time exceeding a

selected delay , then the de vic e enters an overcurrent or short

cir c uit protection mod e. In these modes, the ISL9216

automatically turns off both power FETs and hence prevents

current from flowing through the terminals P+ and P-.

The voltage thresholds and the response times of the

overcurrent protection circuits are selectable for discharge

overcurrent, charge overcurrent, and discharge short circuit

conditions. The specific settings are determined by bits in

the “DISCHARGE SET CONFIGUR AT ION REGISTER

(ADDR: 05H)” on page 18, and “CHARGE/TIME SCALE

CONFIGURATION REGISTER (ADDR: 06H)” on page 19.

(See also “REGISTERS” on page 14).

In an overcurrent condition, the ISL9216 automatically turns off

the voltage on CFET and DFET pins. The DFET output drives

the discharge FET gate low , turning off the FET quickly. The

CFET output turns off and allows the gate of the charge FET to

be pulled low through a resistor .

By turning off the FETs the ISL9216 prevent s damage to the

battery pack caused by excessive current into or out of the cells

(as in the case of a faulty charger or short circuit condition).

When the ISL9216 detects a discharge overcurrent condition,

the ISL9216 turns off both power FETs and sets the DOC bit.

(When the FETs are turned off, the DFET and CFET bits are

also reset). The automatic response to overcurrent during

discharge is prevented by setting the DENOCD bit to “1”. The

external microcontroller can turn on the FETs at any time to

recover from this condition, but it would usually turn on the load

monitor function (by setting the LDMONEN bit) and monitor the

LDFAIL bit to detect that the overcurrent condition has been

removed.

When the ISL9216 detects a discharge short circuit condition,

both power FETs are turned off and DSC bit is set. (When the

FETs are turned off, the DFET and CFET bits are also reset).

The automatic response to short circuit during discharge is

prevented by setting the DENSCD bit to “1”. The external

microcontroller can turn on the FET s at any time to recover from

this condition, but it would usually turn on the load monitor

function (by setting the LDMONEN bit) and monitor the LDF AIL

bit to detect that the overcurrent condition has been removed.

When the ISL9216 detects a charge overcurrent condition, both

power FETs are turned off and COC bit is set. (When the FETs

are turned off, the DFET and CFET bit s are also reset). The

automatic response to overcurrent during discharge is

prevented by setting the DENOCC bit to “1”. The external

microcontroller can turn on the FET s at any time to recover from

this condition, but it would usually wait to do this until the cell

voltages are not over charged and that the overcurrent

condition has been removed. Or, the microcontroller could wait

until the pack is removed from the charger and then re-

attached.

An alternat ive met hod o f provi ding the protection function, if

desired by the designer, is to turn of f the automatic safety

response. In this case, the ISL9216 device still monitors the

conditions and sets the status bits, but takes no action in

overcurrent or short circuit conditions. Safety of the pack

depends, instead, on the microcontroller to send commands to

the ISL9216 to turn of f the FETs.

To facilitate a microcontroller response to an overcurrent

condition, especially if the microcontroller is in a low power

state, a charge overcurrent flag (COC), a discharge overcurrent

flag (DOC), or the short circuit flag (DSC) being set causes the

ISL9216 TEMP3V output to turn on and pull high. (See

Figure 5). This output can be used as an external interrupt by

the microcontroller to wake-up quickly to handle the overcurrent

condition.

LOAD MONITORING

The load monitor function in the ISL9216 (see Figure 4) is used

primarily to detect that the load has been removed following an

overcurrent or short circuit condition during discharge. This can

be used in a control algorithm to prevent the FETs from turning

on while the overload or short circuit condition remains.

The load monitor can also be used by the microcontroller

algorithms after an undervoltage condition on any cells

causes the FETs to turn off. Use of the load monitor prevents

the FETs from turning on while the load is still present. Th is

minimizes the possible “oscillations” that can occur when a

load is applied in a low capacity pack. It can also be part of a

system protection mechanism to prevent the load from

turning on automatically - i.e. some action must be taken

before the pack is again turned on.

FIGURE 4. LOAD MONITOR CIRCUIT

VSS

LDMONEN

VMON

VREF

LDFAIL

ISL9216

P-

=1 if VMON > VVMONH

=0 if VMON ≤ VVMONL

VSS

P+

OPEN

DFET

36V

ISL9216, ISL9217

23 FN6488.1

November 2, 2007

The load monitor circuit can be turned on or off by the

microcontroller. It is normally turned off to minimize current

consumption. It must be acti vated by the external

microcontroller for it to operate. The circuit works by

internally connecting the VMON pin to VSS through a

resistor. Th e circuit operates as shown in Figure 4.

In a typical pack operation, when an overcurrent or short

circuit event happens, the DFET turns off, opening the

battery circuit to the load. At this time, the RL is small and

the load monitor is initially off. In this condition, the voltage at

VMON could rise to nearly the pack voltage. However, since

in most configurations, this voltage would exceed the

maximum limits on the VMON pin, a series zener diode is

required.

Once the power FETs turn off, the microcontroller activates

the load monitor by setting the LDMONEN bit. This turns on

an internal FET that adds a pull-down resistor to the load

monitor circuit. While still in the overload condition the

combination of the load resistor, an external adjustment

resistor (R1), the zener diode, and the internal load monitor

resistor form a voltage divider . R1 is chosen so that when the

load is released to a sufficient level, the LDFAIL condition is

reset.

OVER-TEMPERATURE SAFETY FUNCTIONS

External Temperature Control

The external temperature is monitore d by using a voltage

divider consisting of a fixed resistor and a thermistor. This

divider is powered by the ISL9216 TEMP3V output. This

output is normally controlled so it is on for only short periods

to minimize current consumption.

Without microcontroller intervention, the ISL9216

continuously turns on TEMP3V output (and the external

temperature monitor) for 5ms every 640ms. In this way, the

external temperature is monitored even if the microcontroller

is asleep. If the ATMPOFF bit is set, this automatic

temperature scan is turned off.

When the TEMP3V output turns on, the ISL9216 waits 1ms

for the temperature reading to stabilize, then compares the

external temperature voltage with an internal voltage divider

that is set to TEMP3V/13. When the thermistor voltage is

below the reference threshold after the delay, an external

temperature fail condition exists. To set the external over-

temperature limit, set the value of RX resistor to the 12 times

the resistance of the thermistor at the over-temperature

threshold.

The TEMP3V output pin also turns on when the

microcontroller sets the AO3 :AO0 bit s to select that the

external temperature volt age. This causes the TEMPI volt age

to be placed on AO and activates (after 1ms) the over-

temperature detection. As long as the AO3 :AO0 bits point to

the external temperature, the TEMP3V output remains on.

Because of the manual scan of the temperature, it may be

desired to turn off the automatic scan, although they can be

used at the same time without interference. To turn off the

automatic scan, set the ATMPOFF bit.

The microcontroller can over-ride both the automatic

temperature scan and the microcontroller controlled

temperature scan by setting the TEMP3ON configuration bit.

This turns on th e TEMP3V output to keep the te mperature

control voltage on all the time, for a continuous monitoring of

an over-temperature condition. This likely will consume a

significant amount of current, so this feature is us ua l l y us e d

for special or test purposes.

Protection

As a default, when the ISL9216 detects an internal or

external over-temperature condition, the FETs are turned off,

the cell balancing function is disabled, and the IOT bit or

XOT bit (respectively) is set.

Turning off the FETs in the event of an over-temperature

condition prevents continued discharge or charge of the cells

when they are over heated. Turning off the cell balancing in

the event of an over-temperature condition prevents damage

to the IC in the event too many cells are being balanced,

causing too much power dissipation in the ISL9216.

635ms

5ms

FIGURE 5. EXTERNAL TEMPERA TURE MONITORING AND

CONTROL (ISL9216 ONLY)

RGO

TEMP3V

TEMPI

VSS

I2C

MUX

I2C

TEMP

MONITOR

TEMP FAIL

INDICATOR

VSS (ON)

REGISTERS

TMP3ON

AO3:AO0

DECODE

OSC

ATMPOFF

CHARGE OC

DISCHARGE OC

DISCHARGE SC

µC

XOT

12R

1ms

DELAY

EXTERNAL

EXT TEMP

OVERCURRENT

PROTECTION CIRCUITS

ISL9216

ISL9216, ISL9217

24 FN6488.1

November 2, 2007

In the event of an automatic over-temperature condition, cell

balancing is prevented and FETs are held off until the

temperature drops back below the temperature recovery

threshold. During this temperature shutdown period, the

microcontroller can monitor the internal temperature through

the analog output pi n (AO), but any writes to the CFET bit,

DFET bit, or cell balancing bits are ignored

The automatic response to an internal over-temperature is

prevented by setting the DISITSD bit to “1”. The automatic

response to an external over-temperature is prevented by

setting the DISXTSD bit to “1”. In either case, it is important

for the microcontroller to monitor the internal and external

temperature to protect the pack and the electronics in an

over-temperature condition.

Analog Multiplexer Selection

The ISL9216 and ISL9217 devices can be used to externally

monitor individual battery cell voltages and temperatures.

Each quantity can be monitored at the analog output pin (AO)

and is selected using the I2C interface. See Figure 6.

To monitor the voltages on the ISL9217 inputs, set the

ISL9216 to monitor VCELL6, then set the ISL9217 to the

desired VCELL input. The ISL9216 and ISL9217 VCELL

input voltages are divided by 2, except for the ISL9216

VCELL6 input. This is a divide by 1 input. In this way, the

value read at the ISL9216 AO output is always a divide by 2

of the original cell voltage.

VOLTAGE MONITORING

Since the voltage on each of the Li-Ion Cells are normally

higher than the regulated supply vo ltage, it is necessary to

both level shift and divide the voltage. To get into the voltage

range required by the external A/D converter, the voltage

level shifter divides the cell voltage by 2. Therefore, a Li-Ion

cell with a voltage of 4.2V is reported via the AO pin to be

2.1V.

TEMPERATURE MONITORING

The voltage representing the external temperature applied at

the TEMPI terminal is directed to the AO terminal through a

MUX, as selected by the AO control bits (see Figures 5

and 6). The external temperature voltage is not divided by 2

as are the cell voltages. Instead it is a direct reflection of the

voltage at the TEMPI pin.

A similar operation occurs when monitoring the internal

temperature through the AO output, except there is no

external “calibration” of the voltage associated with the

internal temperature. For the internal temperature

monitoring, the voltage at the output is linear with respect to

temperature. (See “Operating Specifications” on page 6 for

information about the output voltage at +25°C and the output

slope relative to temperature).

Cell Balancing

OVERVIEW

A typical ISL9216 and ISL921 7 Li-ion battery pack consists

of 8 to 12 cells in series, with one or more cells in parallel.

This combination gives both the voltage and power

necessary for power tools, e-bikes, electric wheel chairs,

portable medical equipment, and battery powered industrial

applications. While the series/parallel combination of Li-ion

cells is common, the configuration is not as efficient as it

could be, because any capacity mismatch between series-

connected cells reduces the overall pack capacity. This

mismatch is greater as the number of series cells and the

load current increase. Cell balancing techniques increase

the capacity and the operating time of Li-ion battery packs.

VCELL4

VSS

SCL I2C

FIGURE 6. ANALOG OUTPUT MONITORING DIAGRAM

REGS

AO3:AO0

DECODE

VCELL1

VCELL5

SDA

LEVEL

SHIFT

LEVEL

SHIFT

LEVEL

SHIFT

LEVEL

SHIFT

TEMPI

INT

TEMP

MUX EXT TEMP.

(ISL9216 ONLY)

VCELL2

VSS

I2C

REGS

AO3:AO0

DECODE

VCELL1

VCELL6

VC7/VCC

LEVEL

SHIFT

LEVEL

SHIFT

LEVEL

SHIFT

LEVEL

SHIFT

INT

TEMP

MUX

VCELL6

VCC

LEVEL

SHIFT ISL9216

ISL9217

ISL9216, ISL9217

25 FN6488.1

November 2, 2007

DEFINITION OF CELL BALANCING

Cell balancing is defined as the application of differential

currents to individual cells (or combinations of cells) in a

series string. Normally, of course, cells in a series string

receive identical currents. A battery pack requires additional

components and circuitry to achieve cell balancing. For the

ISL9216 and ISL9217 devices, th e only external

components required are balancing resistors.

CELL BALANCE OPERATION

Cell balancing is accomplished through a microcontroller

algorithm. This algorithm compares the cell voltages (a

representation of the pack capacity) and turns on balancing

for the cells that have the higher voltages. There are many

parameters that should be considered when writing this

algorithm. An example cell balancing algorithm is available

in the ISL9216EVAL1Z evaluation kit.

The microcontroller turns on the specific cell balancing by

setting a bit in the Cell Balance Register. Each bit in the

the bit is set, an internal cell balancing FET turns on. This

shorts an external resistor across the specified cell. The

maximum current that can be drawn from (or bypassed

around) the cell is 200mA. This current is set by selecting

the value of the external resistor . Figure 7 shows an example

with a 200mA (maximum) balancing current.

With lower balancing current, more balancing FETs can be

turned on at once, without exceeding the device power

dissipation limits or generating excessive balancing current

that will heat the external resistor.

External VMON/CFET Protection Mechanisms

When there is a single charge/discharge path, a blocking

diode is required in the ISL9216 VMON to P- path. See D1 in

Figure 8. This diode is to protect against a negative voltage

on the VMON pin that can occur when the FETs are off and

the charger connects to the pack. This diode is not needed

when there is a separate charge and discharge path,

because the voltages on P- (discharge) are likely always

positive.

For the cascaded combination of ISL9216 and ISL9217, a

zener diode (D2 in Figure 8) needs to be in the ISL 9216

VMON path to the P- pin to protect the ISL9216 from an

overvoltage condition when the FETs open due to a short

circuit or overcurrent condition.

With the single set of charge/discharge FETs, the ISL921 6

CFET pin needs to be protected in th e event of an over-

current or short circuit shut-down. When this hap pens, the

FET opens suddenly. The flyback voltage from the motor

windings will likely exceed the maximum input voltage on the

CFET pin. So, when operating in this configuration, an

additional external series diode must be placed between the

CFET pin of the ISL9216 and the gate of the Charge FET.

See Diode D3 in Figure 8. This will reduce the CFET gate

voltage, but not significantly.

Finally, in all co nfigurations, to protect the Charge FET itself

in the event of a large negative voltage on the Pack- pin,

zener diode D4 is added. The large negative voltage can

occur when the P- pin goes significantly negative, while the

CFET pin is being internally clamped at VSS. The zener

voltage of D4 should be less than the VGS(max)

specification of the FET.

CELL

ISL9216, ISL9217

BALANCE

REG

VC7/VCC

VSS

FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH

100mA BALANCING CURRENT

7654321

21Ω

200mA

21Ω

VCELL1

CB1

CB7 MUST ASSUME ZERO rDS(ON)

FOR MAX CURRENT CALCULATION

PACK-

PACK+

ISL9216

ISL9217

CFET

DFET

D2D1

VMON

FIGURE 8. USE OF A DIODES FOR PROTECTING THE

CFET AND VMON PINS.

10M

ISL9216, ISL9217

26 FN6488.1

November 2, 2007

User Flags

The ISL9216 and ISL9217 each contain four flags in the

purpose indicators. These bits are designated UFLG3, UFLG2,

UFLG1, and UFLG0. The microcontroller can set or reset these

bits by writing into the appropriate register .

The user flag bits are battery backed up, so the content s

remain even after a sleep mode. However , if the mirocontroller

sets the POR bit to force a power on reset, all of the user flags

will also be reset. In additio n, if the voltage on cell 1 ever drops

below the POR voltage , the contents of the user flags (as well

as all other register values) could be lost.

Serial Interface

INTERFACE CONVENTIONS

The device supports a bi-directional bus oriente d protocol.

The protocol defines any device that sends data onto the

bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is called the

master and the device being controlled is called the slave.

The master always initiates data transfers, and provides the

clock for both transmit and receive operations. Therefore ,

the ISL9216 and ISL9217 devices operate as slaves in all

applications.

When sending or receiving data, the convention is the most

significant bit (MSB) is sent first. So, the first address bit sent

is bit 7.

CLOCK AND DATA

Data states on the SDA line can change only while SCL is

LOW . SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. See Figure 9.

START CONDITION

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. See Figure 10.

STOP CONDITION

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the devi ce

into the Standby power mode after a read sequence. A stop

condition is only issued after the transmitting device has

released the bus. See Figure 10.

ACKNOWLEDGE

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, releases the bus after transmitting 8-bits.

During the ninth clock cycle, the receiver pulls the SDA line

LOW to acknowledge that it received the 8-bits of data. See

Figure 11.

The device responds with an acknowledge after recognition

of a start condition and the correct slave byte. If a write

operation is selected, the device responds with an

acknowledge after the receipt of each subsequent 8-bits.

The device acknowledges all incoming data and address

bytes, except for the slave byte when the contents do not

match the devices internal pattern.

In the read mode, the device transmits 8-bits of data,

releases the SDA line, then mo nitors the line for an

acknowledge. If an acknowledge is detected and no stop

condition is generated by the master, the device will

continues to transmit data. The device terminates further

data transmissions if an acknowledge is not detected. The

master must then issue a stop condition to return th e d evice

to Standby mode and place the device into a known state.

WRITE OPERATIONS

For a write operation, the device requires a slave byte and an

address byte. The slave byte specifies which of the devices (in

a cascade configuration) the master is writing to. The address

specifies one of the registers in that device. After receipt of

each byte, the device responds with an acknowledge, and

awaits the next 8-bits from the master. After the acknowledge,

following the transfer of data, the master terminates the transfer

by generating a stop condition. See Figure 12.

SCL

SDA

DATA

STABLE DATA

CHANGE DATA

STABLE

FIGURE 9. VALID DATA CHANGES ON I2C BUS

SCL

SDA

START STOP

FIGURE 10. I2C START AND STOP BITS

81 9

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START ACKNOWLEDGE

FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER

SCL FROM

MASTER

ISL9216, ISL9217

27 FN6488.1

November 2, 2007

When receiving data from the master, the value in the data

byte is transferred into the register specified by the address

byte on the falling edge of the clock following the 8th data bit.

After receiving the acknowledge after the data byte, the device

automatically increments the address. So, before sending the

stop bit, the master may send additional data to the device

without re-sending the slave and address bytes. After writing to

address 0AH, the address “wraps around’ to address 0.

Read Operations

Read operations are initiated in the same manner as write

operations with the host sending the address where the read

is to start (but no data). Then, the host sends an ACK, a

repeated start and the slave byte with the LSB = 1. After the

device acknowledges the slave byte, the device sends out

one bit of data for each master clock. After the slave sends 8

bits to the master, the master sends a NACK (Not

acknowledge) to the device to indicate that the data transfer

is complete, then the master sends a stop bit. See Figure 13.

After sending the eighth data bit to the master, the device

automatically increments its internal address pointer.

Therefore, the master, instead of sending a NACK and the

stop bit, can send additional clocks to read the conten ts of

the next register - without sending another slave and

address byte.

If the last address read or written is known, the master can

initiate a current address read. In this case, only the slave byte

is sent before data is returned. See Figure 13.

Cascade Operation

When devices are cascaded, the lower device has the I2C

slave address of 0101 000x and the upper device ha s the

address 0101 001x (See Figure 14), but the operation of

cascaded devices is transparent to the microcontroller

master device.

The serial interface between cascaded ISL9216 and

ISL9217 devices has one clock and two data lines. There is

also a high voltage reference for this commication link. See

Figure 15. The interface lines are:

• SCLHV, which is a level shifted clock from the lower

device (ISL9216) to the upper device (ISL9217);

• SDAOHV and SDAO, which send level shifted data out of

the ISL9216 and ISL9217 (respectively); and

• SDAIHV and SDAI, which are level shifted inputs into the

ISL9216 and ISL9217 (respectively).

• HVI2C (ISL9216), which is a reference volt age for the level

shifted interface. This co nnect s to the ISL921 7 RGO pin.

00101 0x0

SLAVE

BYTE REGISTER

ADDRESS DATA

SDA BUS

SIGNALS

FROM THE

SLAVE

SIGNALS

FROM THE

MASTER

FIGURE 12. WRITE SEQUENCE

ISL9216: x = 0 [SLAVE BYTE = 50H]

ISL9217: x = 1 [SLAVE BYTE = 52H]

FIGURE 13. READ SEQUENCE

10101 000

SLAVE

BYTE

DATA

ISL9208: SLAVE BYTE = 010100xH

00101 000

TSLAVE

BYTE REGISTER

ADDRESS

SDA BUS

SIGNALS

FROM THE

SLAVE

SIGNALS

FROM THE

MASTER

10101 000

SLAVE

BYTE

DATA

RANDOM READ CURRENT ADDRESS READ

0 1 0 1 0 0 0 X

ISL9216 SLAVE BYTE

ISL9217 SLAVE BYTE 0 1 0 1 0 0 1 X

FIGURE 14. DEVICE SLAVE BYTES

ISL9216 ISL9217

SDA

SCL

I2C

BLOCK

SCL SCLHV

SDAI

FIGURE 15. I2C CASCADED INTERFACE

1010 000x

1010 001x

SDAOHV

HVI2C

SDAO

SDAIHV

LEVEL

SHIFT

I2C

BLOCK

LEVEL

SHIFT

LEVEL

SHIFT

RGO

ISL9216, ISL9217

28 FN6488.1

November 2, 2007

When data is clo cked into the ISL9216 through the I2C po rt, it

is immediately transferred to the serial cascade port, so both

the ISL9216 and ISL9217 see the slave byte at the same

time. After the 8th slave bit, the device that receives the

correct slave byte sends an acknowledge, w hile the other

device ignores all subsequen t da t a on the serial port until it

receives a stop bit. However, even though the ISL9216

ignores the data, it still passes it through to the ISL9217.

The SDAI and SDAO pins of the ISL9217 need to have pull-

up resistors of approximately 4.7kΩ, since the output drivers

are open-drain devices.

The Discharge Set, Charge Set, and Feature Set

configuration registers are write protected on initial power-

up. In order to write to these registers it is necessary to set a

bit to enable each one. These write ena ble bits are in the

Write Enable register (Address 08H).

Write the FSETEN bit (Addr 8:bit 7) to “1” to change the data

in the Feature Set register (Address 7).

Write the CHSETEN bit (Addr 8:bit 6) to “1” to change the

data in the Feature Set register (Address 6).

Write the DISSETEN bit (Addr 8:bit 5) to “1” to change the

data in the Feature Set register (Address 5).

The microcontroller can reset these bits back to zero to

prevent inadvertent writes that change the operation of the

pack.

Operation State Machine

Figure 16 shows a device state machine which defines how

the ISL9216 and ISL9217 respond to various conditio ns.

Power Fails and one of the supplies, VCC, VCELL1, VCELL2,

and VCELL3 do not meet minimum voltage requirements

WKUP goes above or below

threshold (edge triggered).

[ISL9217 wake-up requires µC

command to ISL9216].

Or, SLEEP bit is set to ‘0’

I2C interface is disabled. Biasing is disabled.

All registers set to default values (All “0”)

POWER-DOWN STATE

I2C interface is enabled. Biasing is enabled.

Voltage Regulator is enabled.

POWER-UP STATE

Voltage Regulator is ON

Logic and registers are powered by RGO

CFET, DFET, Cell balancing output s are all off.

(Require external command to turn on )

Charge and discharge curre nt protection

circuits and temperature protect ion circuits are

active (Default). Overcurrent conditions force

power FETs to turn off. Over-temperature

conditions force power FETs and cell balance

outputs to tu r n of f.

Voltage and temperature monitoring circuits

are awaiting external control.

MAIN OPERATING STATE

Power is applied and all of the supplies, VCC, VCELL1,

VCELL2, and VCELL3 meet minimum voltage requirements

Voltage Regulato r i s OFF

Biasing is OFF

Logic and registers are powered by VCELL1

CFET, DFET, Cell balancing outputs are a ll off.

Charge and discharge current protection

circuits all off.

Voltage and temperature monitoring circuits

are off.

I2C communication is active (if VCELL1 voltage

is high enough to operate wi th external

device.)

SLEEP STATE

SLEEP bit is set to ‘1’

FIGURE 16. DEVICE OPERATION STATE MACHINE

ISL9216, ISL9217

29 FN6488.1

November 2, 2007

Applications Circuits

The following application circuits are ideas to consider when developing a battery pack implementation. There are many more

ways that the pack can be designed.

P-

B-

VSS

µC

P+

SDAI

RESET

A/D INPUT

VCC

I/O

FIGURE 17. 12-CELL CASCADED APPLICATION CIRCUIT WITH INTEGRATED CHARGE/DISCHARGE

LEDs

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VSS

1µF

SCL

SDA

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VCELL6

SDAO

VSS2

I/O

SINGLE WIRE

INTERFACE

NEEDED DURING

DISCHARGE

DSENSE

CFET

DFET

CSENSE

VCELL6

CB6

VC7/VCC

CB7

RESISTORS

OPTIONAL

CHRG

WKUP

RGO

RGC

ISL9217

ISL9216

VC7/VCC

DSREF

VMON

SDAIHV

SCLHV

SDAOHV

MINIMIZE LENGTH

MAXMIZE GAUGE

TEMP3V

TEMPI

THERM

RGO

RGC

INT

SCL

SDA

10M

24V

16V

1.2M

250k

100

3.6V

10M

WKUPR

SCL

HVI2C

500

4.7µF

ISL9216, ISL9217

30 FN6488.1

November 2, 2007

P-

B-

VSS

µC

P+

SCL

RESET

A/D INPUT

VCC

I/O

FIGURE 18. 12-CELL CASCADED APPLICATION CIRCUIT WITH SEPARATE CHARGE/DISCHARGE

LEDs

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VSS

1µF

SCL

SDA

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VCELL6

SDAI

VSS2

I/O

SINGLE WIRE

INTERFACE NOT

NEEDED DURING

DSENSE

CFET

DFET

CSENSE

OPTIONAL

VCELL6

CB6

VC7/VCC

CB7

RESISTORS

OPTIONAL

CHRG

CHG

WKUP

RGO

RGC

ISL9217

ISL9216

VC7/VCC

DSREF

VMON

HVI2C

SDAOHV

SCLHVL

MINIMIZE LENGTH

MAXMIZE GAUGE

TEMP3V

TEMPI

THERM

RGO

RGC

INT

SDA

SCL

10M

24V

16V

100

3.6V

250k

1.2M

10M

WKUPR

SDAO

SDAIHV

500

4.7µF

DISCHARGE

ISL9216, ISL9217

31 FN6488.1

November 2, 2007

P-

B-

VSS

µC

P+

SCL

SDAI

RESET

A/D INPUT

VCC

I/O

FIGURE 19. 12-CELL CASCADED APPLICATION CIRCUIT WITH SEPARATE CHARGE/DISCHARGE AND SWITCH WAKE-UP

LEDs

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VSS

1µF

SCL

SDA

VCELL4

CB4

CB2

VCELL1

VCELL2

CB3

VCELL3

CB1

VCELL5

CB5

VCELL6

SDAO

VSS2

I/O

SINGLE WIRE INTERFAC E

NOT NEEDED DURING

DISCHARGE

DSENSE

CFET

DFET

CSENSE

OPTIONAL

VCELL6

CB6

VC7/VCC

CB7

RESISTORS

OPTIONAL

CHRG

CHG

WKUP

RGO

RGC

ISL9217

ISL9216

VC7/VCC

DSREF

VMON

HVI2C

SDAOHV

SCLHV

MINIMIZE LENGTH

MAXMIZE GAUGE

TEMP3V

TEMPI

THERM

RGO

RGC

SCL

SDA

INT

10M

24V

16V

1.6M

100

3.6V

WKUPR

16V

SDAIHV

500

4.7µF

ISL9216, ISL9217

32 FN6488.1

November 2, 2007

ISL9216, ISL9217

Package Outline Drawing

L24.4x4D

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 10/06

0 . 90 ± 0 . 1

C0 . 2 REF

TYPICAL RECOMMENDED LAND PATTERN

0 . 05 MAX.

( 24X 0 . 6 )

DETAIL "X"

( 24X 0 . 25 )

0 . 00 MIN.

( 20X 0 . 5 )

( 2 . 50 )

SIDE VIEW

( 3 . 8 TYP )

BASE PLANE

TOP VIEW

BOTTOM VIEW

712

24X 0 . 4 ± 0 . 1

4.00

PIN 1 18

INDEX AREA

4.00 2.5

0.50

20X

SEE DETAIL "X"

- 0 . 05

+ 0 . 07

24X 0 . 23

2 . 50 ± 0 . 15

PIN #1 CORNER

(C 0 . 25)

SEATING PL AN E

0.08 C

0.10 C

0.10 M C A B

(4X) 0.15

located within the zone indicated. The pin #1 indentifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6488.1

November 2, 2007

ISL9216, ISL9217

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L32.5x5B

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.18 0.23 0.30 5,8

D 5.00 BSC -

D1 4.75 BSC 9

D2 3.15 3.30 3.45 7,8

E 5.00 BSC -

E1 4.75 BSC 9

E2 3.15 3.30 3.45 7,8

e 0.50 BSC -

k0.25 - - -

L 0.30 0.40 0.50 8

L1 - - 0.15 10

N322

Nd 8 3

Ne 8 3

P- -0.609

θ--129

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.