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ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN6982 CCM Power Factor Correction Controller Features Description Continuous Conduction Mode The FAN6982 is a 14-pin, Continuous Conduction Mode (CCM) PFC controller IC intended for Power Factor Correction (PFC) pre-regulators. The FAN6982 includes circuits for the implementation of leading edge, average current, "boost"-type power factor correction, and results in a power supply that fully complies with the IEC1000-3-2 specification. Power-On Sequence Control Innovative Switching-Charge Multiplier-Divider Average-Current-Mode for Input-Current Shaping TriFault DetectTM Prevent Abnormal Operation for Feedback Loop Soft-Start Capability Brownout Protection Cycle-by-Cycle Peak Current Limiting. Improves Light-Load Efficiency Fulfills Class-D Requirements of IEC 1000-3-2 Wide Range Universal AC Input Voltage A TriFault DetectTM function helps reduce external components and provides full protection for feedback loops such as open, short, and over voltage. An overvoltage comparator shuts down the PFC stage in the event of a sudden load decrease. The RDY signal can be used for power-on sequence control. The EN function can choose to enable or disable the range function. FAN6982 also includes PFC soft-start, peak current limiting, and input voltage brownout protection. Maximum Duty Cycle 97% VDD Under-Voltage Lockout (UVLO) Applications Desktop PC Power Supply Internet Server Power Supply LCD TV/Monitor Power Supply DC Motor Power Supply Ordering Information Part Number FAN6982MY Operating Temperature Range Package Packing Method -40C to +105C 14-Pin Small Outline Package (SOP) Tape & Reel (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com FAN6982 -- CCM Power Factor Correction Controller July 2010 FAN6982 -- CCM Power Factor Correction Controller Application Diagram Figure 1. Typical Application (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 2 14 1 Low-Power Detect Comparator FBPFC 2.5V 0.3V 13 6 EN RM GmI 2 3 0.5V PFC UVP 2.75V/2.5V PFC OVP VDD 28V/27V GmV S VDD OVP R CLR 1.05V/1.9V VRMS Q 10 VIN UVP IM O Gain Modulator 12 Q PFC ILIMIT S SET R CLR Q k 2 x IAC SET VREF OPFC ISENSE Range VDD 7.5V REFERENCE -1.15V VRMS 4 11 IEA VEA PGND VEA 9 Q RM 2.8V ISENSE VDD UVLO RDY 5 7 RT/CT FBPFC 2.4V/1.15V OSCILLATOR SGND 8 FAN6982 -- CCM Power Factor Correction Controller Block Diagram Figure 2. Functional Block Diagram Marking Information F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (M: SOP) P - Y: Green Package M - Manufacture Flow Code Figure 3. Top Mark (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 3 FAN6982 -- CCM Power Factor Correction Controller Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description 1 IEA Output of Current Amplifier. This is the output of the PFC current amplifier. The signal from this pin is compared with sawtooth and determines the pulsewidth for PFC gate drive. 2 IAC Input AC Current. For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 100A. 3 ISENSE 4 VRMS 5 RDY 6 EN 7 RT/CT Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. 8 SGND Signal Ground. 9 PGND Power Ground. 10 OPFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped under 15V to protect the MOSFET. 11 VDD Power Supply. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively. The operating current is lower than 10mA. 12 VREF Reference Voltage. Buffered output for the internal 7.5V reference. 13 FBPFC 14 VEA Current Sense. The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. Line-Voltage Detection. The pin is used for PFC multiplier. Ready Signal. This pin controls the power-on sequence. Once the FAN6982 is turned on and the FBPFC voltage exceeds in 2.4V, the RDY pin pulls LOW impedance. If the FBPFC voltage is lower than 1.15V, the RDY pin pulls HIGH impedance. Enable Range Function. The range function is enabled when EN is connected to VREF. The range function is disabled when EN is connected to GND. Voltage Feedback Input. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Output of Voltage Amplifier. The error-amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground. (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. DC Supply Voltage Max. Unit 30 V VH OPFC, RDY, EN, VREF -0.3 30.0 V VL IAC, VRMS, RT/CT, FBPFC, VEA -0.3 7.0 V 0 VVREF+0.3 V -5.0 VIEA IEA VN ISENSE 0.7 V IAC Input AC Current 1 mA IREF VREF Output Current 5 mA 0.5 A IPFC-OUT PD Peak PFC OUT Current, Source or Sink 800 mW R j-a Thermal Resistance (Junction-to-Air) 104.10 C/W R j-c Thermal Resistance (Junction-to-Case) 40.61 C/W TJ TSTG TL ESD Power Dissipation, TA < 50C Operating Junction Temperature -40 +125 C Storage Temperature Range -55 +150 C +260 C Lead Temperature (Soldering) Electrostatic Discharge Capability Human Body Model, JESD22-A114 4.5 Charged Device Model, JESD22-C101 1.0 FAN6982 -- CCM Power Factor Correction Controller Absolute Maximum Ratings kV Notes: 1. All voltage values, except differential voltage, are given with respect to the GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 Min. Max. Unit -40 +105 C www.fairchildsemi.com 5 Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF. Symbol Parameter Conditions Min. Typ. Max. Units 22 V 30 80 A 2.0 2.3 3.0 mA 10 11 12 V 1.90 V 29 V VDD Section VDD-OP Continuously Operating Voltage IDD ST Startup Current VDD=VTH-ON-0.1V; OPFC Open VDD=13V; OPFC Open IDD-OP Operating Current VTH-ON Turn-on Threshold Voltage VTH Hysteresis VDD-OVP VDD-OVP 1.35 VDD OVP 27 VDD OVP Hysteresis 28 1 V Oscillator fOSC PFC Frequency RT=27k, CT=1000pF (3) fDV Voltage Stability Temperature Stability fDT (3) 67 kHz 11V VDD 22V 2 % -40C ~ +105C 2 % 70 kHz fTV Total Variation Line, Temperature fRV Ramp Voltage Valley-to-Peak IOSC-DIS Discharge Current VRAMP=0V, VRT/CT=2.5V fRANGE Frequency Range tPFC-DEAD 60 64 58 2.8 V 6.5 15.0 mA 50 75 kHz PFC Dead Time RT=27k, CT=1000pF 400 600 800 ns VVREF Reference Voltage IREF=0mA, CREF=0.1F 7.4 7.5 7.6 V VVREF1 Load Regulation of Reference Voltage CREF=0.1F, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20s 30 50 mV VVREF2 Line Regulation of Reference CREF=0.1F, VVDD=11V to 22V Voltage 25 mV 0.5 % FAN6982 -- CCM Power Factor Correction Controller Electrical Characteristics VREF VVREF-DT (3) Temperature Stability Total Variation (3) -40C ~ +105C 0.4 Line, Load, Temperature 7.35 7.65 V Long-Term Stability TJ=125C, 0 ~ 1000HRs 5 25 mV Maximum Current VVREF > 7.35V 5 VRMS-UVL VRMS Threshold Low When VRMS=1.05V at 75 VRMS 1.00 1.05 1.10 V VRMS-UVH VRMS Threshold High When VRMS=1.9V at 85 * 1.414 1.85 1.90 1.95 V 750 850 950 mV 340 410 480 ms 2.3 2.4 2.5 V 1.15 1.25 1.35 V VFBPFC<2.4V 500 nA ISINK=2mA 0.5 V VVREF-TV VVREF-LS IREF-MAX (3) mA Brownout VRMS-UVP tUVP Hysteresis Under-Voltage Protection Debounce Time RDY Section VFBPFC-RD VFBPFC-RD IRDY-LEK VRDY-L FBPFC Voltage Level to Pull Low Impedance with RDY Pin Hysteresis Leakage Current of RDY High Impedance RDY Low Voltage Continued on the following page... (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 6 Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF. Symbol Parameter Conditions Min. Typ. Max. Units 2.45 2.50 2.55 V 90 mho Voltage Error Amplifier VREF AV Reference Voltage At TA=25C 35 42 Transconductance VNONINV=VINV, VVEA=3.75V at TA=25C 50 70 IFBPFC-L Maximum Source Current VFBPFC=2V, VVEA=1.5V 40 50 IFBPFC-H Maximum Sink Current VFBPFC=3V, VVEA=6V GmV IBS Open-Loop Gain (3) -50 Input Bias Current -1 VVEA-H Output High Voltage on VVEA 5.8 VVEA-L Output Low Voltage on VVEA dB A -40 A 1 A 6.0 0.1 V 0.4 V 0.7 V Current Error Amplifier VISENSE AI GmI Input Voltage Range Open-Loop Gain (3) -1.5 At TA=25C 40 50 88 Transconductance VNONINV=VINV, VIEA=3.75V 75 VOFFSET Input Offset Voltage VVEA=0V, IAC Open -10 VIEA-H Output High Voltage VIEA-L Output Low Voltage 6.8 IL Source Current VISENSE= -0.6V, VIEA=1.5V IH Sink Current VISENSE= +0.6V, VIEA=4.0V 35 dB 100 mho 10 mV 7.4 8.0 V 0.1 0.4 50 V FAN6982 -- CCM Power Factor Correction Controller Electrical Characteristics (Continued) A -50 -35 A 2.70 2.75 2.80 V 200 250 300 mV 0.2 0.3 0.4 V PFC OVP Comparator VFBPFC-OVP Over Voltage Protection VFBPFC-OVP PFC OVP Hysteresis Low-Power Detect Comparator VVEA-OFF VEA Voltage Off OPFC PFC Soft-Start VVEA_CLAMP PFC Soft-Start VFBPFC < 2.4V 2.2 2.8 3.3 V VEN-H High Voltage Level of VEN VEN=VVREF 7.4 7.5 7.6 V VEN-L Low Voltage Level of VEN VEN=GND VVRMS-L RMS AC Voltage Low When VVRMS=1.95V at 132VRMS 1.90 1.95 20.00 V VVRMS-H RMS AC Voltage High When VVRMS=2.45V at 150 VRMS 2.40 2.45 2.50 V VEA Low When VVEA=1.95V at 30% Loading 1.90 1.95 2.00 V VEA High When VVEA=2.45V at 40% Loading 2.40 2.45 2.50 V 18 20 22 A EN Section 0 V Range VVEA-L VVEA-H ITC Source Current from FBPFC Continued on the following page... (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 7 Unless otherwise noted; VDD=15V, TA= 25C, TA=TJ, RT=27k, and CT=1000pF. Symbol Parameter Conditions Min. Typ. Max. Units 100 A Gain Modulator IAC GAIN BW VO(GM) Input for AC Current Gain Modulator (3)(4) Multiplier Linear Range 0 IIAC=17.67A, VVRMS=1.080V VFBPFC=2.25V, at TA=25C 7.500 9.000 10.500 IIAC=20A, VVRMS=1.224V VFBPFC=2.25V, at TA=25C 6.367 7.004 7.704 IIAC=25.69A, VVRMS=1.585V VFBPFC=2.25V, at TA=25C 3.801 4.182 4.600 IIAC=51.62A, VVRMS=3.169V VFBPFC=2.25V, at TA=25C 0.950 1.045 1.149 IIAC=62.23A, VVRMS=3.803V VFBPFC=2.25V, at TA=25C 0.660 0.726 0.798 Bandwidth IIAC=40A Output Voltage=5.7k x (ISENSE-IOFFSET) IAC=20A, VRMS=1.224V VFBPFC=2.25V, at TA=25C 2 0.710 0.798 kHz 0.885 V -1.05 V PFC ILIMIT Comparator VPFC-ILIMIT Vpk Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit PFC ILIMIT-Gain Modulator Output -1.25 IIAC=17.67A, VVRMS=1.08V VFBPFC=2.25V, at TA=25C 200 Gate Output Clamping Voltage VDD=22V 13 -1.15 FAN6982 -- CCM Power Factor Correction Controller Electrical Characteristics (Continued) mV PFC Output Driver VGATE-CLAMP 15 17 V 1.5 V VGATE-L Gate Low Voltage VDD=15V; IO=100mA VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 tR Gate Rising Time VDD=15V; CL=4.7nF; O/P= 2V to 9V 40 70 120 ns tF Gate Falling Time VDD=15V; CL=4.7nF; O/P= 9V to 2V 40 60 110 ns DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 DPFC-MIN Minimum Duty Cycle VIEA>4.5V V % 0 % 2 4 ms 0.5 0.6 V Tri-Fault Detect tFBPFC_OPEN Time to FBPFC Open VPFC-UVP PFC Feedback UnderVoltage Protection VFBPFC=VFBPFC-OVP to FBPFC OPEN, 470pF from FBPFC to GND 0.4 Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This gain is the maximum gain of modulation with a given VRMS voltage when VEA is saturated to high. (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 8 29.0 2.9 28.8 2.8 28.6 2.7 28.4 V D D-O V P (V) I DD-O P (A) 3.0 2.6 2.5 2.4 28.2 28.0 27.8 2.3 27.6 2.2 27.4 2.1 27.2 27.0 2.0 -40 -25 -10 5 20 Figure 5. 35 50 65 80 95 110 -40 12 5 IDD-OP vs. Temperature 74 7 .6 5 72 7 .6 0 5 20 35 50 65 80 95 11 0 125 95 11 0 12 5 95 110 125 11 0 125 7 .5 5 V VREF (V ) (k H z ) -10 Figure 6. VDD-OVP vs. Temperature 70 68 66 f O SC -25 7 .5 0 7 .4 5 64 7 .4 0 62 7 .3 5 60 -4 0 -2 5 -1 0 5 20 50 65 80 95 110 -4 0 125 fOSC vs. Temperature -2 5 -1 0 5 20 35 50 65 80 Figure 8. VVREF vs. Temperature 1 .1 0 1 .9 5 1 .0 8 1 .9 3 V RM S-UVH (V ) V R M S-UVL (V ) Figure 7. 35 FAN6982 -- CCM Power Factor Correction Controller Typical Performance Characteristics 1 .0 6 1 .0 4 1 .0 2 1 .9 1 1 .8 9 1 .8 7 1 .0 0 1 .8 5 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 -4 0 125 Figure 9. VRMS-UVL vs. Temperature -2 5 -1 0 5 20 35 50 65 80 Figure 10. VRMS-UVH vs. Temperature 2 .5 0 500 450 400 350 I R DY-LE K (n A ) V F BPF C -R D (V ) 2 .4 5 2 .4 0 2 .3 5 300 250 200 150 100 50 2 .3 0 0 -4 0 -2 5 -1 0 Figure 11. 5 20 35 50 65 80 95 11 0 12 5 -4 0 VFBPFC-RD vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 -2 5 -1 0 5 20 35 50 65 80 95 Figure 12. IRDY-LEK vs. Temperature www.fairchildsemi.com 9 2 .6 0 90 2 .5 8 85 2 .5 6 80 G m V (m h o ) 2 .5 4 V REF (V ) 2 .5 2 2 .5 0 2 .4 8 2 .4 6 75 70 65 60 2 .4 4 55 2 .4 2 50 2 .4 0 -4 0 -2 5 -1 0 5 Figure 13. 20 35 50 65 80 95 11 0 -4 0 125 VREF vs. Temperature -2 5 -1 0 5 20 Figure 14. 35 50 65 80 95 11 0 125 95 11 0 125 95 11 0 125 95 11 0 125 GmV vs. Temperature 10 12 0 8 6 11 0 G m I (m h o ) V O F FS ET (m V ) 4 2 0 -2 -4 10 0 90 80 70 -6 60 -8 50 -10 -4 0 -2 5 -1 0 Figure 15. 5 20 35 50 65 80 95 11 0 -4 0 125 VOFFSET vs. Temperature -1 0 5 20 35 50 65 80 Figure 16. GmI vs. Temperature 2 .8 0 2 2 .0 2 .7 9 2 1 .5 2 .7 8 2 1 .0 2 .7 7 2 0 .5 2 .7 6 I T C (A ) V F BPF C-OV P (V ) -2 5 FAN6982 -- CCM Power Factor Correction Controller Typical Performance Characteristics (Continued) 2 .7 5 2 .7 4 2 .7 3 2 0 .0 1 9 .5 1 9 .0 2 .7 2 1 8 .5 2 .7 1 1 8 .0 2 .7 0 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 -4 0 125 Figure 17. VFBPFC-OVP vs. Temperature -2 5 -1 0 5 Figure 18. 20 35 50 65 80 ITC vs. Temperature -1 .0 5 0 .8 7 -1 .0 7 0 .8 5 -1 .0 9 -1 .11 V PF C-ILIM IT (V ) V O (G M ) (V ) 0 .8 3 0 .8 1 0 .7 9 0 .7 7 0 .7 5 -1 .1 3 -1 .1 5 -1 .1 7 -1 .1 9 -1 .2 1 0 .7 3 -1 .2 3 -1 .2 5 0 .7 1 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 -4 0 125 Figure 19. VO(GM) vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 -2 5 -1 0 5 20 35 50 65 80 Figure 20. VPFC-ILIMIT vs. Temperature www.fairchildsemi.com 10 17 0 .6 0 17 0 .5 5 16 V PF C-U VP (V ) V G AT E-C LAM P (V ) 16 15 15 0 .5 0 0 .4 5 14 14 0 .4 0 13 -4 0 -2 5 -1 0 5 20 35 50 65 80 95 11 0 -4 0 125 Figure 21. VGATE-CLAMP vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 -2 5 -1 0 Figure 22. 5 20 35 50 65 80 95 VPFC-UVP vs. Temperature 11 0 125 FAN6982 -- CCM Power Factor Correction Controller Typical Performance Characteristics (Continued) www.fairchildsemi.com 11 G Oscillator The internal oscillator frequency of FAN6982 is determined by the timing resistor and capacitor on the RT/CT pin, but note that the optimum operation for FAN6982 is between 50 and 75kHz. The frequency of the internal oscillator is given by: f OSC = 1 0.56 RT CT + 360CT 1 VRMS 2 (1) The dead time for the PFC gate drive signal is determined by tDEAD = 360CT VRMS (2) VRMS-UVP The dead time should be smaller than 2% of switching period to minimize line current distortion around line zero crossing. Figure 24. Modulation Gain Characteristics VIN Gain Modulator Gain modulator is the key block for PFC stage because it provides the reference to the current control error amplifier for the input current shaping, as shown in Figure 23. The output current of gain modulator is a function of VEA, IAC and VRMS. The gain of the gain modulator is given as a ratio between IMO and IAC with a given VRMS when VEA is saturated to high. The gain is 2 inversely proportional to VRMS , as shown in Figure 24, to implement line feed-forward. This automatically adjusts the reference of current control error amplifier according to the line voltage such that the input power of PFC converter is not changed with line voltage, as shown in, Figure 25. VEA FAN6982 -- CCM Power Factor Correction Controller Functional Description IL Figure 25. Line Feed-Forward Operation To sense the RMS value of the line voltage, an averaging circuit with two poles is typically employed as shown in Figure 23. Notice that the input voltage of PFC is clamped at the peak of the line voltage once PFC stops switching since the junction capacitance of bridge diode is not discharged, as shown in Figure 26. Therefore, the voltage divider for VRMS should be designed considering the brownout protection trip point and minimum operation line voltage. IMO = G I AC = I AC K (VEA - 0.6) VRMS 2 (VEAMAX - 0.6) PFC runs PFC stops VIN Figure 23. Gain Modulator Block VRMS Figure 26. VRMS According to the PFC Operation (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 12 2VLINE .BO MAX G < 159 A RIAC The current-control feedback loop also has a pulse-bypulse current limit comparator that forces the PFC switch to turn off if the ISENSE pin voltage drops below -1.15V until the next switching cycle. Voltage-Control of Boost Stage (3) The voltage-control loop regulates PFC output voltage using internal error amplifier such that the FBPFC voltage is same as internal reference of 2.5V. where VLINE.BO is the line voltage that trips brownout MAX protection, G is the maximum modulator gain when VRMS is 1.08V, and 159A is the maximum output current of the gain modulator. To improve system efficiency at low AC line voltage and light-load condition, FAN6982 provides adjustable PFC output voltage. As shown in Figure 29, FAN6982 monitors VEA and VRMS to adjust the PFC output voltage. When VEA and VRMS are lower than thresholds, internal current source of 20A is enabled that flows through RFB2, increasing the voltage of the FBPFC pin. This causes the PFC output voltage to reduce when 20A is enabled as: Current-Control of Boost Stage As shown in Figure 27 the FAN6982 employs two control loops for power factor correction, a currentcontrol loop and a voltage-control loop. The currentcontrol loop shapes inductor current, as shown in Figure 28, based on the reference signal obtained at IAC pin as: I L RCS 1 = I MO RM = I AC G RM VOPFC 2 = (4) VIN RFB1 + RFB 2 x (2.5 - 20 A x RFB 2 ) RFB 2 (5) VO IL FAN6982 -- CCM Power Factor Correction Controller The rectified sinusoidal signal is obtained by the current flowing into the IAC pin. The resistor RIAC should be large enough to prevent saturation of the gain modulator as: RCS1 RF1 RM ISENSE RRMS1 IEA RM RIC CF1 IMO RIAC CIC2 IAC CRMS1 RRMS2 IAC CRMS2 RRMS3 VRMS + VEA - Drive logic RVC CVC2 CIC1 VREF OPFC RT/CT CVC1 2.5V Figure 29. Block of Adjustable PFC Output Brownout Protection RFB1 FAN6982 has a built-in internal brownout protection comparator monitoring the voltage of the VRMS pin. Once the VRMS pin voltage is lower than 1.05V, the PFC stage is shutdown to protect the system from over current. FAN6982 starts up the boost stage once the VRMS voltage increases above 1.9V. FBPFC RFB2 Figure 27. Gain Modulation Block TriFault DetectTM To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards; the FAN6982 includes TriFault Detect technology. This feature monitors FBPFC for certain PFC fault conditions. IAC I MO RM RCS1 In the case of a feedback path failure, the output of the PFC could exceed operating limits. Should FBPFC go too low, or too high, or open; TriFault Detect senses the error and terminates the PFC output drive. IL TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function. Figure 28. Inductor Current Shaping (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 13 RDY Function The FAN6982 PFC soft-start function is shown in Figure 30. When bulk voltage is under the 96% of setting voltage; VEA clamps to 2.8V, the output current of multiplier cuts half, the rectifier line current is limited by current loop, and PFC output rise time increases. The FAN6982 RDY function, is shown in Figure 31, is controlled by voltage of FBPFC. If the voltage of FBPFC is over than 96% of 2.5V, the RDY pin is connected to SGND. If the FBPFC is under the 46% of 2.5V, the RDY appears open-drain situation. Usually the capacitor is parallel with the RDY pin to prevent the layout noise. When bulk voltage is over 96%, the clamping function is disabled, and the bulk voltage can be regulated by voltage error amplifier. The PNP transistor can control the AHB LLC or dualforward controller on the same side or the "op-to" to control the LLC controller on the other side. There have two advantages with PFC soft-start: one is the MOSFET experience of current is reduced, which can obtain more de-rating with MOSFET current level. The other one is to reduce the overshoot of PFC bulk voltage at the rising time because the charge current becomes small, the bulk voltage can not exceed to setting voltage easily. Figure 31. RDY Application Circuit FAN6982 -- CCM Power Factor Correction Controller PFC Soft-Start Function Figure 30. PFC Soft-Start (c) 2009 Fairchild Semiconductor Corporation FAN6982 * Rev. 1.0.3 www.fairchildsemi.com 14 8.75 8.50 A 7.62 14 8 14 B 0.65 8 4.00 3.80 6.00 1 PIN #1 IDENT. 1.27 (0.33) TOP VIEW 5.60 7 0.51 0.35 0.25 M C B A 1.75 MAX 1.70 1 1.27 LAND PATTERN RECOMMENDATION A C 1.50 1.25 FRONT VIEW 0.25 0.10 0.50 0.25 x 45 R0.10 GAGE PLANE R0.10 0.36 8 0 0.90 0.50 (1.04) 0.10 C 0.25 0.19 SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. 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