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July 2010

FAN6982 • Rev. 1.0.3

FAN6982 — CCM Power Factor Correction Controller

FAN6982

CCM Power Factor Correction Controller

Features

 Continuous Conduction Mode

 Innovative Switching-Charge Multiplier-Divider

 Average-Current-Mode for Input-Current Shaping

 TriFault Detect™ Prevent Abnormal Operation for

Feedback Loop

 Power-On Sequence Control

 Soft-Start Capability

 Brownout Protection

 Cycle-by-Cycle Peak Current Limiting.

 Improves Light-Load Efficiency

 Fulfills Class-D Requirements of IEC 1000-3-2

 Wide Range Universal AC Input Voltage

 Maximum Duty Cycle 97%

 VDD Under-Voltage Lockout (UVLO)

Applications

 Desktop PC Power Supply

 Internet Server Power Supply

 LCD TV/Monitor Power Supply

 DC Motor Power Supply

Description

The FAN6982 is a 14-pin, Continuous Conduction Mode

(CCM) PFC controller IC intended for Power Factor

Correction (PFC) pre-regulators. The FAN6982 includes

circuits for the implementation of leading edge, average

current, “boost”-type power factor correction, and

results in a power supply that fully complies with the

IEC1000-3-2 specification.

A TriFault Detect™ function helps reduce external

components and provides full protection for feedback

loops such as open, short, and over voltage. An over-

voltage comparator shuts down the PFC stage in the

event of a sudden load decrease. The RDY signal can

be used for power-on sequence control. The EN

function can choose to enable or disable the range

function. FAN6982 also includes PFC soft-start, peak

current limiting, and input voltage brownout protection.

Ordering Information

Part Number Operating Temperature Range Package Packing Method

FAN6982MY -40°C to +105°C 14-Pin Small Outline Package (SOP) Tape & Reel

FAN6982 • Rev. 1.0.3 2

FAN6982 — CCM Power Factor Correction Controller

Application Diagram

Figure 1. Typical Application

FAN6982 • Rev. 1.0.3 3

FAN6982 — CCM Power Factor Correction Controller

Block Diagram

OSCILLATOR

PGND

RDY

SET

CLR

2.5V

FBPFC

IAC

VRMS

0.3V

Low-Power

Detect Comparator

ISENSE

-1.15V

PFC ILIMIT

PFC OVP

VDD OVP

PFC UVP

2.75V/2.5V

28V/27V

0.5V

SET

CLR

VDD

RT/CT

VEA IEA

7.5V

REFERENCE

VDD VREF

2.4V/1.15V

FBPFC

UVLO

VDD

114 11

OPFC

SGND

1.05V/1.9V

VRMS VIN UVP

Range

VEA

2.8V

ISENSE

Gain Modulator

Figure 2. Functional Block Diagram

Marking Informa ti on

Figure 3. Top Mark

F – Fairchild Logo

Z – Plant Code

X – 1-Digit Year Code

Y – 1-Digit Week Code

TT – 2-Digit Die-Run Code

T – Package Type (M: SOP)

P – Y: Green Package

M – Manufacture Flow Code

FAN6982 • Rev. 1.0.3 4

FAN6982 — CCM Power Factor Correction Controller

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin # Name Description

1 IEA

Output of Current Amplifier. This is the output of the PFC current amplifier. The signal from

this pin is compared with sawtooth and determines the pulsewidth for PFC gate drive.

2 IAC

Input AC Current. For normal operation, this input is used to provide current reference for the

multiplier. The suggested maximum IAC is 100µA.

3 ISENSE

Current Sense. The non-inverting input of the PFC current amplifier and the output of

multiplier and PFC ILIMIT comparator.

4 VRMS

Line-Voltage Detection. The pin is used for PFC multiplier.

5 RDY

Ready Signal. This pin controls the power-on sequence. Once the FAN6982 is turned on and

the FBPFC voltage exceeds in 2.4V, the RDY pin pulls LOW impedance. If the FBPFC voltage

is lower than 1.15V, the RDY pin pulls HIGH impedance.

6 EN

Enable Range Function. The range function is enabled when EN is connected to VREF.

The range function is disabled when EN is connected to GND.

7 RT/CT

Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.

8 SGND

Signal Ground.

9 PGND

Power Ground.

10 OPFC

Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped

under 15V to protect the MOSFET.

11 VDD

Power Supply. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively.

The operating current is lower than 10mA.

12 VREF

Reference Voltage. Buffered output for the internal 7.5V reference.

13 FBPFC

Voltage Feedback Input. The feedback input for PFC voltage loop. The inverting input of PFC

error amplifier. This pin is connected to the PFC output through a divider network.

14 VEA

Output of Voltage Amplifier. The error-amplifier output for PFC voltage feedback loop.

A compensation network is connected between this pin and ground.

FAN6982 • Rev. 1.0.3 5

FAN6982 — CCM Power Factor Correction Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage 30 V

VH OPFC, RDY, EN, VREF -0.3 30.0 V

VL IAC, VRMS, RT/CT, FBPFC, VEA -0.3 7.0 V

VIEA IEA 0 VVREF+0.3 V

VN ISENSE -5.0 0.7 V

IAC Input AC Current 1 mA

IREF VREF Output Current 5 mA

IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A

PD Power Dissipation, TA < 50°C 800 mW

RΘ j-a Thermal Resistance (Junction-to-Air) 104.10 °C/W

RΘ j-c Thermal Resistance (Junction-to-Case) 40.61 °C/W

TJ Operating Junction Temperature -40 +125 °C

TSTG Storage Temperature Range -55 +150 °C

TL Lead Temperature (Soldering) +260 °C

ESD Electrostatic Discharge Capability

Human Body Model,

JESD22-A114 4.5

Charged Device Model,

JESD22-C101 1.0

Notes:

1. All voltage values, except differential voltage, are given with respect to the GND pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

TA Operating Ambient Temperature -40 +105 °C

FAN6982 • Rev. 1.0.3 6

FAN6982 — CCM Power Factor Correction Controller

Electrical Characteristics

Unless otherwise noted; VDD=15V, TA= 25°C, TA=TJ, RT=27kΩ, and CT=1000pF.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

VDD-OP Continuously Operating

Voltage 22 V

IDD ST Startup Current VDD=VTH-ON-0.1V; OPFC Open 30 80 µA

IDD-OP Operating Current VDD=13V; OPFC Open 2.0 2.3 3.0 mA

VTH-ON Turn-on Threshold Voltage 10 11 12 V

△VTH Hysteresis 1.35 1.90 V

VDD-OVP V

DD OVP 27 28 29 V

△VDD-OVP VDD OVP Hysteresis 1 V

Oscillator

fOSC PFC Frequency RT=27kΩ, CT=1000pF 60 64 67 kHz

fDV(3) Voltage Stability 11V ≦ VDD ≦ 22V 2 %

fDT(3) Temperature Stability -40°C ~ +105°C 2 %

fTV Total Variation Line, Temperature 58 70 kHz

fRV Ramp Voltage Valley-to-Peak 2.8 V

IOSC-DIS Discharge Current VRAMP=0V, VRT/CT=2.5V 6.5 15.0 mA

fRANGE Frequency Range 50 75 kHz

tPFC-DEAD PFC Dead Time RT=27kΩ, CT=1000pF 400 600 800 ns

VREF

VVREF Reference Voltage IREF=0mA, CREF=0.1µF 7.4 7.5 7.6 V

△VVREF1 Load Regulation of

Reference Voltage

CREF=0.1µF, IREF=0mA to 3.5mA

VVDD=14V, Rise/Fall Time > 20µs 30 50 mV

△VVREF2 Line Regulation of Reference

Voltage CREF=0.1µF, VVDD=11V to 22V 25 mV

△VVREF-DT Temperature Stability(3) -40°C ~ +105°C 0.4 0.5 %

△VVREF-TV Total Variation(3) Line, Load, Temperature 7.35 7.65 V

△VVREF-LS Long-Term Stability(3) T

J=125°C, 0 ~ 1000HRs 5 25 mV

IREF-MAX Maximum Current VVREF > 7.35V 5 mA

Brownout

VRMS-UVL V

RMS Threshold Low When VRMS=1.05V at 75 VRMS 1.00 1.05 1.10 V

VRMS-UVH V

RMS Threshold High When VRMS=1.9V at 85 • 1.414 1.85 1.90 1.95 V

△VRMS-UVP Hysteresis 750 850 950 mV

tUVP Under-Voltage Protection

Debounce Time 340 410 480 ms

RDY Section

VFBPFC-RD FBPFC Voltage Level to Pull

Low Impedance with RDY Pin 2.3 2.4 2.5 V

△VFBPFC-RD Hysteresis 1.15 1.25 1.35 V

IRDY-LEK Leakage Current of RDY

High Impedance VFBPFC<2.4V 500 nA

VRDY-L RDY Low Voltage ISINK=2mA 0.5 V

Continued on the following page…

FAN6982 • Rev. 1.0.3 7

FAN6982 — CCM Power Factor Correction Controller

Electrical Characteristics (Continued)

Unless otherwise noted; VDD=15V, TA= 25°C, TA=TJ, RT=27kΩ, and CT=1000pF.

Symbol Parameter Conditions Min. Typ. Max. Units

Voltage Error Amplifier

VREF Reference Voltage 2.45 2.50 2.55 V

AV Open-Loop Gain(3) At TA=25°C 35 42 dB

GmV Transconductance VNONINV=VINV, VVEA=3.75V at TA=25°C 50 70 90 µmho

IFBPFC-L Maximum Source Current VFBPFC=2V, VVEA=1.5V 40 50 µA

IFBPFC-H Maximum Sink Current VFBPFC=3V, VVEA=6V -50 -40 µA

IBS Input Bias Current -1 1 µA

VVEA-H Output High Voltage on VVEA 5.8 6.0 V

VVEA-L Output Low Voltage on VVEA 0.1 0.4 V

Current Error Amplifier

VISENSE Input Voltage Range -1.5 0.7 V

AI Open-Loop Gain(3) At TA=25°C 40 50 dB

GmI Transconductance VNONINV=VINV, VIEA=3.75V 75 88 100 µmho

VOFFSET Input Offset Voltage VVEA=0V, IAC Open -10 10 mV

VIEA-H Output High Voltage 6.8 7.4 8.0 V

VIEA-L Output Low Voltage 0.1 0.4 V

IL Source Current VISENSE= -0.6V, VIEA=1.5V 35 50 µA

IH Sink Current VISENSE= +0.6V, VIEA=4.0V -50 -35 µA

PFC OVP Comparator

VFBPFC-OVP Over Voltage Protection 2.70 2.75 2.80 V

△VFBPFC-OVP PFC OVP Hysteresis 200 250 300 mV

Low-Power Detect Comparator

VVEA-OFF VEA Voltage Off OPFC 0.2 0.3 0.4 V

PFC Soft-Start

VVEA_CLAMP PFC Soft-Start VFBPFC < 2.4V 2.2 2.8 3.3 V

EN Section

VEN-H High Voltage Level of VEN V

EN=VVREF 7.4 7.5 7.6 V

VEN-L Low Voltage Level of VEN V

EN=GND 0 V

Range

VVRMS-L RMS AC Voltage Low When VVRMS=1.95V at 132VRMS 1.90 1.95 20.00 V

VVRMS-H RMS AC Voltage High When VVRMS=2.45V at 150 VRMS 2.40 2.45 2.50 V

VVEA-L VEA Low When VVEA=1.95V at 30% Loading 1.90 1.95 2.00 V

VVEA-H VEA High When VVEA=2.45V at 40% Loading 2.40 2.45 2.50 V

ITC Source Current from FBPFC 18 20 22 µA

Continued on the following page…

FAN6982 • Rev. 1.0.3 8

FAN6982 — CCM Power Factor Correction Controller

Electrical Characteristics (Continued)

Unless otherwise noted; VDD=15V, TA= 25°C, TA=TJ, RT=27kΩ, and CT=1000pF.

Symbol Parameter Conditions Min. Typ. Max. Units

Gain Modulator

IAC Input for AC Current Multiplier Linear Range 0 100 µA

GAIN Gain Modulator(3)(4)

IIAC=17.67µA, VVRMS=1.080V

VFBPFC=2.25V, at TA=25°C 7.500 9.000 10.500

IIAC=20µA, VVRMS=1.224V

VFBPFC=2.25V, at TA=25°C 6.367 7.004 7.704

IIAC=25.69µA, VVRMS=1.585V

VFBPFC=2.25V, at TA=25°C 3.801 4.182 4.600

IIAC=51.62µA, VVRMS=3.169V

VFBPFC=2.25V, at TA=25°C 0.950 1.045 1.149

IIAC=62.23µA, VVRMS=3.803V

VFBPFC=2.25V, at TA=25°C 0.660 0.726 0.798

BW Bandwidth IIAC=40µA 2 kHz

VO(GM) Output Voltage=5.7kΩ ×

(ISENSE-IOFFSET)

IAC=20µA, VRMS=1.224V

VFBPFC=2.25V, at TA=25°C 0.710 0.798 0.885 V

PFC ILIMIT Comparator

VPFC-ILIMIT

Peak Current Limit

Threshold Voltage

Cycle-by-Cycle Limit

-1.25 -1.15 -1.05 V

△Vpk PFC ILIMIT-Gain Modulator

Output

IIAC=17.67µA, VVRMS=1.08V

VFBPFC=2.25V, at TA=25°C 200 mV

PFC Output Driver

VGATE-CLAMP Gate Output Clamping

Voltage VDD=22V 13 15 17 V

VGATE-L Gate Low Voltage VDD=15V; IO=100mA 1.5 V

VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 V

tR Gate Rising Time VDD=15V; CL=4.7nF;

O/P= 2V to 9V 40 70 120 ns

tF Gate Falling Time VDD=15V; CL=4.7nF;

O/P= 9V to 2V 40 60 110 ns

DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 %

DPFC-MIN Minimum Duty Cycle VIEA>4.5V 0 %

Tri-Fault Detect

tFBPFC_OPEN Time to FBPFC Open VFBPFC=VFBPFC-OVP to FBPFC

OPEN, 470pF from FBPFC to GND 2 4 ms

VPFC-UVP PFC Feedback Under-

Voltage Protection 0.4 0.5 0.6 V

Notes:

3. This parameter, although guaranteed by design, is not 100% production tested.

4. This gain is the maximum gain of modulation with a given VRMS voltage when VEA is saturated to high.

FAN6982 • Rev. 1.0.3 9

FAN6982 — CCM Power Factor Correction Controller

Typical Performance Characteristics

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

DD-OP

(µA)

27.0

27.2

27.4

27.6

27.8

28.0

28.2

28.4

28.6

28.8

29.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

DD-OVP

(V)

Figure 5. IDD-OP vs. Temperature Figure 6. VDD-OVP vs. Temperature

-40 -25 -10 5 20 35 50 65 80 95 110 125

OSC

(kHz)

7.35

7.40

7.45

7.50

7.55

7.60

7.65

-40 -25 -10 5 20 35 50 65 80 95 110 125

VREF

(V)

Figure 7. fOSC vs. Temperature Figure 8. VVREF vs. Temperature

1.00

1.02

1.04

1.06

1.08

1.10

-40 -25 -10 5 20 35 50 65 80 95 110 125

RMS-UVL

(V)

1.85

1.87

1.89

1.91

1.93

1.95

-40 -25 -10 5 20 35 50 65 80 95 110 125

RMS-UVH

(V)

Figure 9. VRMS-UVL vs. Temperature Figure 10. VRMS-UVH vs. Temperature

2.30

2.35

2.40

2.45

2.50

-40 -25 -10 5 20 35 50 65 80 95 110 125

FBPFC-RD

(V)

100

150

200

250

300

350

400

450

500

-40 -25 -10 5 20 35 50 65 80 95 110 125

RDY-LEK

(nA)

Figure 11. VFBPFC-RD vs. Temperature Figure 12. IRDY-LEK vs. Temperature

FAN6982 • Rev. 1.0.3 10

FAN6982 — CCM Power Factor Correction Controller

Typical Performance Characteristics (Continued)

2.40

2.42

2.44

2.46

2.48

2.50

2.52

2.54

2.56

2.58

2.60

-40 -25 -10 5 20 35 50 65 80 95 110 125

REF

(V)

-40 -25 -10 5 20 35 50 65 80 95 110 125

(µmho)

Figure 13. VREF vs. Temperature Figure 14. GmV vs. Temperature

-10

-8

-6

-4

-2

-40 -25 -10 5 20 35 50 65 80 95 110 125

OFFSET

(mV)

100

110

120

-40 -25 -10 5 20 35 50 65 80 95 110 125

(µmho)

Figure 15. VOFFSET vs. Temperature Figure 16. GmI vs. Temperature

2.70

2.71

2.72

2.73

2.74

2.75

2.76

2.77

2.78

2.79

2.80

-40 -25 -10 5 20 35 50 65 80 95 110 125

FBPFC-OVP

(V)

18.0

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

(µA)

Figure 17. VFBPFC-OVP vs. Temperature Figure 18. ITC vs. Temperature

0.71

0.73

0.75

0.77

0.79

0.81

0.83

0.85

0.87

-40 -25 -10 5 20 35 50 65 80 95 110 125

O(GM)

(V)

-1.25

-1.23

-1.21

-1.19

-1.17

-1.15

-1.13

-1.11

-1.09

-1.07

-1.05

-40 -25 -10 5 20 35 50 65 80 95 110 125

PFC-ILIMIT

(V)

Figure 19. VO(GM) vs. Temperature Figure 20. VPFC-ILIMIT vs. Temperature

FAN6982 • Rev. 1.0.3 11

FAN6982 — CCM Power Factor Correction Controller

Typical Performance Characteristics (Continued)

-40 -25 -10 5 20 35 50 65 80 95 110 125

GATE-CLAMP

(V)

0.40

0.45

0.50

0.55

0.60

-40 -25 -10 5 20 35 50 65 80 95 110 125

PFC-UVP

(V)

Figure 21. VGATE-CLAMP vs. Temperature Figure 22. VPFC-UVP vs. Temperature

FAN6982 • Rev. 1.0.3 12

FAN6982 — CCM Power Factor Correction Controller

Functional Description

Oscillator

The internal oscillator frequency of FAN6982 is

determined by the timing resistor and capacitor on the

RT/CT pin, but note that the optimum operation for

FAN6982 is between 50 and 75kHz. The frequency of

the internal oscillator is given by:

0.56 360

OSC

TT T

=⋅⋅+ (1)

The dead time for the PFC gate drive signal is

determined by

360

DEAD T

tC= (2)

The dead time should be smaller than 2% of switching

period to minimize line current distortion around line

zero crossing.

Gain Modul at or

Gain modulator is the key block for PFC stage because

it provides the reference to the current control error

amplifier for the input current shaping, as shown in

Figure 23. The output current of gain modulator is a

function of VEA, IAC and VRMS. The gain of the gain

modulator is given as a ratio between IMO and IAC with a

given VRMS when VEA is saturated to high. The gain is

inversely proportional to VRMS2, as shown in Figure 24,

to implement line feed-forward. This automatically

adjusts the reference of current control error amplifier

according to the line voltage such that the input power

of PFC converter is not changed with line voltage, as

shown in, Figure 25.

=⋅

⋅−

=⋅ −

(0.6)

MO AC

AC MAX

RMS EA

IGI

IVV

Figure 23. Gain Modulator Block

RMS

RMS-UVP

RMS

∝

Figure 24. Modulation Gain Characteristics

Figure 25. Line Feed-Forward Operation

To sense the RMS value of the line voltage, an

averaging circuit with two poles is typically employed as

shown in Figure 23. Notice that the input voltage of

PFC is clamped at the peak of the line voltage once

PFC stops switching since the junction capacitance of

bridge diode is not discharged, as shown in Figure 26.

Therefore, the voltage divider for VRMS should be

designed considering the brownout protection trip point

and minimum operation line voltage.

PFC runs PFC stops

RMS

Figure 26. VRMS According to the PFC Operation

FAN6982 • Rev. 1.0.3 13

FAN6982 — CCM Power Factor Correction Controller

The rectified sinusoidal signal is obtained by the current

flowing into the IAC pin. The resistor RIAC should be

large enough to prevent saturation of the gain

modulator as:

2159

⋅<

MAX

LINE BO

IAC

VGA

R (3)

where VLINE.BO is the line voltage that trips brownout

protection, GMAX is the maximum modulator gain when

VRMS is 1.08V, and 159µA is the maximum output

current of the gain modulator.

Current-Control of Boost Stage

As shown in Figure 27 the FAN6982 employs two

control loops for power factor correction, a current-

control loop and a voltage-control loop. The current-

control loop shapes inductor current, as shown in

Figure 28, based on the reference signal obtained at

IAC pin as:

1LCS MOM AC M

RIRIGR⋅=⋅=⋅⋅ (4)

ISENSE

IAC

VRMS

VEA

IEA

RRMS1

RRMS2

RRMS3

CRMS1

CRMS2

RIAC

IAC

VIN

RCS1

RF1

CF1

IMO

RIC

CIC1

CIC2

Drive

logic OPFC

2.5V

RVC

CVC1

CVC2

FBPFC

RFB1

RFB2

VREF

RT/CT

Figure 27. Gain Modulation Block

Figure 28. Inductor Current Shaping

The current-control feedback loop also has a pulse-by-

pulse current limit comparator that forces the PFC

switch to turn off if the ISENSE pin voltage drops below

-1.15V until the next switching cycle.

Voltage-Cont rol of Boost Stage

The voltage-control loop regulates PFC output voltage

using internal error amplifier such that the FBPFC

voltage is same as internal reference of 2.5V.

To improve system efficiency at low AC line voltage

and light-load condition, FAN6982 provides adjustable

PFC output voltage. As shown in Figure 29, FAN6982

monitors VEA and VRMS to adjust the PFC output

voltage. When VEA and VRMS are lower than thresholds,

internal current source of 20µA is enabled that flows

through RFB2, increasing the voltage of the FBPFC pin.

This causes the PFC output voltage to reduce when

20µA is enabled as:

(2 5 20 )

=××

FB FB

OPFC FB

V.-μAR

R (5)

Figure 29. Block of Adjustable PFC Output

Brownout Protection

FAN6982 has a built-in internal brownout protection

comparator monitoring the voltage of the VRMS pin.

Once the VRMS pin voltage is lower than 1.05V, the

PFC stage is shutdown to protect the system from over

current. FAN6982 starts up the boost stage once the

VRMS voltage increases above 1.9V.

TriFault Detect™

To improve power supply reliability, reduce system

component count, and simplify compliance to UL 1950

safety standards; the FAN6982 includes TriFault Detect

technology. This feature monitors FBPFC for certain

PFC fault conditions.

In the case of a feedback path failure, the output of the

PFC could exceed operating limits. Should FBPFC go

too low, or too high, or open; TriFault Detect senses the

error and terminates the PFC output drive.

TriFault detect is an entirely internal circuit. It requires

no external components to serve its protective function.

FAN6982 • Rev. 1.0.3 14

FAN6982 — CCM Power Factor Correction Controller

PFC Soft-Start Function

The FAN6982 PFC soft-start function is shown in

Figure 30. When bulk voltage is under the 96% of

setting voltage; VEA clamps to 2.8V, the output current

of multiplier cuts half, the rectifier line current is limited

by current loop, and PFC output rise time increases.

When bulk voltage is over 96%, the clamping function

is disabled, and the bulk voltage can be regulated by

voltage error amplifier.

There have two advantages with PFC soft-start: one is

the MOSFET experience of current is reduced, which

can obtain more de-rating with MOSFET current level.

The other one is to reduce the overshoot of PFC bulk

voltage at the rising time because the charge current

becomes small, the bulk voltage can not exceed to

setting voltage easily.

Figure 30. PFC Soft-Start

RDY Function

The FAN6982 RDY function, is shown in Figure 31, is

controlled by voltage of FBPFC. If the voltage of

FBPFC is over than 96% of 2.5V, the RDY pin is

connected to SGND. If the FBPFC is under the 46% of

2.5V, the RDY appears open-drain situation. Usually

the capacitor is parallel with the RDY pin to prevent the

layout noise.

The PNP transistor can control the AHB LLC or dual-

forward controller on the same side or the “op-to” to

control the LLC controller on the other side.

Figure 31. RDY Application Circuit

1.70

5.60

1.27

0.65

1.50

1.25

1.75 MAX

0.25

0.10

4.00

3.80

8.75

8.50

6.00

(0.33)

0.51

0.35

7.62

1.27

PIN #1

IDENT.

0.25

0.19

0.50

0.25

x 45

R0.10

(1.04)

0.36

8°

0°

0.90

0.50

DETAIL A

SCALE 16 : 1

GAGE

PLANE

SEATING PLANE

TOP VIEW

FRONT VIEW

SIDE VIEW

1 7

LAND PATTERN RECOMMENDATION

NOTES:

A. CONFORMS TO JEDEC MS-012,

VARIATION AB, ISSUE C

B. ALL DIMENSIONS ARE IN MILLIMETERS

C. DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS

D. LAND PATTERN STANDARD:

SOIC127P600X145-14M

E. CONFORMS TO ASME Y14.5M, 2009

D. DRAWING FILENAME: MKT-M14Arev14

0.10

0.25

B A

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