IR3720 DATA SHEET Power Monitor IC with Digital I2C Interface FEATURES DESCRIPTION Accurate TruePowerTM monitor * Minimizes dynamic errors * Reports voltage, current, or power Digital interface * SMBus and I2C compatible Programmable averaging interval Flexible current sensing * Resistive or Inductor DCR Applications * Synchronous rectified buck converters * Multiphase converters 10pin 3x3 DFN lead free package RoHS compliant The IR3720 measures the output voltage and inductor current of low-voltage DC-to-DC converters and reports the average power over a user specified time interval as a digital word on the I2C. The output current is measured across a current sensing resistor or indirectly across the inductor's DCR winding resistance. Additionally, the current measurement method is also applicable to multiphase converters. The real time voltage and current signals are multiplied, digitized, and averaged over a user selectable averaging interval providing Patent Pending TruePowerTM measurement of highly dynamic loads. TYPICAL APPLICATION CIRCUIT Phase Single Phase Converter DCR L Rcs1 Rcs2 3.3V Output Capacitors CCS1 CCS2 LOAD VO VDD IR3720 I2C Bus VREF VCS GND Power Return To system Controller 2 RT GND ORDERING INFORMATION Device IR3720MTRPBF * IR3720MPBF Package 10 lead DFN (3x3 mm body) 10 lead DFN (3x3 mm body) Order Quantity 3000 piece reel 121 Piece tube * Samples only Page 1 of 20 www.irf.com 09/09/08 IR3720 DATA SHEET ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND VDD: ................................................................3.9V ALERT#:...........................................................3.9V ALERT#.............................................. <VDD + 0.3V EXTCLK ...........................................................3.9V All other Analog and Digital pins ......................3.9V Operating Junction Temperature .... -10C to 150oC Storage Temperature Range .......... -65oC to 150oC Thermal Impedance (JC)............................53C/W ESD Rating ............HBM Class 2 JEDEC Standard MSL Rating ..................................................Level 2 Reflow Temperature ..................................... 260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply: VDD = 3.3V 5%, 0oC TJ 125oC, 0.5 VO 1.8 V, and operation in the system accuracy test circuit. See notes following table. PARAMETER IC SYSTEM ACCURACY Power accuracy, IC only BIAS SUPPLY VDD Turn-on Threshold, VDDUP VDD Turn-off Threshold, VDDDN VDD Operating Current VDD Shutdown Current VOLTAGE REFERENCE VREF Voltage Reference load, RT VOLTAGE SENSOR Voltage error Voltage, full scale VFS CURRENT SENSOR Voltage, Current Gain, VIG Current range, Io x DCR Current error Page 2 of 20 TEST CONDITION MIN TYP RCS2 = 600 , RT = 25.5 k, VDCR = 20 mV, VO=1 volt, CCS2 = 1F Sampling frequency 512 kHz. Sampling interval 8 ms, 0OC TJ 85OC Notes 1, 2 MAX UNIT 3.3 % 3.1 480 17 660 100 V V A A 1.5 25.5 1.6 40 V k 0.75 % 2.4 RT = 25.5 k Config Reg enable bit d4=1 RT = 25.5 k Note 1 VO=1V; VDCR=0 mV, 0OC TJ 85OC RCS2=600 , RT=25.5 k, Note 1 1.4 20 -0.75 1.854 RT = 25.5 k RCS2=600 , RT=25.5 k VO=1V; VDCR=20 mV, 0OC TJ 85OC RCS2=600 , RT=25.5 K, Note 1 www.irf.com V 1.5 -35 -2.4 35 2.4 V mV % 09/09/08 IR3720 DATA SHEET PARAMETER DIGITIZER Internal Sampling frequency External Sampling frequency TEST CONDITION Transition time Driven from external clock Note 1 POWER INFORMATION Minimum Averaging Interval Maximum Averaging Interval Output Register Measuring power Output Register Measuring power Output Register Measuring power Output Register Measuring power Full Scale Output Register Measuring power DIGITAL INPUT AND OUTPUT ALERT# pull down resistance SDA & SCL HIGH Level SDA & SCL Low Level SCL Input current SDA pull down voltage TIMING Maximum Frequency Bus free time between stop and start TBUF Hold time after (repeated) start condition THD:STA Repeated start condition setup time TSU:STA Stop condition setup time TSU:STO Data hold time THD:DAT Data setup time TSU:DAT Clock low period TLOW Clock high period THIGH Clock or data fall time TF Clock or data rise time TR Driven from internal clock Driven from external clock Config Reg [d3..d0] = b`0000, Note 1 Config Reg [d3..d0] = b`1000, Note 1 VO=1V; VDCR=20 mV RCS2=600 , RT=25.5 k, Note 1,2 VO=0.5V; VDCR=20 mV RCS2=600 , RT=25.5 k, Note 1,2 VO=1V; VDCR=0 mV RCS2=600 , RT=25.5 k, Note 1,2 VO=1V; VDCR=-8 mV RCS2=600 , RT=25.5 k, Note 1,2 VO = 1.8; VDCR=35 mV RCS2=600 , RT=25.5 k, Note 1,2 Sink 3 mA Note 1 Note 1 Note 1 Sink 4 mA Note 1 MIN 435 922 TYP 512 1024 MAX UNIT 589 1126 kHz kHz 50 ns 0.9 230 1380 1 256 1440 1.1 282 1500 ms ms HEX 0980 0A00 0A80 HEX FF40 0000 00C0 HEX F740 F800 F8C0 HEX 3DC0 3F80 4000 HEX 250 V V uA V 2.1 -5 0.8 +5 0.4 Note 1 Note 1 10 1.3 400 Note 1 0.6 us Note 1 0.6 us Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 0.6 300 100 1.3 0.6 20 20 us ns ns us us ns ns 300 300 kHz us NOTE: 1. Guaranteed by design, not tested in production 2. Average of eight data samples Page 3 of 20 www.irf.com 09/09/08 IR3720 DATA SHEET SYSTEM ACCURACY TEST CIRCUIT VDCR VDD RCS2 CCS2 VDD VDD Bypass Cap VCS VO ALERT# VREF VO EXTCLK ADDR SDA SCL RT GND Page 4 of 20 www.irf.com 09/09/08 IR3720 DATA SHEET BLOCK DIAGRAM IC PIN DESCRIPTION NAME VCS VO VREF GND VDD EXTCLK ADDR SCL SDA ALERT# BASE PAD Page 5 of 20 NUMBER 1 2 3 4 5 6 7 8 9 10 I/O LEVEL DESCRIPTION Analog Analog Analog Current sensing input Voltage sensing input Thermistor sensing input IC bias supply and signal ground 3.3V bias supply Input for optional external clock I2C Address selection input; See Table 1 for address I2C Clock; Input only I2C Data; Input / Open drain output Programmable output function; Open drain output clamped to VDD Connect to pin 4 3.3V 3.3V Digital 3.3V Digital 3.3V Digital 3.3V Digital 3.3V Digital www.irf.com 09/09/08 IR3720 DATA SHEET IC PIN FUNCTIONS VDD PIN ADDR PIN This pin provides operational bias current to circuits internal to the IR3720. Bypass it with a high quality ceramic capacitor to the GND pin. The ADDR pin is an input that establishes the I2C address. Valid addresses are selected by grounding, floating, or wiring to VDD the ADDR pin. Table 1, "User Selectable Addresses", provides a mapping of possible selections. GND PIN This pin returns operational bias current to its source. It is also the reference to which the voltage VO is measured, and it sinks the reference current established by the external resistor RT. VO PIN Connect this pin to the location in the circuit where voltage for the power calculation is desired to be monitored. Since it also measures DCR voltage drop it is critical that it be Kelvin connected to the buck inductor output. Power accuracy may be degraded if the voltage at this pin is below VOmin. VCS PIN The average current into this pin is used to calculate power. A switched current source internal to the IR3720 will maintain the average voltage of this pin equal to the voltage of the VO pin. VREF FUNCTION A voltage reference internal to the IR3720 drives the VREF pin while the pin current is monitored and used to set the amplitude of the current monitor switched current source IREF. This pin should be connected to GND through a precision resistor network RT. This network may include provision for canceling the positive temperature coefficient of the buck inductor's DC resistance (DCR). Table 1 User selectable addresses ADDR pin configuration Low Open High I2C Address b'1110 000 b'1110 010 b'1110 110 EXTCLK This pin is a Schmitt trigger input for an optional externally provided square wave clock. The duty ratio of this externally provided clock, if used, shall be between 40% and 60%. If no external clock is used, connect this pin to GND and the internal clock will be used. SCL SCL is the I2C clock and is capable of functioning with a rate as low as 10 kHz. It will continue to function as the rate is increased to 400 kHz. This device is considered a slave, and therefore uses the SCL as an input only. SDA SDA is monitored as data input during master to slave transactions, and is driven as data output during slave to master transactions as indicated in the Packet Protocol section to follow. ALERT# FUNCTION The ALERT# pin is a multi-use pin. During normal use it can be configured via the I2C as an open drain ALERT# pin that will be driven logic low when new data is available in the output register. After the output register has been read via the I2C the ALERT# will be released to its high resistance state. This pin can also be programmed to pull low when the output exceeds the programmable level. Page 6 of 20 www.irf.com 09/09/08 TYPICAL PERFORMANCE CHARACTERISTICS (System Accuracy Test Circuit, VDD=3.3 V, RCS2 = 600 , CCS2 = 1 F, RT = 25.5 k ) Typical transfer characteristic - Power configuration Average of 8 samples 300 7 Vo = 0.5V Vo = 1.0V 6 Vo = 1.8V Ideal Code Codes (Decimal) Typical error - Current Configuration Average of 8 samples 8 Vo = 0.5V Error (%) 5 0 Vo = 1.0V Vo = 1.8V 4 3 2 -300 -0.035 0.000 0.035 VDCR (V) 1 0 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 VDCR(V) Typical error - Power Configuration Average of 8 samples 8 7 Error (%) 6 Vo = 1.0V 5 Vo = 1.8V 4 3 2 1 0 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 VDCR (V) Page 7 of 20 www.irf.com 09/09/08 FUNCTIONAL DESCRIPTION Please refer to the Functional Description Diagram below. Power flow from the buck converter is the product of output voltage times the current IL flowing through the inductor. The full-scale voltage that can be measured is VFS. Average power is measured with the aid of International Rectifier's proprietary TruePowerTM circuit. Voltage, current, or the product of voltage Vo and current is digitized over the interval of interest and ported to the OUTPUT register. The VCS pin is maintained at an average voltage equal to Vo. VIG (RCS1 + RCS2 ) . (1) RT DCR Full-scale current capability is designed by specifying the external circuit values of equation 1. The full scale power PFS that can be measured is the product of full-scale voltage and full scale current. The full-scale positive current that can be measured is IFS = IL Vin Phase L DCR VO RCS1 RCS2 CCS1 ALERT# Pull-up Resistor CCS2 VDD VCS VO VDD ALERT# VDD Bypass Cap EXTCLK VREF IR3720 ADDR SDA SCL RT External Clock GND Figure 1 Functional Description Diagram Page 8 of 20 www.irf.com 09/09/08 RESISTOR SENSING APPLICATION The voltage on the shunt resistor of the circuit below is directly proportional to the current from the source. Shunts developing 5 mV to 75 mV at IFS have been used. Accuracy is enhanced at the higher voltage. Select RT to be a 25.5 k 1% or better initial tolerance resistor. This value will sink 1.5V /RT of current from the VREF pin of the IR3720. RCS2 should be chosen such that this current through it develops the same voltage that is developed by the shunt at full scale current. CCS2 is the integrator capacitor and should be between 0.1 F and 10 F. IL Vin Phase L RCS2 DCR SHUNT VO CCS2 VDD VCS VDD Bypass Cap VREF VO IR3720 RT VDD ALERT# EXTCLK ADDR SDA SCL GND Figure 2 Resistor Sensing Circuit Page 9 of 20 www.irf.com 09/09/08 INDUCTOR DCR CURRENT SENSING APPLICATION Referring to the Functional Description Diagram, it can be seen that the shunt function can be accomplished by the DC resistance of the inductor that is already present. Omitting the resistive shunt reduces BOM cost and increases efficiency. In exchange for these two significant advantages two easily compensated design complications are introduced, a time constant and a temperature coefficient. The inductor voltage sensed between the Rcs1 resistors is not simply proportional to the inductor current, but rather is expressed in the Laplace equation below. L VL = L DCR1 + s DCR L R R = CS1 CS2 CCS1 . DCR RCS1 + RCS2 Req = RCS1 RCS2 , which can then be rearranged to Rsum Note that this equation is of the form ax 2 + bx + c = 0 where a=0, b=-Rsum, and c=Req*Rsum. The roots of this quadratic equation will be RCS1 and RCS2. Use the higher value resistor as RCS1 in order to minimize ripple current in CCS1. RCS1 RCS2 = Req . RCS1 + RCS2 1+ 1- 4 A second equation is used to set the full scale inductor current. IFS We now know Req and Rsum, but we do not know the individual resistor values RCS1 or RCS2. The next step is to solve for them simultaneously. By substituting Rsum into the Req equation the following can be written: 2 RCS1 - RCS1 Rsum + Req Rsum = 0 . This inductor time constant is canceled when Let Select a standard value CCS1 that is larger than 4 L . Solve for Req. DCR RSUM RSUM 2 and + RCS2 ) V (R = IG CS1 . Let RT DCR 1- 1- 4 RCS1 = RSUM RCS1 + RCS2 = Rsum and solve for Rsum. Page 10 of 20 RCS1 = RSUM Req www.irf.com Req RSUM 2 09/09/08 THERMAL COMPENSATION FOR INDUCTOR DCR CURRENT SENSING The positive temperature coefficient of the DCR can be compensated if RT varies inversely proportional to the DCR. DCR of a copper coil, as a function of temperature, is approximated by DCR(T ) = DCR (TR ) (1 + (T - TR ) TCRCu ) . (2) TR is some reference temperature, usually 25 C, and TCRCu is the resistive temperature coefficient of copper, usually assumed to be 0.0039 near room temperature. Note that equation 2 is linearly increasing with temperature and has an offset of DCR(TR) at the reference temperature. If RT incorporates a negative temperature coefficient thermistor then temperature effects of DCR can be minimized. Consider a circuit of two resistors and a thermistor as shown below. RT ( T ) = Rs + 1 (4) 1 1 + Rp R th ( T ) using Rth(T) from equation 3. Equation 1 of the last section may be rewritten as a new function of temperature using equations 2 and 4 as follows: Rs Rp where Rth(T) is the thermistor resistance at some temperature T, Rth(T0) is the thermistor resistance at the reference temperature T0, and is the material constant provided by the thermistor manufacturer. Degrees Kelvin are used in equation 3. If RS is large and RP is small, the curvature of the effective network resistance can be reduced from the curvature of the thermistor alone. Although the exponential equation 3 can never compensate linear equation 2 at all temperatures, a spreadsheet can be constructed to minimize error over the temperature interval of interest. The resistance RT of the network shown as a function of temperature is IFS ( T ) = Rth VIG (RCS1 + RCS2 ) . RT ( T ) DCR( T ) (5) With Rs and Rp as additional free variables, use a spreadsheet to solve equation 5 for the desired full scale current while minimizing the IFS(T) variation over temperature. Figure 3 RT Network If Rth is an NTC thermistor then the value of the network will decrease as temperature increases. Unfortunately, most thermistors exhibit far more variation with temperature than copper wire. One equation used to model thermistors is Rth (T ) = Rth (T0 ) e Page 11 of 20 1 1 - T T 0 (3) www.irf.com 09/09/08 TYPICAL 2-PHASE DCR-SENSING APPLICATION The IR3720 is capable of monitoring power in a multiphase converter. A two-phase circuit is shown below. The voltage output of any phase is equal to that of any and every other phase, and monitored at VO as before. If DCR1=DCR2, and RCS1=RCS3, then ICS can be simplified to Output current is the sum of the two inductor currents (IL1 + IL2). Superposition is used to derive the transfer function for multiphase sensing. The voltage on RCS2 due to IL1 is Full scale ICS current corresponds to I L1 DCR1 I CS = ( I L1 + I L 2 ) DCR1 RCS1 + 2 RCS 2 ICSFS = ( RCS 2 || RCS 3 ) RCS1 + ( RCS 2 || RCS 3 ) VIG RT which yields 256 digital current counts (0100 0000 0000 0000). Full scale total inductor current is Likewise, the voltage on RCS2 due to IL2 is I L 2 DCR2 (IL1 + IL 2 )FS = ( RCS 2 || RCS1 ) RCS 3 + ( RCS 2 || RCS1 ) VIG (RCS1 + 2 RCS2 ) RT DCR The current through RCS2 due to both inductor currents is ICS. From the two equations above I CS = I L1 DCR1 RCS 3 + I L 2 DCR2 RCS1 RCS1 RCS 2 + RCS1 RCS 3 + RCS 2 RCS 3 IL1 Phase 1 L 3.3V DCR1 RCS1 Multiphase Converter VO RCS3 CCS1 CCS2 RCS2 GND IR3720 Power Return L VREF DCR2 RT IL2 LOAD VCS Ics Phase 2 VDD T I2C Bus 2 To system Controller RTN Figure 4Two Phase DCR Sensing Circuit Page 12 of 20 www.irf.com 09/09/08 ERROR MANAGEMENT Component value errors external to the IR3720 contribute to power and current measurement error. The power reported by the IR3720 is a function not only of actual power or current, but also of products and quotients of RT, RCS1, RCS2, DCR (or RSHUNT), as well as parameters internal to the IR3720. The tolerance of these components increases the total power or current error. Small signal resistors are typically available in 1% tolerance, but 0.1% parts are available. Shunts are also available at 1% or 0.1% tolerance. The DCR tolerance of inductors can be 5%, but 3% are available. Fortunately, it is not typical that worst-case errors would systematically stack in one direction. It is statistically likely that a high going value would be paired with a low going value to somewhat cancel the error. Because of this, tolerances can be added in quadrature (RSS). As an example, a 3% DCR used with a 1% RT, a 1% RCS, and 3.3% IR3720 contributes Quantization error occurs in digital systems because the full scale is partitioned into a finite number of intervals and the number of the interval containing the measured value is reported. It is not likely that the measured value would correspond exactly to the center of the interval. The error could be as large as half the width of the interval. With a binary word size of eight, full scale is partitioned into 255 intervals. Consider a measurement made near full scale. Any signal in this interval is less than .2% (one-half of 100% / 256) away from the interval's center, and would therefore never have more error than that due to quantization. On the other hand, consider a measurement at one-tenth full scale. One-half of an interval size at this level corresponds to 2% of the reported value! Relative quantization error increases as the measured value becomes small compared to the full-scale value. Quantization error can be reduced by averaging a sequence of returned values. (0.03 )2 + (0.01)2 + (0.01)2 + (0.033 )2 4.7% error to a typical system. Page 13 of 20 www.irf.com 09/09/08 CONFIGURATION REGISTER A configuration register is maintained via the I2C MFR_SPECIFIC_00 command, code # D0h. The low order nibble (d3, d2, d1, d0) contains a binary number N from zero to eight. The averaging interval is 2N milliseconds. N defaults to zero on start up. The next bit (d4) is to be used as a function enable bit. b'1 commands an energy saving shut down mode, and power on default b'0 commands fully functioning mode. d5 high enables the EXTCLK pin to receive the external clock signal, and default d5 low enables the internal clock. The next two bits (d7, d6) program the output parameter. B'00 causes power to be measured and is the power on default state. B'01 causes voltage to be measured. B'10 causes current to be measured. B'11 is not defined and should not be used. The next bit (d8) is used to configure the ALERT# pin. b'0 is the power on default, and commands ALERT# being pulled low when new data is available. b'1 programs the ALERT# to pull low when the programmable threshold level is exceeded, whether it is power, voltage, or current. The results of a configuration register change will be reflected in the OUTPUT REGISTER after previously requested operations have completed. BIT # CONFIGURATION REGISTER d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 Averaging interval (LSB) Averaging interval Averaging interval Averaging interval (MSB) Enable External clock OUTPUT config (LSB) OUTPUT config (MSB) ALERT# configuration ALERT# threshold (LSB + 2) ALERT# threshold ALERT# threshold ALERT# threshold ALERT# threshold ALERT# threshold ALERT# threshold (MSB) Register bits (d15...d9) are the ALERT# threshold register. If the output register is larger than this register, and if (d8) is b'1, then the ALERT# pin will pull low. The two least significant bits of the output register are not represented in the ALERT# threshold register. d15...d9 defaults to zero on start up. Page 14 of 20 www.irf.com 09/09/08 OUTPUT REGISTER The output register is loaded with a two's compliment factor of voltage, current, or power, depending on the last request loaded into the configuration register. I2C "Direct Data Format" is used. The value of the output register is to be multiplied by a scale factor that is derived from equations 1 and 2 above. Maximum power is the product of maximum voltage and maximum current. The range of valid values is indicated in Table 2 below. Table 2 Output Register Range of Returned Values Parameter FS voltage Zero voltage +FS current -FS current +FS power -FS power Returned value (twos compliment binary) 0100 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 1100 0000 0000 0000 0100 0000 0000 0000 1100 0000 0000 0000 Returned value (decimal) 256 0 256 -256 256 -256 A binary point is implicitly located to the left of the first six least significant figures, as in the example below. SYYY YYYY YY.00 0000 The "S" above is the twos compliment sign bit, and the "Y's" are the twos compliment. Six zeros pad out the two byte response. These padding zeros could be considered a factor of the slope, which is allowed by the Direct Data Format. The output register multiplied by its scale factor Kx yields the requested quantity in engineering units of volts, amps, or watts. The equations below convert digital counts to engineering units: VFS when configuration register 256 bits (d7, d6) are set to (01). Voltage = counts VIG (RCS1 + RCS2 ) when 256 RT DCR configuration register bits (d7, d6) are set to (10). Current = counts VFS VIG (RCS1 + RCS2 ) when 256 RT DCR configuration register bits (d7, d6) are set to (00). Power = counts There is but one output register, and it holds the measurement type (voltage, current, or power) last requested by the configuration register. It is incumbent upon the user to establish correct configuration before requesting a read. READ_VOUT, READ_IOUT, and READ_POUT are equivalent in that each returns the contents of the same output register. BIT# d15:d0 OUTPUT REGISTER Output variable, D0 is LSB RESERVED COMMAND CODES Command codes D2h through D5h, D7h, and D8h are reserved for manufacturing use only and could lead to undesirable device behavior. Page 15 of 20 www.irf.com 09/09/08 PACKET PROTOCOL S W R A P = = = = = Start Condition Bus write (lo) Bus read (hi) Acknowledge, = 0 for ACK, =1 for NACK Stop Condition = master to slave = slave to master Bus Write CONFIGURATION Register S Slave Address S see Table 1 W A Command Code A 0 A 1 1 0 1 0 0 0 0 A Data Byte Low A d7 d6 d5 d4 d3 d2 d1 d0 A Data Byte High d15 d14 d13 d12 d11 A P d10 d9 d8 A P Bus Read CONFIGURATION Register S S Slave Slave RA W A Command Code A S Address Address see See 0 A 1 1 0 1 0 0 0 0 A S 1 A Table 1 Table 1 Data Byte Low d7 d6 d5 d4 d3 d2 A d1 d0 A Data Byte High d15 d14 d13 d12 d11 d10 A P d9 d8 1 P Bus Read_VOUT (Output Register for Configuration register Data Byte Low = 01XXXXXX) S S Slave Slave RA W A Command Code A S Address Address see See 0 A 1 0 0 0 1 0 1 1 A S 1 A Table 1 Table 1 Data Byte Low d7 d6 d5 d4 d3 d2 A d1 d0 A Data Byte High d15 d14 d13 d12 d11 d10 A P d9 d8 1 P Bus Read_IOUT (Output Register for Configuration register Data Byte Low = 10XXXXXX) S S Slave Slave RA W A Command Code A S Address Address see See 0 A 1 0 0 0 1 1 0 0 A S 1 A Table 1 Table 1 Data Byte Low d7 d6 d5 d4 d3 d2 A d1 d0 A Data Byte High d15 d14 d13 d12 d11 d10 A P d9 d8 1 P Bus Read_POUT (Output Register for Configuration register Data Byte Low = 00XXXXXX) S S Slave Slave RA W A Command Code A S Address Address see See 0 A 1 0 0 1 0 1 1 0 A S 1 A Table 1 Table 1 Page 16 of 20 Data Byte Low d7 d6 www.irf.com d5 d4 d3 d2 A d1 d0 A Data Byte High d15 d14 d13 d12 d11 d10 A P d9 d8 1 P 09/09/08 PCB PAD AND COMPONENT PLACEMENT The figure below shows suggested pad and component placement. Page 17 of 20 www.irf.com 09/09/08 SOLDER RESIST The figure below shows the suggested solder resist placement. Page 18 of 20 www.irf.com 09/09/08 STENCIL DESIGN The figure below shows a suggested stencil design. Page 19 of 20 www.irf.com 09/09/08 PACKAGE INFORMATION 3X3 MM 10L DFN LEAD FREE Data and specifications subject to change without notice. This product has been designed and qualified for the consumer market. Qualification standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Page 20 of 20 www.irf.com 09/09/08