AS7C251MFT18A-85TQCN - Alliance Semiconductor

December 2004

AS7C251MFT18A

12/24/04, v. 1.2 Alliance Semiconductor 1 of 19

2.5V 1M x 18 flowthrough burst synchronous SRAM

Features

• Organization: 1,048,576 words x18 bits

• Fast clock to data access: 7.5/8.5/10 ns

•Fast OE

access time: 3.5/4.0 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available 100-pin TQFP package

•

Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

Logic block diagram

Selection guide

-75 -85 -10 Units

Minimum cycle time 8.5 10 12 ns

Maximum clock access time 7.5 8.5 10 ns

Maximum operating current 275 250 230 mA

Maximum standby current 90 80 80 mA

Maximum CMOS standby current (DC) 60 60 60 mA

Burst logic

ADV

ADSC

ADSP

CLK

LBO

CLK

CLR

A[19:0]

Address

CLK

Memory

array

DQb

CLK

Byte Write

registers

DQa

CLK

Byte Write

registers

Enable

CLK

Enable

CLK

delay

Output

buffers

Input

registers

Power

down

DQ[a,b]

CE0

CE1

CE2

BWb

BWa

CLK

BWE

GWE

AS7C251MFT18A

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16 Mb 2.5V Synchronous SRAM products list1,2

1 Core Power Supply: VDD = 2.5V + 0.125V

2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect

PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect

FT : Flow-through Burst Synchronous SRAM

NTD1-PL : Pipelined Burst Synchronous SRAM with NTDTM

NTD-FT : Flow-through Burst Synchronous SRAM with NTDTM

Org Part Number Mode Speed

1MX18 AS7C251MPFS18A PL-SCD 166/133 MHz

512KX32

AS7C25512PFS32A PL-SCD 166/133 MHz

512KX36

AS7C25512PFS36A PL-SCD 166/133 MHz

1MX18 AS7C251MPFD18A PL-DCD 166/133 MHz

512KX32

AS7C25512PFD32A PL-DCD 166/133 MHz

512KX36

AS7C25512PFD36A PL-DCD 166/133 MHz

1MX18 AS7C251MFT18A FT 7.5/8.5/10 ns

512KX32

AS7C25512FT32A FT 7.5/8.5/10 ns

512KX36

AS7C25512FT36A FT 7.5/8.5/10 ns

1MX18 AS7C251MNTD18A NTD-PL 166/133 MHz

512KX32

AS7C25512NTD32A NTD-PL 166/133 MHz

512KX36

AS7C25512NTD36A NTD-PL 166/133 MHz

1MX18 AS7C251MNTF18A NTD-FT 7.5/8.5/10 ns

512KX32

AS7C25512NTF32A NTD-FT 7.5/8.5/10 ns

512KX36

AS7C25512NTF36A NTD-FT 7.5/8.5/10 ns

1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of

their respective owners.

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AS7C251MFT18A

Pin configuration for 100-pin TQFP

LBO

100

CE0

CE1

BWb

BWa

CE2

CLK

GWE

BWE

ADSC

ADSP

ADV

TQFP 14 x 20mm

DDQ

SSQ

DQb0

DQb1

SSQ

DDQ

DQb2

DQb3

DQb4

DQb5

DDQ

SSQ

DQb6

DQb7

DQPb

SSQ

DDQ

SSQ

DQPa

DQa7

DQa6

SSQ

DDQ

DQa5

DQa4

DQa3

DQa2

DDQ

SSQ

DQa1

DQa0

SSQ

DDQ

AS7C251MFT18A

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Functional description

The AS7C251MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as

1,048,576 words x18 bits

Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion.

Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst

advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out buffers. ADV is

ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for

the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the

LBO

input.

With

LBO

unconnected or driven HIGH, burst operations use an interleaved count sequence. With

LBO

driven LOW, the device uses a linear

count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled

when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is

incremented internally to the next burst address if BWn and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are

as follows:

•ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

•Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C251MFT18A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP package.

TQFP capacitance

* Guaranteed not tested

TQFP thermal resistance

Parameter Symbol Test conditions Min Max Unit

Input capacitance CIN*VIN = 0V - 5 pF

I/O capacitance CI/O*VOUT = 0V - 7 pF

Description Conditions Symbol Typical Units

Thermal resistance

(junction to ambient)1

1 This parameter is sampled

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer θJA 40 °C/W

4–layer θJA 22 °C/W

Thermal resistance

(junction to top of case)1θJC 8°C/W

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AS7C251MFT18A

Signal descriptions

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.

CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is

inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock

edges when ADSC is active or when CE0 and ADSP are active.

ADSP I SYNC Address strobe processor. Asserted LOW to load a new bus address or to enter standby

mode.

ADSC I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

ADV I SYNC Advance. Asserted LOW to continue burst read/write.

GWE I SYNC Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]

control write enable.

BWE I SYNC Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs.

BW[a,b] I SYNC

Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is

LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write

cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read

mode.

LBO ISTATIC

Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When

driven LOW, device follows linear Burst order. This signal is internally pulled High.

ZZ I ASYNC Sleep. Places device in LOW power mode; data is retained. Connect to GND if unused.

NC - - No connects

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Write enable truth table (per byte)

Key: X = don’t care; L = low; H = high; B

, B

= internal write signal

Asynchronous Truth Table

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

Burst sequence table

Function GWE BWE BWa BWb

Write all bytes (a, b) LXXX

HLLL

Write byte a H L L H

Write byte b H L H L

Read HHXX

HLHH

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read LL Dout

LHHigh-Z

Write L X Din, High-Z

Deselected L X High-Z

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address 0 00 11 01 1

2nd Address 0 10 01 11 0

2nd Address 0 11 01 10 0

3rd Address 1 01 10 00 1

4th Address 1 11 00 10 0

4th Address 1 11 00 11 0

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AS7C251MFT18A

Synchronous truth table[4]

CE01

1 X = don’t care, L = low, H = high

CE1 CE2 ADSP ADSC ADV

WRITE

[2]

2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx,

BWE, GWE HIGH. See "Snooze Mode," on page 5 for more information.

Address

accessed CLK Operation DQ

HXXXLX X X NA L to H DeselectHi−Z

L L X L X X X X NA L to H Deselect Hi−Z

L L X H L X X X NA L to H Deselect Hi−Z

L X H L X X X X NA L to H Deselect Hi−Z

L X H H L X X X NA L to H Deselect Hi−Z

L H L L X X X L External L to H Begin read Q

L H L L X X X H External L to H Begin read Hi−Z

L H L H L X H L External L to H Begin read Q

L H L H L X H H External L to H Begin read Hi−Z

XXXHHL H L Next L to HContinue readQ

XXXHHL H H Next L to HContinue readHi−Z

XXXHHH H L Current L to HSuspend readQ

XXXHHH H H Current L to HSuspend readHi−Z

HXXXHL H L Next L to HContinue readQ

HXXXHL H H Next L to HContinue readHi−Z

HXXXHH H L Current L to HSuspend readQ

HXXXHH H H Current L to HSuspend readHi−Z

L H L H L X L X External L to H Begin write D3

3 For write operation following a READ,

must be HIGH before the input data set up time and held HIGH throughout the input hold time

4 ZZ pin is always Low.

XXXHHL L X Next L to HContinue writeD

HXXXHL L X Next L to HContinue writeD

XXXHHH L X Current L to HSuspend writeD

HXXXHH L X Current L to HSuspend writeD

AS7C251MFT18A

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Absolute maximum ratings

Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions may affect reliability.

Recommended operating conditions

Parameter Symbol Min Max Unit

Power supply voltage relative to GND VDD, VDDQ –0.3 +3.6 V

Input voltage relative to GND (input pins) VIN –0.3 VDD + 0.3 V

Input voltage relative to GND (I/O pins) VIN –0.3 VDDQ + 0.3 V

Power dissipation PD–1.8W

DC output current IOUT –20 mAmA

Storage temperature Tstg –65 +150 oC

Temperature under bias Tbias –65 +135 oC

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs VDD 2.375 2.5 2.625 V

Supply voltage for I/O VDDQ 2.375 2.5 2.625 V

Ground supply Vss 0 0 0 V

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AS7C251MFT18A

DC electrical characteristics

† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.

*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC

**VIL min = -1.5 for pulse width less than 0.2 X tCYC

IDD operating conditions and maximum limits

Parameter Sym Conditions Min Max Unit

Input leakage current† |ILI|V

DD = Max, 0V < VIN < VDD -2 2 µA

Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA

Input high (logic 1) voltage VIH

Address and control pins 1.7* VDD+0.3 V

I/O pins 1.7* VDDQ+0.3 V

Input low (logic 0) voltage VIL

Address and control pins -0.3** 0.7 V

I/O pins -0.3** 0.7 V

Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V

Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V

Parameter Sym Conditions -75 -85 -10 Unit

Operating power supply current1

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.

ICC

CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,

IOUT = 0 mA, ZZ < VIL

275 250 230 mA

Standby power supply current

ISB

All VIN ≤ 0.2V or >

– 0.2V,

Deselected,

f = fMax, ZZ < VIL

90 80 80

ISB1 Deselected, f = 0, ZZ < 0.2V,

all VIN ≤ 0.2V or ≥ VDD – 0.2V 60 60 60

ISB2

Deselected, f = f

Max

, ZZ

≥

– 0.2V,

all VIN ≤ VIL or ≥ VIH 50 50 50

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Timing characteristics over operating range

Snooze Mode Electrical Characteristics

Parameter Sym

–75 –85 –10

Unit Notes1

1 See “Notes” on page 16.

Min Max Min Max Min Max

Cycle time tCYC 8.5–10–12– ns

Clock access time tCD –7.5 – 8.5 – 10 ns

Output enable low to data valid tOE – 3.5 – 4.0 – 4.0 ns

Clock high to output low Z tLZC 2.5 – 2.5 – 2.5 – ns 2,3,4

Data output invalid from clock high tOH 3.0 – 3.0 – 3.0 – ns 2

Output enable low to output low Z tLZOE 0 – 0 – 0 – ns 2,3,4

Output enable high to output high Z tHZOE - 3.5 – 4.0 - 4.0 ns 2,3,4

Clock high to output high Z tHZC - 3.5 – 4.0 - 4.0 ns 2,3,4

Output enable high to invalid output tOHOE 0–0–0–ns

Clock high pulse width tCH 2.5 – 3.0 – 4.0 – ns 5

Clock low pulse width tCL 2.5 – 3.0 – 4.0 – ns 5

Address setup to clock high tAS 2.0 – 2.0 – 2.0 – ns 6

Data setup to clock high tDS 2.0 – 2.0 – 2.0 – ns 6

Write setup to clock high tWS 2.0 – 2.0 – 2.0 – ns 6,7

Chip select setup to clock high tCSS 2.0 – 2.0 – 2.0 – ns 6,8

Address hold from clock high tAH 0.5 – 0.5 – 0.5 – ns 6

Data hold from clock high tDH 0.5 – 0.5 – 0.5 – ns 6

Write hold from clock high tWH 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock high tCSH 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock high tADVS 2.0 – 2.0 – 2.0 – ns 6

ADSP setup to clock high tADSPS 2.0 – 2.0 – 2.0 – ns 6

ADSC setup to clock high tADSCS 2.0 – 2.0 – 2.0 – ns 6

ADV hold from clock high tADVH 0.5 – 0.5 – 0.5 – ns 6

ADSP hold from clock high tADSPH 0.5 – 0.5 – 0.5 – ns 6

ADSC hold from clock high tADSCH 0.5 – 0.5 – 0.5 – ns 6

Description Conditions Symbol Min Max Units

Current during Snooze Mode ZZ > VIH ISB2 50 mA

ZZ active to input ignored tPDS 2cycle

ZZ inactive to input sampled tPUS 2cycle

ZZ active to SNOOZE current tZZI 2cycle

ZZ inactive to exit SNOOZE current tRZZI 0cycle

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AS7C251MFT18A

Key to switching waveforms

Timing waveform of read cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

don’t careFalling inputRising input Undefined

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

CSS

ADVH

HZOE

ADSCS

ADSCH

LOAD NEW ADDRESS

ADV inserts wait states

A2A1 A3

Dout

Q(A2Ý10)

Q(A2Ý11)

Q(A3)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A3Ý11)

Q(A1)

HZC

LZOE

CSH

Read

Q(A1)

Suspend

Read

Q(A1)

Read

Q(A2)

Burst

Read

Q(A 2Ý01

)

Read

Q(A3) DSEL

Burst

Read

Q(A 2Ý10

)

Suspend

Read

Q(A 2Ý10

)

Burst

Read

Q(A 2Ý11

)

Burst

Read

Q(A 3Ý01

)

Burst

Read

Q(A 3Ý10

)

Burst

Read

Q(A 3Ý11

)

CE1

AS7C251MFT18A

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Timing waveform of write cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

CYC

ADSPS

ADSPH

ADSCS

ADSCH

CSS

ADVS

CLK

ADSP

ADSC

Address

BWE

CE0, CE2

ADV

Din

CSH

ADVH

D(A2Ý01)

D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A1) D(A2Ý11)

ADV SUSPENDS BURST

ADSC LOADS NEW ADDRESS

A1 A2 A3

CE1

BW[a:b]

Read

Q(A1)

Suspend

Write

D(A1)

Read

Q(A2)

Suspend

Write

D(A 2

)

ADV

Burst

Write

D(A 2Ý01

)

Suspend

Write

D(A 2Ý01

)

ADV

Burst

Write

D(A 2Ý10

)

Write

D(A 3

)

Burst

Write

D(A 3Ý01

)

ADV

Burst

Write

D(A 2Ý11

)

ADV

Burst

Write

D(A 3Ý10

)

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AS7C251MFT18A

Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

Address

BWE

CE0, CE2

ADV

Din

Dout

ADVH

LZOE

LZC

Q(A1)

Q(A3Ý01)

D(A2)

Q(A3)

Q(A3Ý10) Q(A3Ý11)

A1 A2 A3

CE1

HZOE

Suspend

Read

Q(A1)

Read

Q(A1)

Suspend

Write

D(A 2

)

ADV

Burst

Read

Q(A 3Ý01

)

Suspend

Read

Q(A 3Ý11

)

ADV

Burst

Read

Q(A 3Ý10

)

ADV

Burst

Read

Q(A 3Ý11

)

Read

Q(A2)

Read

Q(A3)

BW[a:b]

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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)

Note: ADV is don’t care here.

CYC

ADSCH

CLK

ADSC

ADDRESS

ADSCS

A3 A4 A6

A5 A7 A8 A9

BWE t

CSH

CE0,CE2

CSS

LZOE

HZOE

Q(A1) Q(A2) Q(A3) Q(A4) Q(A9) Q(A10)

D(A6) D(A7)

D(A5)

Dout

Din

READ

Q(A1)

READ

Q(A2)

READ

Q(A3)

READ

Q(A4)

WRITE

D(A5)

WRITE

D(A6)

WRITE

D(A7)

WRITE

D(A8)

READ

Q(A10)

CE1

A10

D(A8)

READ

Q(A9)

BW[a:b]

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AS7C251MFT18A

Timing waveform of power down cycle

W[a:b] is don’t care.

CYC

ADSPS

CLK

ADSP

ADDRESS A1

ADSPS

BWE

CSH

CE0,CE2

CSS

ADV

LZOE

HZOE

Q(A1) Q(A2)

Dout

Din

ADSC

HZC

PDS

Sleep

ZZ Setup Cycle

PUS

ZZ Recovery Cycle Normal Operation Mode

CE1

Q(A2(

01))

BW[a:b]

READ

Q(A1)

READ

Q(A1Ý01)

READ

Q(A2)

READ

Q(A2Ý01)

State

ZZI

SB2

RZZI

supply

AS7C251MFT18A

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AC test conditions

Notes

1 For test conditions, see “AC Test Conditions”, Figures A, B, and C.

2 This parameter is measured with output load condition in Figure C.

3 This parameter is sampled but not 100% tested.

HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.

CH is measured as high above VIH, and tCL is measured as low below VIL.

6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to

GWE

BWE

, and

BW[a,b]

8 Chip select refers to

CE0

CE1

, and

CE2

= 50

Ω

OUT

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+2.5V

• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.

• Input pulse level: GND to 2.5V. See Figure A.

• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.25V.

= V

DDQ

Thevenin equivalent:

353

Ω/1538Ω

5 pF*

319

Ω/1667Ω

OUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+2.5V

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AS7C251MFT18A

Package dimensions

100-pin TQFP (quad flat pack)

He E

TQFP

Min Max

A1 0.05 0.15

A2 1.35 1.45

b0.22 0.38

c0.09 0.20

D13.90 14.10

E19.90 20.10

e0.65 nominal

Hd 15.85 16.15

He 21.80 22.20

L0.45 0.75

L1 1.00 nominal

α0° 7°

Dimensions in millimeters

A1 A2

AS7C251MFT18A

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Ordering information

Note:

Add ‘N’ to the above part numbers for Lead Free Parts (Ex.

AS7C251MFT18A-85TQCN)

Part numbering guide

1. Alliance Semiconductor SRAM prefix

2. Operating voltage: 25 = 2.5V

3. Organization:

4. Flow-through mode

5. Organization: 18 = x18

6. Production version: A = first production version

7. Clock access time: [-75 = 7.5 ns;-85 = 8.5 ns; -10 = 10.0 ns]

8. Package type: TQ = TQFP

9. Operating temperature: C = commercial (

C to 70

C); I = industrial (

-40

C to 85

10. N = Lead Free Part

Package &Width –75 –85 –10

TQFP x18 AS7C251MFT18A-75TQC AS7C251MFT18A-85TQC AS7C251MFT18A-10TQC

AS7C251MFT18A-75TQI AS7C251MFT18A-85TQI AS7C251MFT18A-10TQI

AS7C 25 1M FT 18 A –XX TQ C/I X

4567

8910

AS7C251MFT18A

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C251MFT18A

Document Version: v. 1.2

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