19-1081; Rev 1; 8/96 MAAL/V +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down General Description The MAX113/MAX117 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital con- verters (ADCs). They operate from a single +3V supply and use a half-flash technique to achieve a 1.8ys con- version time (400ksps). A power-down pin (PWRDN) reduces current consumption to 1A typical. The devices return from power-down mode to normal oper- ating mode in less than 900ns, allowing large supply- current reductions in burst-mode applications. (In burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals.) Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (uP) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel yP data bus or system input port. The MAX113/MAX117 input/reference configuration enables ratiometric operation. The 4-channel MAX113 is available in a 24-pin DIP or SSOP. The 8-channel MAX117 is available in a 28-pin DIP or SSOP. For +5V applications, refer to the MAX1 14/MAX118 data sheet. Applications Portable Equipment Remote Data Acquisition Battery-Powered Systems System-Health Monitoring Communications Systems Features # +3.0V to +3.6V Single-Supply Operation 4 (MAX113) or 8 (MAX117) Analog Input Channels Low Power: 1.5mA (operating mode) 1p/A (power-down mode) Total Unadjusted Error < 1LSB Fast Conversion Time: 1.8ps per Channel No External Clock Required Internal Track/Hold Ratiometric Reference Inputs Internally Connected 8th Channel Monitors Reference Voltage (MAX117) -*f -ftethUemhU OH OO Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX113CNG 0C to +70C 24 Narrow Plastic DIP MAX113CAG 0C to +70C 24 SSOP MAX113C/D 0C to +70C Dice* MAX113ENG -40C to +85C 24 Narrow Plastic DIP MAX113EAG -40C to +85C 24 SSOP MAX113MRG ~~ s-55C to +125C =- 24 Narrow CERDIP** Ordering Information continued at end of data sheet. Dice are specified at Ta = +25C, DC parameters only. Contact factory for availability. Pin Configuration appears at end of data sheet. Functional Diagram *IN7 D7 D6 D5 *ING D4 *IN5 IN4 IN3 IN2 IN1 4-BIT D3 FLASH D2 ADC Di (4LSBs) DO TIMING AND CONTROL MAAXLAVI MAX1 13/MAX117 AO A 2 REF- PWRDN cs *MAX117 ONLY MODE iNT WRRDY MA AXILMA Maxim Integrated Products 1 For free samples & the latest literature: http:/)www.maxim-ic.com, or phone 1-800-998-8800 ZLELXVWELLXVWMAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down ABSOLUTE MAXIMUM RATINGS VDD to GND oe cece tee eee e eee teeter tee eeereaneaeeee -0.3V to +7V Digital Input Voltage to GND........ ee -0.3V to (Vpp + 0.3V) Digital Output Voltage to GND... -0.3V to (VoD + 0.3V) REF+ to GND ( ( ) -0.3V to (VpD + 0.3V) REF- to GND...... -0.3V to (VpD + 0.3V) IN_ to GND 00 eee ee eee cette eeeeeeereeeeeeee -0.3V to (VpD + 0.3V) Continuous Power Dissipation (Ta = +70C) 24 Narrow Plastic DIP (derate 13.33MW/C above +70C) ue ees 1.08W 24 SSOP (derate 8.00mMW/C above +70C)......... 640mW 24 Narrow CERDIP (derate 12.50mW/C above +70C) .....1W 28 Wide Plastic DIP (derate 14.29mMW/C above +70C) ue eee eee 1.14W 28 SSOP (derate 9.52mW/C above +70C)......... 762mW 28 Wide CERDIP (derate 16.67mW/C above +70C)....1.33W Operating Temperature Ranges MAX113C_G/MAX117C_| oe eeeeeeeeseesseeereseteeearees MAX113E_G/MAX117E_l oo... esseeeeeseseenreeeaes MAX113MRG/MAX117MJI Storage Temperature Range . Lead Temperature (soldering, 10sec) ......... eee +300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), Ta = TMIN to TMAx, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS ACCURACY (Note 1) Resolution N 8 Bits Total Unadjusted Error TUE +1 LSB Differential Nonlinearity DNL No-missing-codes guaranteed +1 LSB Zero-Code Error +1 LSB Full-Scale Error +1 LSB Channel-to-Channel Mismatch +1/4 LSB DYNAMIC PERFORMANCE Signal-to-Noise Plus SINAD MAX11_C/E, fSAMPLE = 400kHZ, fin = 30.273kHz 45 4B Distortion Ratio MAX11_M, fsamPLe = 340kHz, fiIN = 30.725kHz 45 Total Harmonic Distortion THD MAX 1_CIE, fSAMPLE = 400kHz, fin = 30.273kHz 0 dB MAX11_M, fSAMPLE = 340kHz, fin = 30.725kHz -50 Spurious-Free Dynamic SPOR MAX11_C/E, fsaMPLE = 400kHz, fin = 30.273kHz 50 4B Range MAX11_M, fSAMPLE = 340kHz, fin = 30.725kHz 50 Input Full-Power Bandwidth VIN_ = 3Vp-p 0.3 MHz Input Slew Rate, Tracking 0.28 0.5 Vis ANALOG INPUT Input Voltage Range VIN_ VREF- VREF+ Vv Input Leakage Current lIN_. GND < Vin_< Vppb +3 pA Input Capacitance CIN_ 32 pF REFERENCE INPUT Reference Resistance RREF 1 2 4 kQ REF+ Input Voltage Range VREF- VbD Vv REF- Input Voltage Range GND VREF+ Vv 2 MAXLAA+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), Ta = TMIN to TMAx, unless otherwise noted.) ZLELXVWELLXVW PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS LOGIC INPUTS Input High Voltage VINH CS, WR, RD, FWRDN, AO, At, A2 2 Vv MODE 2.4 CS, WR, RD, PWRDN, AO, A1, A2 0.66 Input Low Voltage VINL Vv MODE 0.8 CS, RD, PWRDN, AO, A1, A2 +1 Input High Current lINH WR +3 pA MODE 15 100 Input Low Current INL CS, WR, RD, PWRDN, MODE, AO, A1, A2 +1 pA Input Capacitance (Note 2) CIN CS, WR, RD, PWRDN, MODE, AO, A1, A2 5 8 pF LOGIC OUTPUTS ISINK = 20A, INT, DO-D7 0.1 Output Low Voltage VoL ISINK = 400A, INT, DO-D7 0.4 Vv RDY, IsiInK = 1mA 0.4 Output High Voltage VOH ISOURCE = 20HA, INT, DO-D7 Vop - 0.1 Vv ISQURCE = 400A, INT, DO-D7 Vpop - 0.4 Three-State Current ILKG DO-D7, RDY, digital outputs = OV to Vpp +3 pA (Note2) Capacitance Cout DO-D7, RDY 5 8 pF POWER REQUIREMENTS Supply Voltage Vppb 3.0 3.6 Vv Vpp = 3.6V, CS= RD= ov, | MAX11_C 2.5 Vbb Supply Current IDD PRON = Woo MAX11_E/M 28 8 mA Vpp = 3.0V, CS= RD= ov, | MAX11_C 1.5 3 PWRDN = VpD MAX11_E/M 1.5 3.5 Power-Down Vpp Current CS = RD = Vpp, PWRDN = OV (Note 3) 1 10 pA Power-Supply Rejection PSR VDD = 3.0V to 3.6V, VREF = 3.0V 41/16 +1/4 LSB Note 1: Accuracy measurements performed at VoD = +3.0V. Operation over supply range is guaranteed by power-supply rejection test. Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or Vpp. MAXIM 3MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down TIMING CHARACTERISTICS (VoD = +3V, Ta = +25C, unless otherwise noted.) (Note 4) Ta = +25C Ta = TmIN to TMAX PARAMETER SYMBOL CONDITIONS ALL GRADES MAX117C/E MAX117M UNITS MIN TYP MAX | MIN MAX | MIN MAX Conversion Time tRD < tINTL, CL = 100pF (WR-RD Mode) 'CWR | (Note 5) 18 2.06 24 | ps Conversion Time (RD Mode) tcRD 2.0 24 2.6 ys Power-Up Time tuP 0.9 1.2 1.4 ys CS to RD, WR Setup Time tcss 0 0 0 ns CS to RD, WR Hold Time tesH 0 0 0 ns ns CL = 50pF, CS to RDY Delay tRDY Ri = 5.1kQ to Vpp 100 120 140 ns Data Access Time _ tCRD + tcrp + tcRp + (RD Mode) tacco | CL = 100pF (Note 5) 100 130 150 | "Ss RD to INT Delay _ (RD Mode) tINTH CL = 50pF 100 160 170 180 ns Data Hold Time {DH (Note 6) 100 130 150 ns Minimum Acquisition Time tACQ (Note 7) 450 600 700 ns WR Pulse Width twR 0.6 10 0.66 10 0.8 10 ys Delay Between WR and RD Pulses tRD 0.8 0.8 1.0 HS RD Pulse Width tRD < tiINTL, determined by (WR-RD Mode) tREAD1 tacct 400 500 600 ns Data Access Time tRD < tiINTL, CL = 100pF (WR-RD Mode) tAcct (Note 5) 400 500 600 ns RD to INT Delay tRI 300 340 400 ns WR to INT Delay tint. | CL = 50pF 0.7 1.45 1.6 1.8 ys RD Pulse Width tRD > tINTL, determined by (WR-RD Mode) tREAD2 | tacco 180 220 250 ns Data Access Time tRD > tiINTL, CL = 100pF (WR-RD Mode) tacce (Note 5) 180 220 250 ns WR to INT Delay tiHwR | Pipelined mode, CL = 50pF 180 200 240 ns Data Access Time ar After INT tID Pipelined mode, CL = 100pF 100 130 150 ns Multiplexer Address Hold Time tAH 50 60 70 ns Note 4: Input control signals are specified with t; = tf = 5ns, 10% to 90% of 3V, and timed from a voltage level of 1.3V. Timing delays get shorter at higher supply voltages. See the Conversion Time vs. Supply Voltage graph in the Typical Operating Characteristics to extrapolate timing delays at other power-supply voltages. Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V. Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time. 4 MAXUM+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down Typical Operating Characteristics (Vop = +3V, TA = +25C, unless otherwise noted.) CONVERSION TIME EFFECTIVE BITS vs. vs. AMBIENT TEMPERATURE INPUT FREQUENCY (WR-RD MODE) ; SIGNAL-TO-NOISE RATIO 1.6 5 8.0 s T T T T 8 mE : | fy =80.27kKHz 5 wt wal: 75 5 0 | Vin =2.88Vp-p 5 >. Le PF 7|>,7 7 7 7 7 fsamece = 400ksps =S Lr 7.0 | SNR = 48.848 eg 12 1 < e _ | oe Vpp = 3.6V Le Leet = 65 s- | i us |) | wi = \ I JE 10 a nT av| 5 6 Z | | = m YL "| A DD = fz a \ Fe, Lae 55 en a T a Ja Vpp = 3.0V 5.0 = 06 45 fsaMPLE = 400kHz Vin = 2.98Vp-p 04 4.0 60-20 20 60 100 140 1k 10k 100k 1M 0 40 80 120160200 TEM PERATURE (C) INPUT FREQUENCY (Hz) FREQUENCY (kHz) CONVERSION TIME AVERAGE POWER CONSUMPTION vs. SUPPLY VOLTAGE vs. SAMPLING RATE USING PWRDN 1400 5 MAX113/117-04 MAX113/117-08, 1300 \ 1200 \ 1100 NX 1000 NS N 900 N 1 A MN 7 7 Lo) torp (ns) POWER DISSIPATION (mW) 800 0 28 30 32 34 36 38 4.0 i 10 100 1000 SUPPLY VOLTAGE (V) SAMPLING RATE (ksps) TOTAL UNADJUSTED ERROR SUPPLY CURRENT vs. TEMPERATURE vs. POWER-UP TIME (EXCLUDING REFERENCE CURRENT) 5 g 4 2 4 Vpp = 3.0V 5 g = 3 E aN = b | Yop = 3.3V g 8 fe a = 2 [4 = Pn FP 2 > Lf a Vpp = 3.0V 5 a 1 1 0 0 320 -60 = -20 20 60 100 140 tup (ns) TEM PERATURE (C) MAXIM 5 ZLELXVWELLXVWMAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down Pin Description MAXI13 PIN MAXII7 NAME FUNCTION _ 1 IN6 Analog Input Channel 6 _ 2 IN5 Analog Input Channel 5 1 3 IN4 Analog Input Channel 4 2 4 IN3 Analog Input Channel 3 3 5 IN2 Analog Input Channel 2 4 6 IN4 Analog Input Channel 1 Mode Selection Input. Internally pulled low with a 15yA current source. MODE = 0 5 7 MODE activates read mode; MODE = 1 activates write-read mode (see Digital Interface section). 6 8 DO Three-State Data Output (LSB) 7,8,9 9, 10, 11 D1, D2, D3 Three-State Data Outputs 10 12 RD Read Input. RD must be low to access data (see Digital Interface section). 14 13 INT Interrupt Output. INT goes low to indicate end of conversion (see Digital interface section). 12 14 GND Ground 13 15 REF- Lower limit of reference span. REF- sets the zero-code voltage. Range is GND < VReF- < VREF+- 14 16 REF+ Upper limit of reference span. REF+ sets the full-scale input voltage. Range is Vrer- < VREF+ < Vpp. Internally hardwired to IN8 (Table 1). 15 17 WR/RDY Write-Control Input/Ready-Status Output (see Digital Interface section) 16 18 cs Chip-Select Input. CS must be low for the device to recognize WR or RD inputs. 17, 18,19 19, 20, 21 D4, D5, D6 Three-State Data Outputs 20 22 D7 Three-State Data Output (MSB) _ 23 A2 Multiplexer Channel Address Input (MSB) 21 24 Al Multiplexer Channel Address Input 22 25 AO Multiplexer Channel Address Input (LSB) 23 26 PWRDN Power-Down Input. PWRDN reduces supply current when low. 24 27 VbD Positive Supply, +3.0V to +3.6V _ 28 IN7 Analog Input Channel 7 MAXUM+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down Vp RL=3k DATA DATA OUTPUTS OUTPUTS R_ =3k | CL | CL a) HIGH-7 TO VOY b) HIGH-Z TO VoL Vpp 3k DATA DATA OUTPUTS OUTPUTS 3k | 10pF | 10pF a) VOH TOHIGH-Z b) VoL TOHIGH-Z Figure 1. Load Circuits for Data-Access Time Test Detailed Description Converter Operation The MAX113/MAX117 use a half-flash conversion tech- nique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 com- parators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash con- version and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash com- parators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX113) or eight (MAX117) different analog voltages under microprocessor (uP) control. One of the MAX117s analog channels, IN8, is internally hard- wired and always reads VREF+ when selected. Power-Down Mode In burst-mode or low-sample-rate applications, the MAX113/MAX117 can be shut down between conver- sions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1HA when powered from a single +3V supply. A logic high on PWRDN wakes up the MAX113/MAX117, and the selected analog input enters the track mode. The signal is fully acquired after 900ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can MAXIM Figure 2. Load Circuits for Data-Hold Time Test be started. If the power-down feature is not required, connect PWRDN to Vpp. For minimum current con- sumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reducing the reference current during power-down. Digital Interface The MAX113/MAX117 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The AO, A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum time, taca, before the next conversion starts. Table 1. Truth Table for Input Channel Selection MAX113 MAX117 SELECTED CHANNEL A1 AO A2 A1- AO 0 =O 0 0 0 IN14 | 0 0 1 IN2 1 0 0 1 0 IN3 1 1 0 1 1 IN4 - 1 0 0 IN5 - 1 0 1 IN6 - 1 1 0 IN7 - 1 1 1 INB (reads VREF; if selected) ZLELXVWELLXVWMAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down Read Mode (MODE = 0) In read mode, conversions and data access are con- trolled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of taca. A conversion is initiated by driving CS and RD low. With Ps that can be forced into a wait state, hold RD low until output data appears. The uP starts the conversion, waits, and then reads data with a single read instruction. In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a pP. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not_used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the ris- ing edge of CS or RD. Write-Read Mode (MODE = 1) Figures 4 and 5 show the operating sequence for write- read mode. The comparator inputs track the analog input voltage for the duration of taca. The conversion is initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time (tac) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections). a Using Internal Delay The LP waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs DO-D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Fastest Conversion: Reading Before Delay An external method of controlling the conversion time is shown in Figure 5. The internally generated delay (tINTL) varies slightly with temperature and supply volt- age, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the ris- ing edge of WR, but before INT goes low. This com- pletes the conversion and enables the output buffers 8 PWRDN cs tcss al laca A0-A2 ADDRESS VALID ADDRESS VALID (N + 1) taH RDY WITH EXTERNAL PULL-UP tcrp Do-D7 lacco Figure 3. Read Mode Timing (Mode = 0) sy y__ L\ toss Ic WR WR r 1 a taca > t AH [~~ | IACQ lag A0-A2 ADDRESS N VALID (N) ADDRESS VALID (N +1) 1 = tess le tos RD ~~ \L trace __ t tro > NTH INT * # tint. VALID DATA DO-D7 -----------2 on ren nnn nnn nnn-- rye tacce >| toy le Figure 4. Write-Read Mode Timing (trp > tintL) (Mode = 1) ADDRESS VALID (N + 1) tcsH tbH Figure 5. Write-Read Mode Timing (tRp < tintL) (Mode = 1) MAXUM+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down t [ tcsH - | taca GF it 2 IN A0-A2 Wr inoress | K VALID (N) 7 > tHwe ih ___ a INT tint | lip DO-D7 OLDDATA(N- 1) }--------7---- {NEW DATA(N) Figure 6. Pipelined Mode Timing (WR = RD) (Mode = 1) that contain the conversion result (DO-D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: twR + tRD + tacci = 1800ns. Pipelined Operation Besides the two standard write-read-mode options, pipelined operation can be achieved by connecting WR and RD together (Figure 6). With CS low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion. Analog Considerations Reference Figures 7a, 7b, and 7c show typical reference connec- tions. The voltages at REF+ and REF- set the ADCs analog input range (Figure 10). The voltage at REF- defines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones. The internal resistance from REF+ to REF- can be as low as 1kQ, and current will flow through it even when the MAX113/MAX117 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REF- to break this current path during power-down. The FET should have an on-resistance of less than 2Q with a 3V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a time equal to the power-up delay (tUP) plus the N-channel FETs turn-on time. Although REF+ is frequently connected to VpD, the cir- cuit of Figure 7d uses a low-current, low-dropout, 2.5V voltage reference: the MAX872. Since the MAX872 cannot continuously furnish enough current for the ref- MAXIM IN . GND maxim ow Vpp MAX113 OnE per, MAX117 _L co REF- Figure 7a. Power Supply as Reference Vine t Vpp a, 42.5 vane te Tow TT tr = Vpp MAxim MAX113 REF+ MAX117 volt on ToL * CURRENT PATH MUST STILL EXIST FROM Vix. TO GND REF- OAUF O.1pF tI Figure 7c. Input Not Referenced to GND erence resistance, this circuit is intended for applica- tions where the MAX113/MAX117 are normally in stand- by and are turned on in order to make measurements at intervals greater than 100us. C1 (the capacitor con- nected to REF+) is slowly charged by the MAX872 dur- ing the standby period, and furnishes the reference current during the short measurement period. The 4.7uF value of C1 ensures a voltage drop of less than 1/2LSB when performing four to eight successive conversions. Larger capacitors reduce the error still fur- ther. Use ceramic or tantalum capacitors for C1. ZLELXVWELLXVWMAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down Vpp MAXIM MAX113 REF+ MAX117 * IRML2402 Figure 7d. An N-channel MOSFET switches off the reference load during power-down Initial Power-Up When power is first applied, perform a conversion to initialize the MAX113/MAX117. Disregard the output data. Bypassing Use a 4.7pF electrolytic in parallel with a 0.1pF ceramic capacitor to bypass VDD to GND. Minimize capacitor lead lengths. Bypass the reference inputs with 0.1yF capacitors, as shown in Figures 7a, 7b, and 7c. Analog Inputs Figure 8 shows the equivalent circuit of the MAX113/ MAX117 input. When a conversion starts and WR is low, VIN_ is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resis- tance as high as 1.5kQ without setup problems. For larger resistances, the acquisition time (tacq) must be increased. Internal protection diodes, which clamp the analog input to Vpp and GND, allow the channel input pins to swing from GND - 0.3V to Vpp + 0.3V without damage. However, for accurate conversions near full scale and zero scale the inputs must not exceed Vpp by more than 50mV or be lower than GND by 50mV. 10 MAXIM o MAX113 MUX MAX117 o Ron Vinze ~VAy oO o RN . TH o = = Figure 8. Equivalent Input Circuit R 2k iV Vin ~WW--# 22pF 10pF | MAAXIAA +1 L MAX113 - ~ MAX117 Figure 9. RC Network Equivalent Inout Model QUTPUT CODE FULL-SCALE 44419444 TRANSITION, 11111110 11111101 | | | I / ! | 7 I / / {L9B - Mpere- VREr / 256 I 7 ' / I I 7 | I 7 | / | 00000011 / | 00000010 ! 00000001 ! 7 VRE 00000000 }++-4 -ty 4 Var 2 1 2 3 \ FS INPUT VOLTAGE (LSBs) FS - 1LSB Figure 10. Transfer Function MAXUM+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down If the analog input exceeds 50mV beyond the sup- plies, limit the input current to no more than two milliamperes, as excessive current will degrade the conversion accuracy of the on channel. Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, taca. Transfer Function Figure 10 shows the MAX113/MAX117s nominal trans- fer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (VREF+ - VREF-) / 256. Conversion Rate The maximum sampling rate (fMAx) for the MAX113/ MAX117 is achieved in write-read mode (tRD < tINTL) and is calculated as follows: 1 twr + tap + tar + taca 1 600ns + 800ns + 300ns + 450ns fax = MAX. = 465kHz where twrR = the write pulse width, tRD = the delay between write and read pulses, tR| = RD to INT delay, and tacq = minimum acquisition time. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequencys RMS amplitude to all other ADC output signals. The output spectrum is limit- ed to frequencies above DC and below one-half the ADC sample rate. MAXIM The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADCs resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a per- fect 8-bit ADC can do no better than 50dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 30.27kHz sinusoid at a 400kHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or effective number of bits) the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics). Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequen- cy band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: W2.y2,y2 2 Vo" +35 +Vy0 +...M THD = 20log) S22_ _*_ " "__ V where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADCs noise floor. See the Signal-to-Noise Ratio graph in Typical Operating Characteristics. 11 ZLELXVWELLXVWMAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1A Power-Down __ Ordering Information (continued) Chip Information PART TEMP. RANGE PIN-PACKAGE MAX117CPI 0C to +70C 28 Wide Plastic DIP TRANSISTOR COUNT: 2011 MAX117CAl 0C to +70C 28 SSOP MAX117C/D 0C to +70C Dice* MAX117EPI -40C to +85C 28 Wide Plastic DIP MAX117EAI -40C to +85C 28 SSOP MAX117M4JI -55C to +125C 28 Wide CERDIP** Dice are specified at Ta = +25C, DC parameters only. Contact factory for availability. Pin Configurations TOP VIEW ~ .~ ie -Al Voo Ine [7 | 28] IN7 Ins [2 | 23] PWRDN m5 [2] 27] Von we Fa al a0 na [3 | 26] PWRDN IN1 we [a 5] La] anaxem [ei] 41 no [se] AAAXIAA fra) ai MODE[5 = MAX713 20| D7 MAX117 oo [g Fa] 0s Int [e | j23] A2 [7 Ha] 05 Mobe [7 | 22] 07 we [e Fa] 4 bo|s [21] D D8 | 9 16] CS DI} 9 20] bs RD [10 [15] WAIRDY be fio 19] ba INT [i] ra] Pers D8 }14 18] cS enn [ra] rg] Re PD [12 [17] WRRDY INT [13 | 16] REF+ DIP/SSOP eno [14] 15] REF- DIP/SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel! Drive, Sunnyvale, CA 94086 (408) 737-7600 1996 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products.