$61SP12832 ISST 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM F EATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs JEDEC 100-Pin TQFP and 119-pin PBGA package Single +3.3V, +10%, 5% power supply Power-down snooze mode ADVANCE INFORMATION APRIL 1999 DESCRIPTION The JSST 1S61SP12832 is a high-speed, low-power synchro- nous static RAM designed to provide a burstable, high- performance, secondary cache for the Pentium, 680X0, and PowerPC microprocessors. It is organized as 131,072 words by 32 bits, fabricated with JSS/'s advanced CMOS technology. The device integrates a 2-bit burst counter, high- speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated inter- nally by the IS61SP12832 and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter -166 -150 -133 -117 5 Units tka Clock Access Time 3.5 3.8 4 4 5 ns tke Cycle Time 6 6.7 7.5 8.5 10 ns Frenquency 166 150 133 117 100 MHz This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99ISSF BLOCK DIAGRAM _ MODE AO CLK b> CLK 0570 } BINARY COUNTER . ADV ace Qt rr x Al _ 7 128K x 32 AD: We 3 o-| +d arr MEMORY ed ARRAY 17 15 17 A16-A0 D Q > ADDRESS REGISTER A Lol CE > CLK 32 32 Gw D Q a DHE 2%ct] D eWa BYTE WRITE REGISTERS > CLK ew TT) D DQc Q | > q BYTE WRITE EWS REGISTERS b> CLK ) oa TT) > Dab BD BYTEWRITE| | BWwe REGISTERS > CLK D Q i L_| DQa BWT GaP Bytewrre| tL Bwi REGISTERS > CLK CE2 a) D Q INPUT OUTPUT 32 ee ed ENABLE REGISTERS REGISTERS oo Dayat:o] REGISTER bcik P cik Oc Lqi CE > CLK ; L D Q | > CLK ENABLE DELAY REGISTER Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 SSP PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin TQFP j= ose BERBER S25 RMEBB oo 1 2 3 4 5 6 7 <<tlo Olalnaininlo> oO olblmbltitit tc / \ OOO Tt CUCU A oO oO oO oO oO oO oO 100 99 98 97 96 95 94 93 92 91 90 89 8B 87 86 85 84 83 82 81 vccQ AG A4 ADSP A8& A16 VCCQ NCLI]1 @ 80 [7 NC B oO oO oO oO oO oO DQc1 [-] 2 79 [7] DQb8 NC CE2 AS ADSC AQ CE NC DQc2 [| 3 78 [1 DQb7 Cc oO Oo oO oO Oo oO oO vocag CL] 4 77 {7 VCCQ NC AT A2 vcc Al2 A15 NC GND [J 5 76 {] GND D oO Oo oO oO oO oO DQc3 [| 6 75 [1 DQb6 DQc1 NC GND NC GND NC DQb8 DQc4 (| 7 74 [7] DQb5 E Oo Oo Oo oO Oo Oo Oo DQc5 (-] 8 73 [4 DQb4 DQc2 DQc3 GND CE GND DQb6 DQb7 DQc6 [_] 9 72 {1 DQb3 F Oo Oo Oo oO Oo Oo oO GND (| 10 71 [5 GND VCCQ DQc4 GND OE GND DQb5 vcCCQ veoca CF] 11 70 [-] VCCQ G QO oO Oo. DQc7 (J 12 69 [1 DQb2 DQc5 DQc6 BW3 ADV BWw2 DQb4 DQb3 DQc8 [_] 13 68 [1 DQb1 H oO oO Oo O oO oO Nc CJ 14 67 [1 GND DQc7 DQc8 GND GW GND DQb2 DQb1 vcc (J 15 66 [1 NC J O O O O O O O NC | 16 65 | vec vccQ vcc NC Vcc NC vcc VCCQ GND [-] 17 64 [7 ZZ K Oo O Oo O O O Dadi (| 18 63 [1 DQas DQd1 DQd2 GND CLK GND DQa7 DQa8s Dad CI 19 62 1] DQaz7 L Oo Oo Oo Oo oO oO O Vcoca [-] 20 61 [4 veca DQd4 DQd3 BW4 NG BW1 DQa5 DQa GND CJ 21 60 [9 GND M Oo O Oo oO O Oo O DQd3 C] 22 59 [1 DQa VCCQ DQd5 GND BWE GND DQa4 VCCQ DQd4 C2] 23 58 [ DQas N O O O O O O DQds [| 24 57 | DQa4 DQd6 -DQd7_ GND A GND DQa3_ Qa? Dade CJ 25 56 DQa3 r DQd8 o So 9 wo Q DQa1 GND } % 88 F-) GND a veca [| 27 541] vec " a 2 MODE Veo Q Qe Q Dad? || 83 f DQae DQds [_} 29 52 [1] DQat Th O GO GO GO OD QO OO No | 30 st Nc. u Oo Oo A10 Oo Oo Oo O 31 32 38 34 35 36 97 98 39 40 41 42 43 44 45 46 47 48 49 50 Lvea NG MM vCQ) DOuoUO UU OU OU QAtttt tt 72770225 ER ER EE o o> = PIN DESCRIPTIONS AO, Al Synchronous Address Inputs. These G Synchronous Global Write Enable pins must tied to the two LSBs of the CE, CE2, CE2 Synchronous Chip Enable address bus. ____ OE Output Enable A2-A16 Synchronous Address Inputs P DQa-DQd Synchronous Data Input/Output CLK Synchronous Clock y P P MODE Burst Sequence Mode Selection ADSP Synchronous Processor Address q Status Vcc +3.3V Power Supply ADSC Synchronous Controller Address GND Ground Status Vcca Isolated Output Buffer Supply: DV Synchronous Burst Address Advance +3.3V BW1-BW4 Synchronous Byte Write Enable ZZ Snooze Enable BWE Synchronous Byte Write Enable GNDa Isolated Output Buffer Ground Integrated Silicon Solution, Inc. 1-800-379-4774 3 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 TRUTH TABLE Address __ eee Operation Used CE cCE2 CE2 ADSP ADSC ADV WRITE OE DQ Deselected, Power-down None H Xx Xx Xx L X X X High-2 Deselected, Power-down None L Xx H L Xx X X X High-2 Deselected, Power-down None L L Xx L Xx X X X High-2 Deselected, Power-down None Xx Xx H H L X X X High-2 Deselected, Power-down None Xx 0 Xx H L X X X High-2 Read Cycle, Begin Burst External L H L L x x x X High-Z Read Cycle, Begin Burst External L H L H 0 x Read X High-Z Write Cycle, Begin Burst External L H L H L x Write X High-Z Read Cycle, Continue Burst Next Xx Xx Xx H H L Read L Q Read Cycle, Continue Burst Next x x x H H L Read H High-Z Read Cycle, Continue Burst Next H Xx Xx Xx H L Read L Q Read Cycle, Continue Burst Next H x x x H L Read H High-Z Write Cycle, Continue Burst Next x x x H H L Write X High-Z Write Cycle, Continue Burst Next H x x x H L Write X High-Z Read Cycle, Suspend Burst Current x x x H H H Read L Q Read Cycle, Suspend Burst Current x x x H H H Read H High-Z Read Cycle, Suspend Burst Current H x x x H H Read L Q Read Cycle, Suspend Burst Current H x x x H H Read H High-Z Write Cycle, Suspend Burst Current x x x H H H Write X High-Z Write Cycle, Suspend Burst Current H x x x H H Write X High-Z PARTIAL TRUTH TABLE Function GW BWE BWi BW2 BWs BW4 Read H H X X X X Read H L H H H H Write Byte 1 H L L H H H Write All Bytes H L L L L L Write All Bytes L x x x xX xX Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 INTERLEAVED BURST ADDRESS TABLE (MODE = Vcca or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDa) o At', AO = 1,1 S \ ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit TBIAS Temperature Under Bias 40 to +85 C TsTG Storage Temperature 55 to +150 C Pb Power Dissipation 1.6 Ww lout Output Current (per I/O) 100 mA Vin, Vout Voltage Relative to GND for I/O Pins 0.5to Vcca+03 V VIN Voltage Relative to GND for 0.5 to Vcc + 0.5 Vv for Address and Control Inputs Vcc Voltage on Vcc Supply Relatiive to GND 0.5 to 4.6 Vv Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. [SSP Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 [SST OPERATING RANGE Range Ambient Temperature Vcc Commercial 0C to +70C 3.3V, +10%, -5% Industrial 40C to +85C 3.3V, +10%, -5% DC ELECTRICAL CHARACTERISTICS" (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage loH = 4.0 mA 2.4 _ Vv VoL Output LOW Voltage loL=8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.0 Vceca+0.3 Vv ViL Input LOW Voltage 0.3 0.8 Vv Iu Input Leakage Current GND < Vin < Veca) Com. -2 2 uA Ind. -5 5 ILo Output Leakage Current GND < Vout < Veca, OE = Vin Com. 2 2 LA Ind. -5 5 POWER SUPPLY CHARACTERISTICS (Over Operating Range) -166 -150 -133 -117 5 Symbol Parameter Test Conditions Typ. Max. Typ. Max. Typ. Max. Typ. Max Typ. Max. Unit lec AC Operating Device Selected, Com. 200 230 190 220 180 210 175 205 170 200 mA Supply Current All Inputs = Vit or Vin Ind. 200 230 190 220 185 215 180 210 mA OE = Vin, Vec = Max. Cycle Time > tke min. Isp Standby Current Device Deselected, Com. 45 70 45 70 45 70 45 65 45 65 mA Vcc = Max., Ind. 50 80 50 80 50 75 50 75 mA All Inputs = Vin or Vi CLK Cycle Time 2 tke min. Iz Power-down Mode ZZ = Vcca Com. 5 5 6 5 6 mA Current Clock Running Ind 15 15 15 15 15 mA All Inputs < GND +0.2V or 2 Vec-0.2V Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to Vcca. 2. The MODE pin should be tied to Vec or GND. It exhibits +10 pA maximum leakage current when tied to < GND + 0.2V or > Vee - 0.2V. 6 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 SSP CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 5 pF Court Input/Output Capacitance Vout = OV 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vec = 3.3V. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS 3179 3.3V Zo = 500 OUTPUT Output 50 Buffer 30 pF 5 pF 351 Including jig and 1 1.5V scope = = Figure 1 Figure 2 Integrated Silicon Solution, Inc. 1-800-379-4774 7 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 [SST READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 -150 -133 -117 5 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fMAX Clock Frequency _ 166 _ 150 _ 133 _ 117 _ 100 MHz tke Cycle Time 6 _ 6.7 _ 75 _ 8.5 _ 10 _ ns tKH Clock High Time 2.4 _ 2.6 _ 2.8 _ 3.4 _ 4 _ ns tKL Clock Low Time 2.4 _ 2.6 _ 2.8 3.4 4 ns tka Clock Access Time _ 3.5 _ 3.8 _ 4 4 5 ns tkax'? ~~ Clock High to Output Invalid 15 _ 15 _ 15 15 25 ns tkaiz") Clock High to Output Low-Z 0 _ 0 _ 0 _ 0 _ 0 _ ns tkaHz"2) Clock High to Output High-Z 15 6 15 6.7 15 75 1.5 8.5 1.5 10 ns toEa Output Enable to Output Valid _ 3.5 _ 3.5 _ 3.8 _ 4 _ 5 ns toeax" Output Disable to Output Invalid 0 _ 0 _ 0 _ 0 _ 0 ns toeiz") Output Enable to Output Low-Z 0 _ 0 _ 0 _ 0 _ 0 ns toeHz" Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 4 2 5 ns tas Address Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tss Address Status Setup Time 15 _ 15 _ 1.5 _ 1.5 _ 1.5 _ ns tws Write Setup Time 1.5 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tces Chip Enable Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tavs Address Advance Setup Time 15 _ 15 _ 1.5 _ 1.5 _ 1.5 _ ns TAH Address Hold Time 0.5 _ 0.5 _ 0.5 0.5 0.5 ns tsH Address Status Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 0.5 ns {WH Write Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 0.5 ns tceH Chip Enable Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 _ 0.5 _ ns tAVH Address Advance Hold Time 0.5 _ 0.5 _ 0.5 0.5 0.5 ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 8 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 READ/WRITE CYCLE TIMING je tC | | | CLK | | {KH {KL | | | | | | | tes {SH ! | ADSP is blocked by CE i ra we | | | | | | SSE AEF BH | | a ate read | | | ms TT TN ota eth I | | | | tus-jerrest tv | Sucpend Burst | | | | | mi WW! A! 7 | ae | | | | | | | | | | | | | wo | | | | | | | | | At5-A0 RD! XRD2 X X RD3 X | | | | | | | | | | | | | | twslesesttwi | | | | | | | | | mae Wee ey 7 wy ae | | | | | | | | | | a SS ooo ove A AA A AY AY | a BW4BWi __| | | | | | | | | | | | | | | | tces- leo te | | | | | CE Masks ADSP | | | i Ar vy waAt | | | | 1 | | _ | | | | toeseriest tcc | | CE2and CE only sampled with AD BP or ADSC | | Us wi \ r\ fl \ \ [ eH AS | Xf" Ut | | | | tCes tCEH | l | | | | | | | | | | | oo NL | | ! | <>| 10EHZ | | | | | | | _ | | | | | OE | J] | \ | | | | | | / I | | p< I I I I I | | | | 1OEOX | | | | | | pe tkax | l DATAOUT b_ HighZ | a HX 2a XX 25 XX Zz MX 2X aa | | l tore | | | | | | tKQHZ | Pf pm FP | | | yi | | | | | | | | PATA t HighZ 4 | } | 1 | , | , | | | | \<_ Pipelined Read tT Single Read le Burst Read ____} _ Unselected Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 [SST WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 -150 -133 -117 5 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tke Cycle Time 6 _ 6.7 _ 75 _ 8.5 _ 10 _ ns tKH Clock High Time 2.4 _ 2.6 _ 2.8 _ 3.4 _ 4 _ ns tKL Clock Low Time 2.4 _ 2.6 _ 2.8 3.4 4 _ ns tas Address Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tss Address Status Setup Time 15 _ 15 _ 1.5 _ 1.5 _ 1.5 _ ns tws Write Setup Time 1.5 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tos Data In Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tces Chip Enable Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tavs Address Advance Setup Time 15 _ 15 _ 1.5 _ 1.5 _ 1.5 _ ns TAH Address Hold Time 0.5 _ 0.5 _ 0.5 0.5 0.5 _ ns tsH Address Status Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 0.5 _ ns tOH Data In Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 _ 0.5 _ ns {WH Write Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 _ 0.5 _ ns tceH Chip Enable Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 _ 0.5 _ ns tAVH Address Advance Hold Time 0.5 _ 0.5 _ 0.5 0.5 0.5 _ ns 10 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 SSP WRITE CYCLE TIMING Le CE2 and CE2 only sampled with ADSP or ADSC | DATAOUT High-Z | | DATAIN High-Z BW4-BW1 only are applied to first oycle of WR2 | 22 XX_% XX_20 XX_20_ XX | | | | | | | | 32 l | | | | | | | | | | | (< Single Write 1-___ Burst Write >- Write Unselected. > Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 [SST SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 -150 -133 -117 5 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tke Cycle Time 6 _ 6.7 _ 75 _ 8.5 _ 10 _ ns tKH Clock High Time 2.4 _ 2.6 _ 2.8 _ 3.4 _ 4 _ ns tKL Clock Low Time 2.4 _ 2.6 _ 2.8 3.4 4 ns tka Clock Access Time _ 3.5 _ 3.8 _ 4 4 5 ns tkax'? Clock High to Output Invalid 15 _ 15 15 2 _ 25 ns tkaiz") Clock High to Output Low-Z 0 _ 0 _ 0 _ 0 _ 0 _ ns tkaHz"2) Clock High to Output High-Z 15 3.6 15 6.7 1.5 75 1.5 8.5 1.5 10 ns toEa Output Enable to Output Valid _ 3.5 _ 3.5 _ 3.9 _ 4 _ 5 ns toeax" Output Disable to Output Invalid 0 _ 0 _ 0 _ 0 _ 0 ns toeiz") Output Enable to Output Low-Z 0 _ 0 _ 0 _ 0 _ 0 ns toeHz" Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 4 2 5 ns tas Address Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns tss Address Status Setup Time 15 _ 15 _ 1.5 _ 1.5 _ 1.5 _ ns tces Chip Enable Setup Time 15 _ 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns TAH Address Hold Time 0.5 _ 0.5 _ 0.5 0.5 0.5 ns tsH Address Status Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 0.5 ns tceH Chip Enable Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 _ 0.5 _ ns tzzs ZZ Standby 2 _ 2 _ 2 _ 2 2 cyc tzzrec ~- ZZ Recovery 2 _ 2 _ 2 _ 2 2 cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99IS61SP12832 SSP SNOOZE AND RECOVERY CYCLE TIMING jetKc | | DATAOUT = High-Z | | ; | ) | | | | | ke-tkKQ>} ia ; | | | | |tKQHZ \ | \ DATANy HighZ | ! \ \ | | <_+ es >I | < tZ2REC oI | Z Lf | | Jp or _ [< Single Read > | Snooze with Data Retention >le Read | | | Integrated Silicon Solution, Inc. 1-800-379-4774 13 ADVANCE INFORMATION SR038-0D 04/16/99ISSF IS61SP12832 ORDERING INFORMATION Commercial Range: 0C to +70C Speed Order Part Number Package 166 MHz IS61SP12832-166TQ TQFP IS61SP12832-166B PBGA 150 MHz IS61SP12832-150TQ TQFP 1IS61SP12832-150B PBGA 133 MHz IS61SP12832-133TQ TQFP 1S61SP12832-133B PBGA 117 MHz IS61SP12832-117TQ TQFP 1IS61SP12832-117B PBGA 5ns IS61SP12832-5TQ TQFP IS61SP12832-5B PBGA Industrial Range: 40C to +85C Speed Order Part Number Package 150 MHz IS61SP12832-150TQI TQFP 133 MHz IS61SP12832-133TQI TQFP 117 MHz IS61SP12832-117TQI TQFP 5ns IS61SP12832-5TQI TQFP I S S I . Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 14 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR038-0D 04/16/99