1
®
FN3127.6
HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
CMOS Analog Switches
This family of CMOS analog switches offers low resistance
switching performance for anal og voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. rON remains
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
0oC and 75oC. rON is nominally 25Ω for HI-5049 and
HI-5051 and 50Ω for HI-5042 through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25oC).
This family of switches also features very low power
operation (1.5mW at 25oC).
There are 7 devices in this switch series which are
differentiated by type of switch action and value of rON (see
Functional Description Table). The HI-504X and HI-505X series
switches can directly replace IH-5040 series devices, and are
functionally compatible with the DG180 and DG190 family
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance. . . . . . . . . . . . . . . . . . . . . . . . . 25Ω
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns
- Turn-Off Time. . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
•Pb-Free Available (RoHS Compliant)
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
Functional Description
PART NUMBER TYPE rON
HI-5042 SPDT 50Ω
HI-5043 Dual SPDT 50Ω
HI-5047 4PST 50Ω
HI-5049 Dual DPST 25Ω
HI-5051 Dual SPDT 25Ω
S
N
AP
D
Data Sheet April 6, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
DWG. #
HI1-5042-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5043-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5043-5 0 to 75 16 Ld CERDIP F16.3
HI3-5043-5 0 to 75 16 Ld PDIP E16.3
HI3-5043-5Z
(See Note) 0 to 75 16 Ld PDIP*
(Pb-free) F16.3
HI9P5043-5 0 to 75 16 Ld SOIC M16.15
HI9P5043-5Z
(See Note) 0 to 75 16 Ld SOIC
(Pb-free) M16.15
HI1-5047-5 0 to 75 16 Ld CERDIP F16.3
HI1-5049-5 0 to 75 16 Ld CERDIP F16.3
HI1-5051-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5051-5 0 to 75 16 Ld CERDIP F16.3
HI3-5051-5 0 to 75 16 Ld PDIP E16.3
HI3-5051-5Z
(See Note) 0 to 75 16 Ld PDIP *
(Pb-free) E16.3
HI9P5051-9 -40 to 85 16 Ld SOIC M16.15
HI9P5051-9Z
(See Note) -40 to 85 16 Ld SOIC
(Pb-free) M16.15
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50Ω)4PST
HI-5047 (50Ω)
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Dual Control
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)DUAL DPST
HI-5049 (25Ω)
NOTE: Unused pins may be internally connected. Ground all
unused pins.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D1
D2
S2
S1
A
VL
VR
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D2
D1
S1
S2
S4
D4
D3
VL
VR
A
S3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D3
S3
S4
D4
V-
V+
S1
S2
A2
VL
VR
A1
D1
D2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
S1
S2
A2
VL
VR
A1
D3
S3
S4
D4
D1
D2
HI-5042 thru HI-5051
3
Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT)
SPDT
HI-5042 (50Ω)DUAL SPDT
HI-5043 (50Ω)
4PST
HI-5047 (50Ω)DUAL DPST
HI-5049 (25Ω)DUAL SPDT
HI-5051 (25Ω)
12 11
13 14
15
A
1
16
3
4
V+VL
S1
S2
V-VR
D1
D2
1
3
8
6
5
9
10
12
15
4
16 11
13 14
V+VL
S1
A1
A2
S4
S3
S2
V-VR
D1
D2
D4
D3
12 11
13 14
15
3
4
1
16
8
9
6
5
D1
D2
D4
D3
S1
S3
S4
S2
A
V-VR
V+VL
1
3
8
6
5
9
10
12
15
4
16 11
13 14
V+VL
S1
A1
A2
S4
S3
S2
V-VR
D1
D2
D4
D3
1
3
8
6
5
9
10
12
15
4
16 11
13 14
D1
D2
D4
D3
S1
A1
A2
S4
S3
S2
V-VR
V+VL
HI-5042 thru HI-5051
4
Schematic Diagrams
NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT (NOTE)
SWITCH CELL
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
P14 P15 P16
QN1
QP1
25µA
P13
V+
QN2
N14 N15 N16
QP2
R7
QP3 QP4
QP5 QP6
QP8
R2 QP7
R4
R5
R6 R3
TO VR’
to VL’
V-
V+
25µA
25µA
25µA
100µA
16µA
25µA
VL
VR
35µA
N13
P2 N2
N1
N3
V-
P1
IN OUT
V+
A1 (A2)
A1 (A2)
N1
N2
P2
P1
P3
P5
P4
P6 P7 P8 P9 P10 P11 P12
A1
A2
N12N11N10N9N8N7N6
N5
N4
N3
V-
VL'
VR'
V+
V+
D2
D1
V-
AR4
200Ω
A1
A2
HI-5042 thru HI-5051
5
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
VR to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+, V-
Digital and Analog Input Voltage . . . . . . . . . . . .(V+) +4V to (V-) -4V
Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA
Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
Operating Conditions
Temperature Range
HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 75 22
SOIC Package . . . . . . . . . . . . . . . . . . . 110 N/A
PDIP Package* . . . . . . . . . . . . . . . . . . 90 N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Storage Temperature . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Log ic Le vel H igh ) = 2.4 V, V AL ( Logic L eve l Lo w) = 0. 8V, VL=5V,
Unless Otherwise Specified . For Test Co ndition s, Consult Performa nce Char acteristics,
Unused Pins ar e Grou nd ed
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
DYNAMIC CHARACTERISTICS
Switch ON Time, tON (Note 5) 25 - 370 500 - 370 500 ns
Switch OFF Time, tOFF (Note 5) 25 - 280 500 - 280 500 ns
Charge Injection, Q (Note 3) 25 - 5 20 - 5 - mV
OFF Isolation (Note 4) 25 75 80 - - 80 - dB
Crosstalk (Note 4) 25 -80 -88 - - -88 - dB
Input Switch Capacitance, CS(OFF) 25 - 11 - - 11 - pF
Output Switch Capacitance, CD(OFF) 25 - 11 - - 11 - pF
Output Switch Capacitance, CD(ON) 25 - 22 - - 22 - pF
Digital Input Capacitance, CA25 - 5 - - 5 - pF
Drain To Source Capacitance, CDS(OFF) 25 - 0.5 - - 0.5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL Full - - 0.8 - - 0.8 V
Input High Threshold, VAH Full 2.4 - - 2.4 - - V
Input Leakage Current (High or Low), IAFull - 0.01 1.0 - 0.01 1.0 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range Full -15 - +15 -15 - +15 V
ON Resistance, rON
HI-5042 to HI-5047 (Note 2) 25 - 50 75 - 50 75 Ω
Full - - 150 - - 150 Ω
HI-5049, HI-5051 (Note 2) 25 - 25 45 - 25 45 Ω
Full - - 50 - - 50 Ω
Channel-to-Channel Match, ∆rON
HI-5042 to HI-5047 25 - 2 10 - 2 10 Ω
HI-5049, HI-5051 25 - 1 5 - 1 5 Ω
HI-5042 thru HI-5051
6
OFF Input or Output Leakage Current,
IS(OFF) = ID(OFF) 25 - 0.8 2 - 0.8 2 nA
Full - 100 200 - 100 200 nA
ON Leakage Current, ID(ON) 25 -0.012 -0.012 nA
Full - 2 200 - 2 200 nA
POWER REQUIREMENTS
Quiescent Power Dissipation, PD25 - 1.5 - - 1.5 - mW
I+, I-, IL, IR25 - - 0.2 - - 0.3 mA
I+, +15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
I-, -15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IL, +5V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IR, Ground Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
NOTES:
2. VOUT = ±10V, IOUT = 1mA.
3. VIN = 0V, CL = 10nF.
4. RL = 100Ω, f = 100kHz, VIN = 2.0VP-P, CL = 5pF.
5. VAL = 0V, VAH = 5V.
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Log ic Le vel H igh ) = 2.4 V, V AL ( Logic L eve l Lo w) = 0. 8V, VL=5V,
Unless Otherwise Specified . For Test Co ndition s, Consult Performa nce Char acteristics,
Unused Pins ar e Grou nd ed (Continued)
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 1C. N O R MA L I Z E D O N RE S I S T A N C E vs TE M P E RA T U R E
FIGURE 1. ON RESISTANCE
IN OUT
1mA
V2
rON = 1mA
V2
±VIN
ANALOG SIGNAL LEVEL (V)
ON RESISTANCE (Ω)
80
60
40
20
0-15 -10 -5 0 5 10 15
V+ = +10V
V- = -10V
V+ = +12V
V- = -12V
V+ = +15V
V- = -15V
TEMPERATURE (oC)
-50 -25 0 75 100 1255025
0.6
1.2
1.1
1.0
0.9
0.8
0.7
NORMALIZED ON RESISTANCE
(REFERRED TO 25oC)
VIN = 0V
HI-5042 thru HI-5051
7
FIGURE 2A. LEAKAGE CURRENTS vs TEMPERATURE FIGURE 2B. TEST CIRCUITS
FIGURE 2. LEAKAGE CURRENTS
FIGURE 3A. NORMALIZED ON RESISTANCE vs ANALOG
CURRENT FIGURE 3B. TEST CIRCUIT
FIGURE 3. NORMALIZED ON RESISTANCE
FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4B. TEST CIRCUIT
FIGURE 4C. OFF ISOLATION
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
ID(ON)
TEMPERATURE (oC)
75 100 1255025
IS(OFF) = ID(OFF)
100nA
10nA
1nA
100pA
10pA
LEAKAGE CURRENT
IN OUT AA
±10V
±
IN OUT
A
±10V
ID(ON)
ID(OFF)
IS(OFF)
10V
ON LEAKAGE CURRENT
OFF LEAKAGE CURRENT
ANALOG CURRENT (mA)
40 60 80200
1.4
NORMALIZED ON RESISTANCE
1.3
1.2
1.1
1.0
(REFERRED TO 1mA)
IN OUT
±VIN
I
rON VIN
I
---------=
FREQUENCY (Hz)
10K 100K 1M1001
200
OFF ISOLATION (dB)
160
120
80
40
1K10
RL = 100Ω
RL = 10kΩ
50ΩRL
VOUT
VIN
2VP-P
IN OUT
OFF ISOLATION 20 Log VIN
VOUT
----------------
=
HI-5042 thru HI-5051
8
FIGURE 5A. CROSSTALK vs FREQUENCY FIGURE 5B. TEST CIRCUIT
FIGURE 5. CROSSTALK
FIGURE 6A. POWER CONSUMPTION vs FREQUENCY FIGURE 6B. TEST CIRCUIT
FIGURE 6. POWER CONSUMPTION
FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
FREQUENCY (Hz)
-200
-160
-120
-80
-40
10K 100K 1M10011K10
0
CROSSTALK (dB)
RL = 100Ω
RL = 10kΩRL = 1kΩ
50Ω
RL
RL
VOUT
VIN
2VP-P
SWITCHED
CHANNEL
CROSSTALK 20 Log VOUT
VIN
----------------
=
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
200
160
120
80
40
10K 100K 1M1K
0
POWER CONSUMPTION (mW)
VR
VL
IL
V+ V-
A
I-
I+
+5V +15V -15V
+10V
-10V
TOGGLE
AT 50%
DUTY
+10V
IN1
IN2
VA
1K 1K
OUT 1
OUT 2
90% 90%
tOFF tON
tON tOFF
90%
90%
VA
OUT 1
OUT 2
VAH
HI-5042 thru HI-5051
9
VA = 0V to 5V
Vertical: 2V/Div.
Horizontal: 200ns/Div.
FIGURE 7C. WAVEFORMS WITH TTL COMPATIBLE LOGIC
INPUT
VA = 0V to 10V
Vertical: 5V/Div.
Horizontal: 200ns/Div.
FIGURE 7D. WAVEFORMS WITH CMOS CO MPATIBLE LOGIC
INPUT
FIGURE 7E. SWITCHING TIMES vs POSITIVE DIGITAL
VOLTAGE FIGURE 7F. SWITCHING TIMES vs NEGATIVE DIGITAL
VOLTAGE
FIGURE 7. SWITCH tON AND tOFF
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
VA
OUTPUT
VA
OUTPUT
DIGITAL “HIGH” (V)
2.4 3.0 3.6 4.2 4.8
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
(NEED INPUT)
DIGITAL “LOW” (V)
00.51.01.5
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
(NEED INPUT)
HI-5042 thru HI-5051
10
HI-5042 thru HI-5051
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
11
HI-5042 thru HI-5051
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) B
MM
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
B0.014 0.019 0.35 0.49 9
C0.007 0.010 0.19 0.25 -
D0.386 0.394 9.80 10.00 3
E0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H0.228 0.244 5.80 6.20 -
h0.010 0.020 0.25 0.50 5
L0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 1 02/02
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HI-5042 thru HI-5051
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2 , 3
N16 168
Rev. 0 4/94
