Rev. 1.1 4/13 Copyright © 2013 by Silico n Laboratories Si550
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
Applications
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC -based approa ch allows the crystal resonator to provid e
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si55 0 IC-based VCXO is factory-configurable
for a wide va riety of user spe cifica tions, incl uding fre qu ency, supply v oltage,
output for mat, tuni ng slope, and temp erature stab ility. Specific conf igurat ions
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
Functional Block Diagram
Available with any frequency from
10 to 945 MHz and select
frequencies to 1.4 GHz
3rd generation DSPLL® with
superior jitter performance (0.5 ps)
3x better temperature stability than
SAW-based oscillators
Excellent PSRR performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency
XO
Any-Frequency
10 M Hz– 1.4 GH z
DSPLL®
Clock Synthesis
ADC
VDD
Vc
OE GND
CLK–
CLK+
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
Si550
REVISION D
Si550
2 Rev. 1.1
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage1VDD 3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current IDD Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
108
99
90
130
117
108
98
mA
tristate mode — 60 75 mA
Output Enable (OE)2VIH 0.75 x VDD ——V
VIL ——0.5V
Operating Temperature Range TA–40 — 85 °C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details.
2. OE pin includes a 17 k resistor to VDD.
Table 2. VC Control Voltage Input
Parameter Symbol Test Cond i tio n Min Ty p Max Units
Control Voltage Tuning Slope1,2,3 KV10 to 90% of VDD —
—
—
—
—
—
33
45
90
135
180
356
—
—
—
—
—
—
ppm/V
Control Voltage Linearity4LVC BSL –5 ±1 +5 %
Incremental –10 ±5 +10 %
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
VC Input Impedance ZVC 500 — — k
Nominal Control Voltage VCNOM @ fO—V
DD/2 — V
Control Voltage Tuning Range VC0V
DD V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
Si550
Rev. 1.1 3
Table 3. CLK± Output Frequency Characteristics
Parameter Symbol Test Condition Min Typ Max Units
Nominal Frequency 1,2,3 fOLVDS/CML/LVPECL 10 — 945 MHz
CMOS 10 — 160 MHz
Temperature Stability1,4 TA= –40 to +85 ºC –20
–50
–100
—
—
—
+20
+50
+100 ppm
Absolute Pull Range1,4 APR ±12 — ±375 ppm
Aging Frequency drift over first year. — — ±3 ppm
Frequency drift over 15 year life. — — ±10
Power up Time5tOSC ——10ms
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM =V
DD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
Parameter Symbol Test Condi tion Min Typ Max Units
LVPECL Output Option1VOmid-level VDD – 1.42 — VDD – 1.25 V
VOD swing (diff) 1.1 —1.9 VPP
VSE swing (single-ended) 0.55 —0.95 VPP
LVDS Output Option2VOmid-level 1.125 1.20 1.275 V
VOD swing (diff) 0.5 0.7 0.9 VPP
CML Output Option2
VO2.5/3.3 V option mid-level — VDD – 1.30 — V
1.8 V option mid-level — VDD – 0.36 — V
VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP
1.8 V option swing (diff) 0.35 0.425 0.50 VPP
CMOS Output Option3VOH IOH =32mA 0.8 x VDD —VDD V
VOL IOL =32mA — — 0.4 V
Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps
CMOS with CL=15pF — 1 — ns
Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: VDD/2 45 — 55 %
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Si550
4 Rev. 1.1
Table 5. CLK± Output Phase Jitter
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)1,2,3
for FOUT > 500 MHz JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.26
0.26 —
—ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.27
0.26 —
—ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.32
0.26 —
—ps
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.40
0.27 —
—ps
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.49
0.28 —
—ps
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.87
0.33 —
—ps
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Si550
Rev. 1.1 5
Phase Jitter (RMS)1,2,3,4,5
for FOUT of 125 to 500 MHz JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.37
0.33 —
—ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.37
0.33 0.4
—ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.43
0.34 —
—ps
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.50
0.34 —
—ps
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.59
0.35 —
—ps
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—1.00
0.39 —
—ps
Table 5. CLK± Output Phase Jitter (Continued)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Si550
6 Rev. 1.1
Phase Jitter (RMS)1,2,5
for FOUT 10 to 160 MHz
CMOS Output Only
JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.63
0.62 —
—ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.63
0.62 —
—ps
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.67
0.66 —
—ps
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.74
0.72 —
—ps
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.83
0.8 —
—ps
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—1.26
1.2 —
—ps
Table 6. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Units
Period Jitter* JPER RMS — 2 — ps
Peak-to-Peak — 14 —
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 5. CLK± Output Phase Jitter (Continued)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Si550
Rev. 1.1 7
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency 74.25 MHz
90 ppm/V
LVPECL
155.52 MHz
45 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–87
–114
–132
–142
–148
–150
n/a
–86
–111
–128
–133
–144
–147
n/a
–75
–100
–116
–124
–135
–146
–147
–65
–90
–109
–121
–134
–146
–147
dBc/Hz
Table 8. Environmental Compliance
The Si550 meets the following qualification test requirements.
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 203
Gross & Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level J-STD-020, MSL 1
Contact Pads J-STD-020, MSL 1
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W
Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W
Ambient Temperature TA–40 — 85 °C
Junction Temperature TJ——125°C
Si550
8 Rev. 1.1
Table 10. Absolute Maximum Ratings1
Parameter Symbol Rating Units
Maximum Op er at ing Temperat ur e TAMAX 85 ºC
Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V
Input Voltage VI–0.5 to VDD + 0.3 V
Storage Temperature TS–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 V
Soldering Temperat ur e (Pb -f re e pr of ile)2TPEAK 260 ºC
Soldering Temperature Time @ TPEAK (Pb-free profile)2tP20–40 seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging F AQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
Si550
Rev. 1.1 9
2. Pin Descriptions
Table 11. Si550 Pin Descriptions
Pin Name Type Function
1 VCAnalog Input Control Voltage
2OE* Input
Output Enable (Polarity = High):
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
Output Enable (Polarity = Low):
0 = clock output enabled
1 = clock output disabled (outputs tri-stated)
3GND Ground Electrical and Case Gr ou n d
4CLK+ Output Oscillator Output
5CLK–
(N/A for CMOS) Output Complementary Output
(N/C for CMOS, make no external connection)
6 VDD Power Power Supply Voltage
*Note: OE includes 17 k pullup resistor to VDD. See Section 3. "Ordering Information" on page 10 for details on OE polarity
ordering options.
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
(Top View)
Si550
10 Rev. 1.1
3. Ordering Information
The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD. Specific device configurations are programmed into the Si550 at time of shipment. Configurations are
specified using the Part Number Configu ration chart show n below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si550 VCXO series is available in an industry-standard, RoHS compliant,
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
Figure 1. Part Number Convention
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
550 VCXO
Product Family
550 X X XXXMXXX D G R
1st Option Code
VDD Ou tput Format Output Enable Polarity
A 3.3 LVPECL High
B 3.3 LVDS High
C 3.3 CMOS High
D3.3CML High
E 2.5 LVPECL High
F 2.5 LVDS High
G 2.5 CMOS High
H2.5CML High
J 1.8 CMOS High
K1.8CML High
M3.3LVPECL Low
N3.3LVDS Low
P3.3CMOS Low
Q3.3CML Low
R2.5LVPECL Low
S2.5LVDS Low
T2.5CMOS Low
U2.5CML Low
V1.8CMOS Low
W1.8CML Low
Note:
CMOS available to 160 MHz.
2nd Op tio n Code
Temperature Tuning Slope Minimum APR
Stability Kv (±ppm) for VD D @
Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V
A 100 180 100 75 25
B 100 90 30 Note 6 Note 6
C 50 180 150 125 75
D50 90 803025
E 20 45 25 Note 6 Note 6
F50 135 1007550
G 20 356 375 300 235
H 20 180 185 145 105
J 20 135 130 104 70
K 100 356 295 220 155
M 20 33 12 Note 6 No te 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO w ith an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning sl ope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x VDD x tuning slope – stability – 10 ppm
5. Mi nimum APR values noted above include worst case values for all pa ramet ers.
6. Combination not available.
Example Part Number: 550AF622M080DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply,
LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part
is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
Frequency (e.g . 622M080 is 622.080 MH z)
Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to
1417 MHz. The position of “M” shifts to denote higher or lower
frequencies. If the frequency of interest requires greater than 6 digit
resolution, a six digit code will be assigned for the specific frequency.
Si550
Rev. 1.1 11
4. Package Outline and Suggested Pad Layout
Figure 2 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si550 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
c 0.50 0.60 0.70
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC.
E 7.00 BSC.
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
p 1.80 — 2.60
R 0.70 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.50
Si550
12 Rev. 1.1
5. 6-Pin PCB Land Pattern
Figure 3 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 3. Si550 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
e 2.54 BSC
E2 4.15 REF
GD 0.84 —
GE 2.00 —
VD 8.20 REF
VE 7.30 REF
X1.70 TYP
Y2.15 REF
ZD — 6.78
ZE — 6.30
Notes:
1. Dimensioning and tolerancing per th e ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millime ters (mm).
Si550
Rev. 1.1 13
6. Top Marking
6.1. Si550 Top Marking
6.2. Top Marking Explanation
Line Position Description
1 1–10 “SiLabs”+ Part Family Number, 550 (First 3 characters in part number)
2 1–10 Si550: Option1+Option2+Freq(6007)+Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (D)
Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Position 10 “+” to indicate Pb-Free and RoHS-compliant
Si550
14 Rev. 1.1
DOCUMENT CHANGE LIST
Revision 0.6 to Revision 1.0
Updated Table 4 on page 3.
Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications.
Updated Table 5 on page 4.
Removed the words “Differential Modes:
LVPECL/LVDS/CML” in the footnote referring to AN256.
Added footnotes clarifying max offset frequency test
conditions.
Added CMOS phase jitter specs.
Updated Table 10 on page 8.
Separated 1.8 V, 2.5 V/3.3 V supply voltage
specifications.
Updated and clarified Table 8 on page 7
Added “Moisture Sensitivity Level” and “Contact Pads”
rows.
Updated 6. "Top Marking" on page 13 to reflect
specific marking information (previously, figure was
generic).
Updated 4. "Packag e Ou tlin e an d Suggested Pad
Layout" on page 11.
Added cyrstal impedance pin in Figure 2 on page 1 1 and
Table 12 on page 11.
Reordered spec tables and back matter to conform
to data sheet quality conventions.
Revision 1.0 to Revision 1.1
Added Table 9, “Thermal Characteristics,” on
page 7.
Si550
Rev. 1.1 15
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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