Features * Hardware - ATSTK94 Onboard Features Programmable Switches, LEDs and Alphanumeric Displays Two RS232 Compatible Serial Ports Multiple Clocks (4 MHz, 18.432 MHz, 32.768 kHz and Manual) 2-wire Serial Interface for Communication Easy Access to all FPSLIC Pins via Headers Push Button AVR and FPSLIC Reset - Supports both Drop-In and In-System Programming (ISP) - Runs Off Portable 9V DC Power Supply - Designed to Work with Atmel System DesignerTM 1.0 or Above * Software - Atmel's System Designer Atmel's AVR Studio(R) Atmel's Configurator Programming System (CPS) Co-verification, Powered by Mentor Graphics Exemplar's LeonardoSpectrumTM Model TechnologyTM's ModelSim(R) Several C Compiler Evaluation Copies - Atmel's Integrated Development System (IDS) - FPGA Place & Route Tool - Supports Windows(R) 95/98/2000/Me and WindowsNT(R) - Online Help * Contents - ATSTK94 Starter Kit Board with 1 Configurator - ATDH2225 Programming Dongle with 10-pin Ribbon Cable - 9V DC, 200 mA, 2.1 mm Center Positive Power Supply - Atmel System Designer CD with Evaluation License (4 Months) - Detailed User Guide including Complete Board Schematics - Software Tutorial and Sample Designs on Floppy Disk Starter Kit Programmable SLI ATSTK94 Description Atmel's AT94K Starter Kit (ATSTK94) allows designers to, quickly and economically, evaluate Atmel's family of AT94K Field Programmable System Level Integrated Circuit (FPSLIC) devices and AT17 FPSLIC Configuration Memory devices. The ATSTK94, see Figure 1, board connects to any x86 PC via the parallel port through a 10-pin header cable to program the AT17 FPSLIC Configuration EEPROM, which in turn programs the AT94K FPSLIC device. A truly portable solution, which allows engineers to prototype and develop designs from their lab bench or office. Rev. 2309B-FPSLI-01/02 1 Figure 1. ATSTK94 FPSLIC Starter Kit Board Switches Jumpers LEDs UART0 UART1 Power Socket Programming Switch Configurator Header Power LED Alphanumeric Displays 2 Configurator Socket Power Switch Reset Switch ATSTK94 2309B-FPSLI-01/02 ATSTK94 Switches, LEDs, and Alphanumeric Displays The user configures each Programmable Switch or LED for use, with either the FPGA or AVR portion of the FPSLIC device. Furthermore, some switches may be configured for use as AVR External Interrupts allowing simulation of external events. The board features four Alphanumeric Displays which are connected to I/O pins of the embedded AT40KAL FPGA core. Program and Run Switch The Program and Run Switch controls the connection from the download cable to the Configurator and the Configurator to the FPSLIC. In the PROG position you can use the download cable and CPS to program the configuration memory with your FPSLIC Bitstream file generated by System Designer. In the Run position the FPSLIC device will load the Bitstream file and run your design. If the design does not start, you can use the RESET button with JP19 in the RESET position to force a reconfiguration of the device. In the Run position, the configurator will boot the FPSLIC device with the current program. ISP and Reset Connections There are 2 device reset connections in the FPSLIC device. The AVR RESET will reset the AVR and start from the reset vector in the interrupt table. RESET will cause the whole device to reset and reboot from the Configurator. SW12 is used to perform the reset. Jumper 19 is used to determine whether it will be an AVR reset or a full device reset, see Table 1. If you have logic RESET signal in your design, you cannot use SW12 to perform this reset; you should use one of the switches SW 1 - 8 to perform your design reset. Your design reset can be connected to any User IO on the FPGA side of FPSLIC. If you are using SW1 - 8, then you should use Pin locks to assign the correct user IO for the correct Switch. Table 1. Reset Connections Button/Switch Connections RESET Source Pin Hardware Settings RESET SW12 108 JP19 Set to RESET (Default) AVR RESET SW12 48 JP19 Set to AVR RESET The jumpers, located next to the buttons/switches control the button/switch connections, see Table 2. The left side of the jumpers are connected to LEDs, the right side of the jumpers are connected to Switches. The A and F markings indicate a connection to the AVR or the FPGA. When you press the switch it generates a "1". 3 2309B-FPSLI-01/02 Table 2. Switch Connections LED Connections Switch Destination Pin Hardware Settings SW1 FPGA User IO 202 Jumper Set to F SW2 FPGA User IO 198 Jumper Set to F SW3 FPGA User IO 192 Jumper Set to F SW4 FPGA User IO 188 Jumper Set to F SW5 FPGA User IO 180 Jumper Set to F SW6 FPGA User IO 176 Jumper Set to F SW7 FPGA User IO 172 Jumper Set to F SW8 FPGA User IO 168 Jumper Set to F SW1 AVR Interrupt INTP0 135 Jumper Set to A SW2 AVR Interrupt INTP1 145 Jumper Set to A SW3 AVR Interrupt INTP2 146 Jumper Set to A SW4 AVR Interrupt INTP3 152 Jumper Set to A SW5 AVR PortE PE0 109 Jumper Set to A SW6 AVR PortE PE1 110 Jumper Set to A SW7 AVR PortE PE2 113 Jumper Set to A SW8 AVR PortE PE3 122 Jumper Set to A The jumpers, located next to the LEDs, control the LED connections. Alternate jumpers connect to the switches, see Table 3, and to the LEDs. A white line on the silk screen indicates whether the jumper is for LED or the Switch. With the A F text the right way up the left most Jumper is for the LED 1. The A and F markings indicate a connection to the AVR or the FPGA. When you drive a "1" to the LED it will light. Table 3. LED Connections 4 LED Source Pin Hardware Settings L1 FPGA User IO 200 Jumper Set to F L2 FPGA User IO 196 Jumper Set to F L3 FPGA User IO 190 Jumper Set to F L4 FPGA User IO 186 Jumper Set to F L5 FPGA User IO 178 Jumper Set to F L6 FPGA User IO 174 Jumper Set to F L7 FPGA User IO 170 Jumper Set to F L8 FPGA User IO 166 Jumper Set to F L1 AVR PortD PD0 111 Jumper Set to A L2 AVR PortD PD1 112 Jumper Set to A L3 AVR PortD PD2 114 Jumper Set to A ATSTK94 2309B-FPSLI-01/02 ATSTK94 Table 3. LED Connections Alphanumeric Connections LED Source Pin Hardware Settings L4 AVR PortD PD3 120 Jumper Set to A L5 AVR PortD PD4 121 Jumper Set to A L6 AVR PortD PD5 126 Jumper Set to A L7 AVR PortD PD6 127 Jumper Set to A L8 AVR PortD PD7 134 Jumper Set to A There are 4 digits of Alphanumeric on the board. The connections to the Alphanumeric are shared between both bits on the same device, see Table 4. This means that Bit 0 and Bit 1 share connections, and Bit 2 and Bit 3 share connections for all the segments, see Figure 2. The difference in connection is in the cathode connection that selects between the 2 digits. The cathodes should be driven with a 1/10 Duty Cycle and a 0.1 ms Pulse Width, see Table 5. Table 4. Alphanumeric Connections LED 0 Source Pin LED 1 Source Pin Anode A FPGA User IO 94 Anode A FPGA User IO 73 Anode B FPGA User IO 98 Anode B FPGA User IO 80 Anode C FPGA User IO 97 Anode C FPGA User IO 76 Anode D FPGA User IO 93 Anode D FPGA User IO 72 Anode E FPGA User IO 81 Anode E FPGA User IO 59 Anode F FPGA User IO 82 Anode F FPGA User IO 60 Anode G FPGA User IO 87 Anode G FPGA User IO 66 Anode H FPGA User IO 89 Anode H FPGA User IO 69 Anode J FPGA User IO 91 Anode J FPGA User IO 70 Anode K FPGA User IO 88 Anode K FPGA User IO 68 Anode L FPGA User IO 86 Anode L FPGA User IO 65 Anode M FPGA User IO 83 Anode M FPGA User IO 61 Anode N FPGA User IO 92 Anode N FPGA User IO 71 Anode P FPGA User IO 84 Anode P FPGA User IO 63 Anode D.P. FPGA User IO 95 Anode D.P. FPGA User IO 74 Cathode Bit 1 FPGA User IO 85 Cathode Bit 1 FPGA User IO 64 Cathode Bit 2 FPGA User IO 96 Cathode Bit 2 FPGA User IO 75 5 2309B-FPSLI-01/02 Figure 2. LEDs LED 0 LED 1 Bit 3 Bit 2 Bit 2 Bit 0 Table 5. ASCII Code Table 6 Value DP P N M L K J H G F E D C B A 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 2 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 3 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 4 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 5 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 6 0 0 1 0 0 0 1 0 0 1 1 1 1 0 1 7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 8 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 9 0 0 1 0 0 0 1 0 0 1 0 1 1 1 1 a 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 b 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 c 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 d 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0 e 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 f 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 . 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 ATSTK94 2309B-FPSLI-01/02 ATSTK94 RS232-compatible UARTs The RS232-compatible UARTs allow for communication between the two on-board UARTs through the null-modem cable. It is also possible for communication between the UARTs and other devices, such as your PC, by using a simple terminal program. UART Connections The 2 UART connections, see Table 6, are made to DB9 connectors. Printf commands are sent out on UART 0. Table 6. UART Connections UART Multiple Clocks Source /Destination Pin Hardware Settings UART 0 RX0 140 Connect Cable to UART0 UART 0 TX0 141 Connect Cable to UART 0 UART1 RX1 149 Connect Cable to UART 1 UART1 TX1 150 Connect Cable to UART 1 There are multiple clock circuits on the Starter Kit. A Manual Clock or the 4 MHz Oscillator are connected to 2 of the FPGA Global Clock pins. The 32,768 KHz (for the implementation of the Real Time Clock calculations), 4 MHz, or 18.432 MHz can be used to drive the AVR. The FPGA has 8 Global Clocks, 2 of these (GCLK5 and GCLK6) can also be driven from the AVR system Clock. GCLK6 can alternatively be driven from the Watchdog timer or one of the timer counters. For full details on the Clock circuits in the FPSLIC device please refer to the AT94K datasheet available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc1138.pdf. Table 7. Clock Connections Frequency Destination Pin Hardware Settings Manual Clock FPGA GCLK7 162 Use MAN CLK Switch (SW9) to Pulse Clock Available Global Clocks FPGA FPGA FPGA FPGA FPGA FPGA 4 47 57 100 162 204 32,768 KHz Crystal AVR TOSC 1 147 None 4 MHz Oscillator AVR System Clock 138 For Rev2 - JP17 towards side of board, JP18 is unconnected. For Rev3 and beyond -Position of JP17 is changed, it is aligned with FPGA and AVR jumpers. JP17 is connected towards the inner side of the board, JP18 is unconnected. 18.432 MHz Crystal AVR System Clock 138 For Rev2 - JP17 towards middle of board, JP18 connected. For Rev3 and beyond - Position of JP17 is changed, it is aligned with FPGA and AVR jumpers. JP17 is connected towards the edge of the board, JP18 is connected. GCLK1 GCLK2 GCLK3 GCLK4 GCLK7 GCLK8 7 2309B-FPSLI-01/02 2-wire Serial Interface The 2-wire Serial Interface is the protocol from which the FPSLIC device receives configuration data from the AT17LV010 Configuration Memory. The maximum size of an AT94K40 design is approximately 800 kbits, thus leaving approximately 200 kbits of unused space. By using the 2-wire Serial Interface, it is possible to use the unused 200 kbits as external data storage memory. Related Documents * ATSTK94 Starter Kit User Guide (Supplied with ATSTK94) * AT94K Series datasheet, available at http://www.atmel.com/atmel/acrobat/doc1138.pdf. * AT94K Series Configuration application note, available at http://www.atmel.com/atmel/acrobat/doc2313.pdf. * AT17LV010 datasheet, available at http://www.atmel.com/atmel/acrobat/doc0944.pdf. * Programming Specification for Atmel's Configuration EEPROMs, available at http://www.atmel.com/atmel/acrobat/doc0437.pdf. * Additional application notes found on the Atmel web site, at http://www.atmel.com/atmel/products/prod183.htm. 8 ATSTK94 2309B-FPSLI-01/02 3 2 1 VCC U11 1 D 8 N/C GND VCC OUT 4 D 5 Board Schematics 4 Clock Circuits 2309B-FPSLI-01/02 5 GCK4_100 4 MHz Osc SOCKETED DIP8 C Label OSC and XTAL 2 TOSC1_147 1 XTAL1_138 3 JP17 3JUMPER C23 27 pF Y1 C16 27 pF 18.432 MHz R21 10M C Y2 32,768 Hz JP18 XTAL2_139 1 2 C17 33 pF JUMPER R22 TOSC2_148 VCC C24 33 pF 200K B B R23 330 ohm SW9 GCK7_162 C18 10 nF R3 1K A A ATMEL CORPORATION Title: Clock Circuits Document Number: CHW5454 Date: Wednesday, June 27, 2001 5 4 3 2 Rev: 4 Sheet 1 of 8 1 9 ATSTK94 Size: A 4 3 2 1 D D U9 1 2 3 4 5 6 7 8 9 E_59 M_61 L_65 K_68 J_70 D_72 DP_74 C_76 +E +M nc +L +K +J +D +DP +C +F +P -1 +G +H +N +A -2 +B 18 17 16 15 14 13 12 11 10 F_60 P_63 1_64 G_66 H_69 N_71 A_73 2_75 B_80 18 17 16 15 14 13 12 11 10 F_82 P_84 1_85 G_87 H_89 N_92 A_94 2_96 B_98 LPT3784G01 U10 C 1 2 3 4 5 6 7 8 9 E_81 M_83 L_86 K_88 J_91 D_93 DP_95 C_97 +E +M nc +L +K +J +D +DP +C +F +P -1 +G +H +N +A -2 +B C LPT3784G01 Green Display Modules B B A A ATMEL CORPORATION Title: Alphanumeric Display Circuits 2309B-FPSLI-01/02 Size: A 5 4 3 Document Number: CHW5454 Date: Wednesday, June 27, 2001 2 Rev: 4 Sheet 2 of 8 1 Alphanumeric Display Circuits 10 ATSTK94 5 4 3 2 1 CON52 D 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PIN61 PIN60 PIN59 PIN58 PIN57 PIN56 PIN55 PIN54 PIN53 PIN52 PIN51 PIN50 PIN49 PIN48 PIN47 PIN46 PIN45 PIN44 PIN43 PIN42 PIN41 PIN40 PIN39 PIN38 PIN37 PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29 PIN28 PIN27 PIN26 PIN25 PIN24 PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PIN15 PIN14 PIN13 PIN12 PIN11 PIN10 D CCLK_153 INTP3_152 D0_151 TX1_150 RX1_149 TOSC2_148 TOSC1_147 INTP2_146 INTP1_145 TX0_141 RX0_140 XTAL2_139 XTAL1_138 INTP0_135 SW5_180 LED5_178 SW6_176 LED6_174 SW7_172 LED7_170 SW8_168 LED8_166 GCK7_162 GND VCC GND GND GCK8 SW1_202 LED1_200 SW2_198 LED2_196 SW3_192 LED3_190 SW4_188 LED4_186 GND VCC C1 Add labels to connectors every 10 pins. Labels should match chip pin numbers up to 208. B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND GCK1 GND FCK1 GND VCC FCK2 GND OTS GCK2 M0_50 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 NC GND NC GCK1(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND FCK1(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O FCK2(I/O) GND I/O I/O I/O I/O I/O I/O I/O I/O OTS(I/O) GCK2(I/O) AVRRESET GND M0 NC NC NC NC VCC CCLK INTP3 D0 TX1 RX1 TOSC2 TOSC1 INTP2 INTP1 NC NC GND TX0 RX0 XTAL2 XTAL1 NC NC INTP0 PD7 PE7 PE6 GND VCC PE5 PE4 PD6 PD5 SCL SDA CS0 PE3 PD4 PD3 NC NC NC NC NC PD2 PE2 PD1 PD0 PE1 PE0 RESET NC VCC NC AT94K40-25DQC 156 155 VCC 154 153 152 151 150 149 148 147 146 145 144 143 GND 142 141 140 139 138 137 136 135 134 PE7 133 PE6 132 GND 131 VCC 130 PE5 129 PE4 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 VCC 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 0.1 uF CON52 CON52 0.1 uF VCC NC NC NC VCC GCK8(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O CS1(I/O) I/O I/O GCK7(I/O) I/O GND I/O NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 C2 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 0.1 uF GCK4 VCC GND PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33 PIN34 PIN35 PIN36 PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52 PIN53 PIN54 PIN55 PIN56 PIN57 PIN58 PIN59 PIN60 PIN61 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 GND M2_56 E_81 F_82 M_83 P_84 1_85 L_86 G_87 K_88 H_89 J_91 N_92 D_93 A_94 DP_95 2_96 C_97 B_98 CON_103 GCK4_100 GCK3 HDC B RESET_108 PE0_109 PE1_110 PD0_111 PD1_112 PE2_113 PD2_114 PD3_120 PD4_121 PE3_122 SDA_124 SCL_125 PD5_126 PD6_127 PD7_134 PE7_133 VCC E_59 F_60 M_61 P_63 1_64 L_65 G_66 K_68 H_69 J_70 N_71 D_72 A_73 DP_74 2_75 C_76 INIT_77 B_80 C C4 VCC AVRRESET_48 PIN61 PIN60 PIN59 PIN58 PIN57 PIN56 PIN55 PIN54 PIN53 PIN52 PIN51 PIN50 PIN49 PIN48 PIN47 PIN46 PIN45 PIN44 PIN43 PIN42 PIN41 PIN40 PIN39 PIN38 PIN37 PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29 PIN28 PIN27 PIN26 PIN25 PIN24 PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PIN15 PIN14 PIN13 PIN12 PIN11 PIN10 VCC C PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33 PIN34 PIN35 PIN36 PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52 uF U1 NC NC VCC M2 GCK3(I/O) HDC(I/O) I/O I/O I/O LDC(I/O) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT)I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GCK4(I/O) GND NC CON NC 0.1 FPSLIC Connections 2309B-FPSLI-01/02 5 52 Pin Connectors are double rows of Probe pins, 26 x 2 on each side of the chip. A A ATMEL CORPORATION CON52 Size: C Document Number: CHW5454 Date: Wednesday, June 27, 2001 5 4 3 2 Rev: 4 Sheet 3 of 8 1 11 ATSTK94 Title: FPSLIC Connections A B C D 150 R7 VCC R11 4.7K 4 AT17C010_2J SOCKET PLCC20 SER_ENPE7 VCC CEO/A2 CLK WP1 DATA WP2 CE RESET/OE GND READY U12 20 4 2 8 6 15 3 VCC 1N4001 D3 R6 2K7 VCC 2 4 6 7 9 10 2 4 6 8 10 HDR2X5 U5_ISP 1 3 5 7 9 2 4 6 8 10 Document Number: CHW5454 Sheet 4 of 8 ATMEL CORPORATION Date: Wednesday, June 27, 2001 2 Size: A 1 3 5 7 9 10-pin header from ATDH2200 J1 1 VCC 1 Need a 3-channel switch, single item. Close to program Configurator. Clock and Data need to be isolated to allow programming without removinng the cable. SER_EN pulled low to program. Title: ISP and Reset Circuits SW 4PDT 2 5 8 11 CCLK_153 D0_151 CON_103 INIT_77 SCL_125 SDA_124 12 SW10 1 RESET_108 DEVICE 10 17 14 5 7 R5 2K7 VCC 3 5 2 AVR AVRRESET_48 JP19 Label as shown if possible R20 2.7k JP20 3 Label RESET 0.1 uF C19 VCC JP21 JP22 JP23 PE7_133 R4 2K7 VCC 4 SW12 VCC 1 3 2 12 1 5 Rev: 4 A B C D ISP and Reset Circuits ATSTK94 2309B-FPSLI-01/02 LED Circuits 2309B-FPSLI-01/02 5 4 3 2 1 U6 150R Code 151 GREEN LED same style as Starter Kit LEDs 9 8 7 6 5 4 3 2 1 R8 R7 R6 R5 R4 R3 R2 R1 COM 8 RESNET LED1_200 1 JP1 L1 D D LED 3 2 PD0_111 LED2_196 L2 1 JP2 3 2 LED For Silk screen do not label too many jumpers. Indicate function of jumper by connecting line as shown. PD1_112 LED3_190 1 JP3 L3 2 LED LED0 3 C swjmp0 ledjmp0 cap sw0 C PD2_114 LED4_186 1 JP4 L4 3 2 LED PD3_120 LED5_178 L5 1 JP5 3 2 LED PD4_121 B 1 L6 B LED6_174 JP6 3 2 LED PD5_126 LED7_170 L7 1 JP7 3 2 LED PD6_127 LED8_166 A L8 2 PD7_134 Size: A Document Number: CHW5454 4 3 2 Rev: 4 Sheet 5 of 8 1 13 ATSTK94 Date: Wednesday, June 27, 2001 5 A Title: LED Circuits 3 LED ATMEL CORPORATION 1 JP8 Power Circuits 14 4 3 2 1 D D Power Socket as on Motherboard SW14 1 P3 C SPDT + - 2 LM317T1 D4 3 3 IN 1N4001 C22 100 uF OUT 3.3V C 2 R8 2.2K C21 0.1uF R9 330 C20 + 1 uF - 1 DCPOWER9V 500 mA VCC Swicth as on Motherboard On Off ADJ ATSTK94 5 R10 3.3K L10 LED B B Red LED for Power A A ATMEL CORPORATION Title: Power Circuits 2309B-FPSLI-01/02 Size: A Document Number: CHW5454 Date: Wednesday, June 27, 2001 5 4 3 2 Rev: 4 Sheet 6\ of 8 1 4 3 2 RS232 Circuits 2309B-FPSLI-01/02 5 1 D D VCC VCC VCC R1 2K7 C13 0.33 uF R2 2K7 P1 5 9 4 8 3 7 2 6 1 C14 0.68 uF D1 U8 1N6050 1 2 3 4 5 6 7 8 9 10 11 12 L9 15 uH C RX0_140 RX1_149 D2 TX0_141 TX1_150 1N6050 C15 0.33 uF LN GND LP V+ VCC R1IN SD R2IN EN R3IN R1OUT R4IN R2OUT R5IN R3OUT T1OUT R4OUT T2OUT R5OUT T3OUT T1IN VT2IN T3IN 24 23 22 21 20 19 18 17 16 15 14 13 UART0 CONNECTOR DB9 C P2 5 9 4 8 3 7 2 6 1 MAX212CWG UART1 CONNECTOR DB9 B B TP5 VCC TP6 VCC 1 TEST POINT TP3 GND 1 1 TEST POINT TP2 GND 1 TP8 VCC 1 TEST POINT TP1 GND VCC 1 TEST POINT TP7 TP4 GND 1 1 A TEST POINT TEST POINT TEST POINT A ATMEL CORPORATION TEST POINT Size: A 5 4 3 Document Number: CHW5454 Date: Wednesday, June 27, 2001 2 Rev: 4 Sheet 7 of 8 1 15 ATSTK94 Title: RS232 Circuits A B C D 5 R6 R8 R7 U7 330R VCC R5 R4 R3 R2 R1 COM 5 9 8 7 6 5 4 3 2 1 SW8 SW7 SW6 SW5 SW4 SW3 SW2 4 Switches similar to FPGA Starter Kit SW1 4 C12 10 nF C11 10 nF C10 10 nF C9 10 nF C8 10nF C7 10 nF C6 10 nF C5 10 nF R19 1k R18 1k R17 1k R16 1k R15 1k R14 1k R13 1k R12 1k 3 2 2 2 2 2 2 2 2 3 JP16 JP15 JP14 JP13 JP12 JP11 JP10 JP9 Jumpers similar to FPGA Starter Kit Clock Jumpers 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 16 8 RESNET PE3_122 SW8_168 PE2_113 SW7_172 PE1_110 SW6_176 PE0_109 SW5_180 INTP3_152 SW4_188 INTP2_146 SW3_192 INTP1_145 SW2_198 INTP0_135 SW1_202 swjmp0 ledjmp0 cap 2 Sheet 8 of 8 ATMEL CORPORATION Document Number: CHW5454 sw0 Date: Wednesday, June 27, 2001 Siz e: A Tit le: Switch Circuits LED0 For Silk screen do not label too many jumpers for LED and Switches. Indicate function of jumper by connecting line as shown. 2 1 1 Rev: 4 A B C D Switch Circuits ATSTK94 2309B-FPSLI-01/02 ATSTK94 Device Pinout and Board Connection Summary Table 8 shows the pin number for the FPSLIC device, the corresponding function of the FPSLIC pin and then the function as it is laid out on the Starter Kit. Any pin that does not have a board Function assigned may be used as a wire wrap or probe connection into the FPSLIC device. All probe pins on the board are connected to the corresponding IO of the chip. Pins that connect to the Switches or LEDs may also be used as user-specific inputs or outputs simply by leaving the corresponding Jumper disconnected. Table 8. Pinout and Board Connection Pin FPSLIC IO Type Board Function 1 No Connect 2 GND 3 No Connect 4 GCK1(IO) 5 IO 6 IO 7 IO 8 IO 9 IO 10 IO 11 IO 12 IO 13 IO 14 GND 15 FCK1(IO) 16 IO 17 IO 18 IO 19 IO 20 IO 21 IO 22 IO 23 IO 24 IO 25 GND GND 26 VCC VCC 27 IO 28 IO 29 IO Hardware GND GND 17 2309B-FPSLI-01/02 Table 8. Pinout and Board Connection 18 Pin FPSLIC IO Type Board Function Hardware 30 IO 31 IO 32 IO 33 IO 34 IO 35 IO 36 FCK2(IO) 37 GND 38 IO 39 IO 40 IO 41 IO 42 IO 43 IO 44 IO 45 IO 46 OTS(IO) 47 GCK2(IO) 48 AVRRESET AVR RESET 49 GND GND 50 M0 GND 51 No Connect 52 No Connect 53 No Connect 54 No Connect 55 VCC 56 M2 57 GCK3(IO) 58 HDC(IO) 59 IO ALPHANUMERIC 1 E LED1 E 60 IO ALPHANUMERIC 1 F LED1 F 61 IO ALPHANUMERIC 1 M LED1 M 62 LDC(IO) 63 IO ALPHANUMERIC 1 P LED1 P 64 IO ALPHANUMERIC 1 Cathode 1 LED1 Cathode 1 GND JP19, SW12 GND ATSTK94 2309B-FPSLI-01/02 ATSTK94 Table 8. Pinout and Board Connection Pin FPSLIC IO Type Board Function Hardware 65 IO ALPHANUMERIC 1 L LED1 L 66 IO ALPHANUMERIC 1 G LED1 G 67 GND GND 68 IO ALPHANUMERIC 1 K LED1 K 69 IO ALPHANUMERIC 1 H LED1 H 70 IO ALPHANUMERIC 1 J LED1 J 71 IO ALPHANUMERIC 1 N LED1 N 72 IO ALPHANUMERIC 1 D LED1 D 73 IO ALPHANUMERIC 1 A LED1 A 74 IO ALPHANUMERIC 1 DP LED1 DP 75 IO ALPHANUMERIC 1 Cathode 2 LED1 Cathode 2 76 IO ALPHANUMERIC 1 C LED1 C 77 INIT(IO) INIT AT17 RESET/OE 78 VCC VCC 79 GND GND 80 IO ALPHANUMERIC 1 B LED1 B 81 IO ALPHANUMERIC 0 E LED0 E 82 IO ALPHANUMERIC 0 F LED0 F 83 IO ALPHANUMERIC 0 M LED0 M 84 IO ALPHANUMERIC 0 P LED0 P 85 IO ALPHANUMERIC 0 Cathode 1 LED0 Cathode 1 86 IO ALPHANUMERIC 0 L LED0 L 87 IO ALPHANUMERIC 0 G LED0 G 88 IO ALPHANUMERIC 0 K LED0 K 89 IO ALPHANUMERIC 0 H LED0 H 90 GND GND 91 IO ALPHANUMERIC 0 J LED0 J 92 IO ALPHANUMERIC 0 N LED0 N 93 IO ALPHANUMERIC 0 D LED0 D 94 IO ALPHANUMERIC 0 A LED0 A 95 IO ALPHANUMERIC 0 DP LED0 DP 96 IO ALPHANUMERIC 0 Cathode 2 LED0 Cathode 2 97 IO ALPHANUMERIC 0 C LED0 C 98 IO ALPHANUMERIC 0 B LED0 B 19 2309B-FPSLI-01/02 Table 8. Pinout and Board Connection 20 Pin FPSLIC IO Type Board Function Hardware 99 IO 100 GCK4 (IO) GCK4 - 4 MHz Clock 4 MHz Oscillator 101 GND GND 102 No Connect 103 CON 104 No Connect 105 No Connect 106 VCC 107 No Connect 108 RESET FPSLIC Device RESET JP19, SW12 109 PE0 PortE 0 JP13 A 110 PE1 PortE 1 JP14 A 111 PD0 PortD 0 JP1 A 112 PD1 PortD 1 JP2 A 113 PE2 PortE 2 JP15 A 114 PD2 PortD 2 JP3 A 115 No Connect 116 No Connect 117 No Connect 118 No Connect 119 No Connect 120 PD3 PortD 3 JP4 A 121 PD4 PortD 4 JP5 A 122 PE3 PortE 3 JP16 A 123 CS0 124 SDA 2 Wire Serial Data AT17 Data 125 SCL 2 Wire Serial Clock AT17 Clock 126 PD5 PortD 5 JP6 A 127 PD6 PortD 6 JP7 A 128 PE4 PortE 4 129 PE5 PortE 5 130 VCC VCC 131 GND GND 132 PE6 PortE 6 133 PE7 PortE 7 134 PD7 PortD 7 Configuration Control AT17 /CE VCC JP8 A ATSTK94 2309B-FPSLI-01/02 ATSTK94 Table 8. Pinout and Board Connection Pin FPSLIC IO Type Board Function Hardware 135 INTP0 External Interrupt 0 JP9 A 136 No Connect 137 No Connect 138 XTAL1 AVR System Clock Input JP17, Y1 139 XTAL2 AVR System Clock Pair JP18, Y1 140 RX0 UART 0 Receive UART 0 pin3 141 TX0 UART 0 Transmit UART 0 pin 2 142 GND GND 143 No Connect 144 No Connect 145 INTP1 External Interrupt 1 JP10 A 146 INTP2 External Interrupt 2 JP11 A 147 TOSC1 Oscillator Input Y2 148 TOSC2 Oscillator Pair Y2 149 RX1 UART 1 Receive UART 1 pin 2 150 TX1 UART 1 Transmit UART 1 pin 3 151 D0 Configuration Data Input AT17 Data 152 INTP3 External Interrupt 3 JP12 A 153 CCLK Configuration Clock AT17 Clock 154 VCC 155 No Connect 156 No Connect 157 No Connect 158 No Connect 159 IO 160 GND 161 IO0 162 GCK7(IO) GCK7 Manual Clock MAN CLK (SW) 163 IO 164 IO 165 IO 166 IO LED 8 JP8 F 167 IO 168 IO Switch 8 JP16 F 169 IO 21 2309B-FPSLI-01/02 Table 8. Pinout and Board Connection 22 Pin FPSLIC IO Type Board Function Hardware 170 IO LED 7 JP7 F 171 GND 172 IO Switch 7 JP15 F 173 IO 174 IO LED 6 JP6 F 175 IO 176 IO Switch 6 JP14 F 177 IO 178 IO LED 5 JP5 F 179 IO 180 IO Switch 5 JP13 F 181 IO 182 GND 183 VCC 184 IO 185 IO 186 IO LED 4 JP4 F 187 IO 188 IO Switch 4 JP12 F 189 IO 190 IO LED 3 JP3 F 191 IO 192 IO Switch 3 JP11 F 193 IO 194 GND 195 IO 196 IO LED 2 JP2 F 197 IO 198 IO Switch 2 JP10 F 199 IO 200 IO LED 1 JP1 F 201 IO 202 IO Switch 1 JP9 F 203 IO 204 GCK8(IO) 205 VCC ATSTK94 2309B-FPSLI-01/02 ATSTK94 Table 8. Pinout and Board Connection Pin FPSLIC IO Type 206 No Connect 207 No Connect 208 No Connect Board Function Hardware 23 2309B-FPSLI-01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Atmel Programmable SLI Hotline e-mail (408) 436-4119 literature@atmel.com Atmel Programmable SLI e-mail Web Site fpslic@atmel.com http://www.atmel.com FAQ Available on web site (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R), AVR (R) and AVR Studio (R) are the registered trademarks of Atmel; FPSLIC TM and System DesignerTM are the trademarks of Atmel. Windows (R) and WindowsNT (R) are the registered trademarks of Microsoft Corporation; ModelSim (R) is the registered trademark of Mentor Graphics Corporation; LeonardoSpectrum TM and Model TechnologyTM are the trademarks of Mentor Graphics Corporation; Synplify(R) is the registered trademark of Synplicity; FPGA ExpressTM is the trademark of Synopsys. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2309B-FPSLI-01/02 xM