AGR19045EF
45 W, 1930 MHz—1990 MHz, PCS LDMOS RF Power Transistor
Introduction
The AGR19045EF isa 45 W, 28 VN-channel later-
ally diffused metal oxide semiconductor (LDMOS)
RF power field effect transistor (FET) suitable for
personal communication service (PCS) (1930 MHz—
1990 MHz), global system for mobile communication
(GSM/EDGE), time-division multiple access (TDMA),
and single-carrier or multicarrier class AB power
amplifier applications.
Figure 1. AGR19045EF (flanged) Package
Typical two carrier N-CDMA performance: VDD =
28 V, IDQ = 550 mA, f1 = 1958.75 MHz, f2 =
1961.25 MHz, IS-95 CDMA (pilot, sync, paging,
traffic codes 8—13).Peak/average (P/A) = 9.72 dB
at 0.01% probability on CCDF. 1.2288 MHz trans-
mission bandwidth (BW). Adjacent channel power
ratio (ACPR) measured over 30 kHz BW at f1 –
885 kHz and f2 + 885 kHz. Third-order intermodu-
lation distortion (IM3)measured over a
1.2288 MHz BW at f1 – 2.5 MHz and f2 + 2.5 MHz:
— Output power (POUT): 9.5 W.
— Powergain: 15dB.
— Efficiency: 24.8%.
— IM3: –34.5 dBc.
— ACPR: –49.5 dBc.
EDGE Features
Typical EDGE performance,
1990 MHz, 26 V, IDQ = 400 mA:
— Output power (POUT): 18 W typical.
— Powergain: 14.5 dB.
— Efficiency: 35% typical.
— Spectral regrowth:
@ ±400 kHz = –62 dBc.
@ ±600 kHz = –74 dBc.
— Error vector magnitude (EVM)= 2.0%.
GSM Features
Typical performance over entire GSM band:
— P1dB: 50 W typical.
—Power gain @ P1dB = 14.0 dB continuous wave
(CW).
— Efficiency @ P1dB = 54% typical CW.
— Return loss: –10 dB.
Device Performance Features
High-reliability, gold-metalization process.
Low hot carrier injection (HCI)induced bias drift
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
Device can withstand 10:1 voltage standing wave
ratio (VSWR) at 28 Vdc, 1930 MHz, 45 W CW out-
put power.
Large signal impedance parameters available.
ESD Rating*
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly,and test operations. Agere
employsa human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limitsand protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from elec-
trostatic charge. Reasonable precautions in han-
dling and packaging MOS devices should be
observed.
AGR19045EF Minimum (V) Class
HBM 500 1B
MM 50 A
CDM 1500 4