16-Bit, 4-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●PIN FOR PIN WITH ADS7841
●SINGLE SUPPLY: 2.7V to 5V
●4-CHANNEL SINGLE-ENDED OR
2-CHANNEL DIFFERENTIAL INPUT
●UP TO 100kHz CONVERSION RATE
●86dB SINAD
●SERIAL INTERFACE
●SSOP-16 PACKAGE
DESCRIPTION
The ADS8341 is a 4-channel, 16-bit sampling Analog-to-
Digital (A/D) converter with a synchronous serial interface.
Typical power dissipation is 8mW at a 100kHz throughput
rate and a +5V supply. The reference voltage (VREF) can be
varied between 500mV and VCC, providing a corresponding
input voltage range of 0V to VREF. The device includes a
shutdown mode that reduces power dissipation to under
15µW. The ADS8341 is tested down to 2.7V operation.
Low power, high speed, and an onboard multiplexer make
the ADS8341 ideal for battery-operated systems such as
personal digital assistants, portable multi-channel data log-
gers, and measurement equipment. The serial interface also
provides low-cost isolation for remote data acquisition. The
ADS8341 is available in an SSOP-16 package and is en-
sured over the –40°C to +85°C temperature range.
APPLICATIONS
●DATA ACQUISITION
●TEST AND MEASUREMENT
●INDUSTRIAL PROCESS CONTROL
●PERSONAL DIGITAL ASSISTANTS
●BATTERY-POWERED SYSTEMS
CDAC
SAR
Comparator
Four
Channel
Multiplexer
Serial
Interface
and
Control
CH0
CH1
CH2
CH3
COM
VREF
CS
SHDN
DIN
DOUT
BUSY
DCLK
ADS8341
ADS8341
SBAS136D – SEPTEMBER 2000 – APRIL 2003
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS8341
2SBAS136D
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
MAXIMUM NO
INTEGRAL MISSING
LINEARITY CODES SPECIFICATION
ERROR ERROR TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) RANGE PACKAGE DESIGNATOR(1) NUMBER MEDIA
ADS8341E 8 14 –40°C to +85°C SSOP-16 DBQ ADS8341E Rails
" " " " " " ADS8341E/2K5 Tape and Reel
ADS8341EB 6 15 –40°C to +85°C SSOP-16 DBQ ADS8341EB Rails
" " " " " " ADS8341EB/2K5 Tape and Reel
NOTE: (1) For the most current specifications and package information, refer to our web site www.ti.com.
PIN CONFIGURATIONS
Top View SSOP
PACKAGE/ORDERING INFORMATION
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1+V
CC Power Supply, 2.7V to 5V
2 CH0 Analog Input Channel 0
3 CH1 Analog Input Channel 1
4 CH2 Analog Input Channel 2
5 CH3 Analog Input Channel 3
6 COM Ground Reference for Analog Inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground or ground reference
point.
7 SHDN Shutdown. When LOW, the device enters a very low power shutdown mode.
8V
REF Voltage Reference Input. See Electrical Characteristics Table for ranges.
9+V
CC Power Supply, 2.7V to 5V
10 GND Ground. Connect to Analog Ground
11 GND Ground. Connect to Analog Ground.
12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.
13 BUSY Busy Output. This output is high impedance when CS is HIGH.
14 DIN Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.
15 CS Chip Select Input. Controls conversion timing and enables the serial input/output register.
16 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency
equals 2.4MHz to achieve 100kHz sampling rate.
ABSOLUTE MAXIMUM RATINGS(1)
+VCC to GND ........................................................................–0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
1
2
3
4
5
6
7
8
+VCC
CH0
CH1
CH2
CH3
COM
SHDN
VREF
DCLK
CS
DIN
BUSY
DOUT
GND
GND
+VCC
16
15
14
13
12
11
10
9
ADS8341
ADS8341 3
SBAS136D
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8341E, P ADS8341EB, PB
✻ Same specifications as ADS8341E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 76µV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 ✻BITS
ANALOG INPUT
Full-Scale Input Span Positive Input - Negative Input 0 VREF ✻✻V
Absolute Input Range Positive Input –0.2 +VCC +0.2 ✻✻V
Negative Input –0.2 +1.25 ✻✻V
Capacitance 25 ✻pF
Leakage Current ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 14 15 Bits
Integral Linearity Error ±8±6LSB
Offset Error ±2±1mV
Offset Error Match 1.2 4.0 ✻✻LSB(1)
Gain Error ±0.05 ±0.024 %
Gain Error Match 1.0 4.0 ✻✻ LSB
Noise 20 ✻µVrms
Power-Supply Rejection +4.75V < VCC < 5.25V 3 ✻LSB(1)
SAMPLING DYNAMICS
Conversion Time 16 ✻Clk Cycles
Acquisition Time 4.5 ✻Clk Cycles
Throughput Rate 100 ✻kHz
Multiplexer Settling Time 500 ✻ns
Aperture Delay 30 ✻ns
Aperture Jitter 100 ✻ps
Internal Clock Frequency SHDN = VDD 2.4 ✻MHz
External Clock Frequency 0.024 2.4 ✻✻MHz
Data Transfer Only 0 2.4 ✻✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2) VIN = 5Vp-p at 10kHz –90 ✻dB
Signal-to-(Noise + Distortion) VIN = 5Vp-p at 10kHz 86 ✻dB
Spurious-Free Dynamic Range VIN = 5Vp-p at 10kHz 92 ✻dB
Channel-to-Channel Isolation VIN = 5Vp-p at 50kHz 100 ✻dB
REFERENCE INPUT
Range 0.5 +VCC ✻✻V
Resistance DCLK Static 5 ✻GΩ
Input Current 40 100 ✻✻ µA
fSAMPLE = 12.5kHz 2.5 ✻µA
DCLK Static 0.001 3 ✻✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
VIH | IIH | ≤ +5µA 3.0 5.5 ✻✻V
VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V
VOH IOH = –250µA 3.5 ✻V
VOL IOL = 250µA 0.4 ✻V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
+VCC Specified Performance 4.75 5.25 ✻✻V
Quiescent Current 1.5 2.0 ✻mA
fSAMPLE = 12.5kHz 300 ✻µA
Power-Down Mode(3), CS = +VCC 3✻µA
Power Dissipation 7.5 10 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
ADS8341
4SBAS136D
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8341E, P ADS8341EB, PB
✻ Same specifications as ADS8341E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 76µV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 ✻BITS
ANALOG INPUT
Full-Scale Input Span Positive Input - Negative Input 0 VREF ✻✻V
Absolute Input Range Positive Input –0.2 +VCC +0.2 ✻✻V
Negative Input –0.2 +0.2 ✻✻V
Capacitance 25 ✻pF
Leakage Current ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 14 15 Bits
Integral Linearity Error ±12 ±8LSB
Offset Error ±1±0.5 mV
Offset Error Match 1.2 4.0 ✻✻ LSB
Gain Error ±0.05 ±0.0024 % of FSR
Gain Error Match 1.0 4.0 ✻✻ LSB
Noise 20 ✻µVrms
Power-Supply Rejection +2.7 < VCC < +3.3V 3 ✻LSB(1)
SAMPLING DYNAMICS
Conversion Time 16 ✻Clk Cycles
Acquisition Time 4.5 ✻Clk Cycles
Throughput Rate 100 ✻kHz
Multiplexer Settling Time 500 ✻ns
Aperture Delay 30 ✻ns
Aperture Jitter 100 ✻ps
Internal Clock Frequency SHDN = VDD 2.4 ✻MHz
External Clock Frequency 0.024 2.4 ✻✻MHz
When Used with Internal Clock 0.024 2.0 ✻✻MHz
Data Transfer Only 0 2.4 ✻✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2) VIN = 2.5Vp-p at 10kHz –90 ✻dB
Signal-to-(Noise + Distortion) VIN = 2.5Vp-p at 10kHz 86 ✻dB
Spurious-Free Dynamic Range VIN = 2.5Vp-p at 10kHz 92 ✻dB
Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 ✻dB
REFERENCE INPUT
Range 0.5 +VCC ✻✻V
Resistance DCLK Static 5 ✻GΩ
Input Current 13 40 ✻✻ µA
fSAMPLE = 12.5kHz 2.5 ✻µA
DCLK Static 0.001 3 ✻✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
VIH | IIH | ≤ +5µA+V
CC • 0.7 5.5 ✻✻V
VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V
VOH IOH = –250µA+V
CC • 0.8 ✻V
VOL IOL = 250µA 0.4 ✻V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
+VCC Specified Performance 2.7 3.6 ✻✻V
Quiescent Current 1.2 1.85 ✻✻ mA
fSAMPLE = 12.5kHz 220 µA
Power-Down Mode(3), CS = +VCC 3✻µA
Power Dissipation 3.2 5 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
ADS8341 5
SBAS136D
TYPICAL CHARACTERISTICS: +5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
–160
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.001kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140
–160
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 9.985kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SFDR (dB)
100
90
80
70
60
THD (dB)
–100
–90
–80
–70
–60
SFDR
THD(1)
(1) First Nine Harmonics
of the Input Frequency
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101 100
Frequency (kHz)
Effective Number of Bits
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
Temperature (°C)
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
25 100–50 –25 0 50 75
Delta from 25°C (dB)
fIN = 9.985kHz, –0.2dB
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SNR and SINAD (dB)
100
90
80
70
60
SNR
SINAD
ADS8341
6SBAS136D
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
Output Code
3
2
1
0
–1
–2
–3
INTEGRAL LINEARITY ERROR vs CODE
8000h FFFFh0000h 4000h C000h
ILE (LSBS)
Output Code
4
3
2
1
0
–1
–2
DIFFERENTIAL LINEARITY ERROR vs CODE
8000h FFFFh0000h 4000h C000h
DLE (LSBS)
CHANGE IN OFFSET vs TEMPERATURE
20 40 600–20–40 10080
Temperature (°C)
Change in Offset (LSB)
1.0
0.50
0.00
–0.50
–1.00
–1.50
CHANGE IN GAIN vs TEMPERATURE
Change in Gain (LSB)
0.40
0.30
0.20
0.10
0.00
–0.10
–0.20
–0.30 20 40 600–20–40 10080
Temperature (°C)
WORST CASE CHANNEL-TO-CHANNEL
OFFSET MATCH vs TEMPERATURE
Offset Match (LSB)
2.50
2.00
1.50
1.00
0.50
0.00 20 40 600–20–40 10080
Temperature (°C)
Gain Match (LSB)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
WORST CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
20 40 600–20–40 10080
Temperature (°C)
ADS8341 7
SBAS136D
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
I
Q
(mA)
1.45
1.40
1.35
1.20
1.25
I
Q
vs TEMPERATURE
20 40 600–20–40 100
Temperature (°C) 80
ADS8341
8SBAS136D
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
–160
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.001kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140
–160
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SNR and SINAD (dB)
90
85
80
75
70
65
60
SNR
SINAD
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SFDR (dB)
100
90
80
70
60
50
SFDR
THD(1)
(1) First nine harmonics
of the input frequency.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101 100
Frequency (kHz)
Effective Number of Bits
15
14
13
12
11
10
9
8
Temperature (°C)
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
25 100–50 –25 0 50 75
Delta from 25°C (dB)
fIN = 9.985kHz, –0.2dB
ADS8341 9
SBAS136D
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
Output Code
3
2
1
0
–1
–2
–3
INTEGRAL LINEARITY ERROR vs CODE
8000h FFFFh0000h 4000h C000h
ILE (LSBS)
Output Code
4
3
2
1
0
–1
–2
DIFFERENTIAL LINEARITY ERROR vs CODE
8000h FFFFh0000h 4000h C000h
DLE (LSBS)
CHANGE IN OFFSET vs TEMPERATURE
Change in Offset (LSB)
0.30
0.20
0.10
0.00
–0.10
–0.20
–0.30 20 40 600–20–40 100
Temperature (°C) 80
CHANGE IN GAIN vs TEMPERATURE
Change in Gain (LSB)
0.200
0.100
0.000
–0.100
–0.200
–0.300 20 40 600–20–40 100
Temperature (°C) 80
Offset Match (LSB)
0.400
0.300
0.200
0.100
0.000
WORST CASE CHANNEL-TO-CHANNEL
OFFSET MATCH vs TEMPERATURE
20 40 600–20–40 100
Temperature (°C) 80
Gain Match (LSB)
0.200
0.150
0.100
0.050
0.000
WORST CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
20 40 600–20–40 100
Temperature (°C) 80
ADS8341
10 SBAS136D
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
+VSS (V)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
SUPPLY CURRENT vs +VSS
3.5 5.02.5 3.0 4.0 4.5
Supply Current (mA)
fSAMPLE = 100kHz
VREF vs +VSS
I
Q
(mA)
1.15
1.10
1.05
1.00
0.95
I
Q
vs TEMPERATURE
20 40 600–20–40 100
Temperature (°C) 80
ADS8341 11
SBAS136D
THEORY OF OPERATION
The ADS8341 is a classic Successive Approximation Reg-
ister (SAR) A/D converter. The architecture is based on
capacitive redistribution which inherently includes a sample-
and-hold function. The converter is fabricated on a 0.6µm
CMOS process.
The basic operation of the ADS8341 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V.
The external reference can be any voltage between 500mV
and +VCC. The value of the reference voltage directly sets
the input range of the converter. The average reference
input current depends on the conversion rate of the
ADS8341.
The analog input to the converter is differential and is
provided via a four-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using two of the four
input channels (CH0 - CH3). The particular configuration is
selectable via the digital interface.
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS8341. The differential input of the converter is
derived from one of the four inputs in reference to the COM
pin or two of the four inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs, as shown in
Figure 2, is captured on the internal capacitor array. The
voltage on the –IN input is limited between –0.2V and
1.25V, allowing the input to reject small signals that are
common to both the +IN and –IN input. The +IN input has
a range of –0.2V to +VCC + 0.2V. FIGURE 2. Simplified Diagram of the Analog Input.
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN–IN
101–IN +IN
010 +IN–IN
110 –IN +IN
TABLE II. Differential Channel Control (SGL/DIF LOW).
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN –IN
101 +IN –IN
010 +IN –IN
110 +IN–IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conver-
sion rate.
FIGURE 1. Basic Operation of the ADS8341.
Converter
+IN
–IN
CH0
CH1
CH2
CH3
COM
A2-A0
(Shown 001
B
)
SGL/DIF
(Shown HIGH)
+V
CC
CH0
CH1
CH2
CH3
COM
SHDN
V
REF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
DOUT
GND
GND
+V
CC
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
0.1µF1µF
0.1µF
+2.7V to +5V ADS8341
Single-ended
or differential
analog inputs
+
+
1µF
to
10µF
External
V
REF
ADS8341
12 SBAS136D
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8341 will operate with a reference in the range of
500mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input, see
Figure 2. For example, in the single-ended mode, a 1.25V
reference, with the COM pin grounded, the selected input
channel (CH0 - CH3) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference
input and its wide voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(least significant bit) size and is equal to the reference
voltage divided by 65,536. Any offset or gain error inherent
in the A/D converter will appear to increase, in terms of LSB
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In
each case, the actual offset of the device is the same, 76µV.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
500mV, the LSB size is 7.6µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the VREF input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8341. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
Figure 3 shows the typical operation of the ADS8341’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +VCC). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight cycles are used to provide the control byte via
the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer
appropriately, it enters the acquisition (sample) mode. After
three more clock cycles, the control byte is complete and the
converter enters the conversion mode. At this point, the
input sample-and-hold goes into the hold mode. The next 16
clock cycles accomplish the actual analog-to-digital conver-
sion.
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’
bit, must always be HIGH and indicates the start of the
control byte. The ADS8341 will ignore inputs on the DIN
pin until the start bit is detected. The next three bits (A2 -
A0) select the active input channel or channels of the input
multiplexer (see Tables I and II and Figure 2).
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)
S A2A1A0—SGL/DIF PD1 PD0
TABLE III. Order of the Control Bits in the Control Byte.
tACQ
AcquireIdle Conversion
1DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
81 8
AcquireIdle Conversion
181
15
(MSB)
(START)
A2SA1A0
SGL/
DIF
PD1 PD0
14
ADS8341 13
SBAS136D
TABLE IV.Descriptions of the Control Bits within the
Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
DIN.
6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input,
see Tables I and II.
2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input, see Tables I and II.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
PD0 = 1 for external clock mode. After enabling the re-
quired clock mode, only then should the ADS8341 be set to
power-down between conversions (i.e., PD1 = PD0 = 0).
The ADS8341 maintains the clock mode it was in prior to
entering the power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts
data in and out of the ADS8341, it also controls the A/D
conversion steps. BUSY will go HIGH for one clock period
after the last bit of the control byte is shifted in. Successive-
approximation bit decisions are made and appear at DOUT
on each of the next 16 DCLK falling edges (see Figure 3).
Figure 4 shows the BUSY timing in external clock mode.
Since one clock cycle of the serial clock is consumed with
BUSY going high (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits
of data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
shown in Figure 3, where the beginning of the next control
byte appears at the same time the LSB is being clocked out
of the ADS8341. This method allows for maximum through-
put and 24 clock cycles per conversion.
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode, as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be valid.
Clock Modes
The ADS8341 can be used with an external serial clock or
an internal clock to perform the successive-approximation
conversion. In both clock modes, the external clock shifts
data in and out of the device. Internal clock mode is selected
when PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the
other, an extra conversion cycle will be required before the
ADS8341 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8341 prior to the change in clock modes.
When power is first applied to the ADS8341, the user must
set the desired clock mode. It can be set by writing PD1
= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and
PD1 PD0 Description
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
1 0 Selects Internal Clock Mode
0 1 Reserved for Future Use
1 1 No power-down between conversions, device al-
ways powered. Selects external clock mode.
TABLE V. Power-Down Selection.
FIGURE 4. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
15
DOUT
BUSY
DIN
14
ADS8341
14 SBAS136D
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 900 ns
tDS DIN Valid Prior to DCLK Rising 50 ns
tDH DIN Hold After DCLK HIGH 10 ns
tDO DCLK Falling to DOUT Valid 100 ns
tDV CS Falling to DOUT Enabled 70 ns
tTR CS Rising to DOUT Disabled 70 ns
tCSS CS Falling to First DCLK Rising 50 ns
tCSH CS Rising to DCLK Ignored 0 ns
tCH DCLK HIGH 150 ns
tCL DCLK LOW 150 ns
tBD DCLK Falling to BUSY Rising 100 ns
tBDV CS Falling to BUSY Enabled 70 ns
tBTR CS Rising to BUSY Disabled 70 ns
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes high; after the next CS
falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8341 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz.
BUSY goes LOW at the start of conversion and then returns
HIGH when the conversion is complete. During the conver-
sion, BUSY will remain LOW for a maximum of 8µs. Also,
during the conversion, DCLK should remain LOW to achieve
the best noise performance. The conversion result is stored
in an internal register; the data may be clocked out of this
register any time after the conversion is complete.
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the DOUT line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the DOUT line will remain in tri-state until CS goes
LOW, as shown in Figure 6. CS does not need to remain
LOW once a conversion has started. Note that BUSY is not
tri-stated when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8341 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time tACQ, is kept above 1.7µs.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8341.
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0
81 8
Idle
18
Zero Filled...
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
8
9 1011121314151617181920212223242526272829303132
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
FIGURE 5. External Clock Mode 32 Clocks Per Conversion.
FIGURE 6. Internal Clock Mode Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 1.5 µs
tDS DIN Valid Prior to DCLK Rising 100 ns
tDH DIN Hold After DCLK HIGH 10 ns
tDO DCLK Falling to DOUT Valid 200 ns
tDV CS Falling to DOUT Enabled 200 ns
tTR CS Rising to DOUT Disabled 200 ns
tCSS CS Falling to First DCLK Rising 100 ns
tCSH CS Rising to DCLK Ignored 0 ns
tCH DCLK HIGH 200 ns
tCL DCLK LOW 200 ns
tBD DCLK Falling to BUSY Rising 200 ns
tBDV CS Falling to BUSY Enabled 200 ns
tBTR CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
ADS8341 15
SBAS136D
FIGURE 8. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
FIGURE 9. Supply Current versus State of CS.
10k 100k1k 1M
fSAMPLE (Hz)
Supply Current (µA)
100
10
1
1000
fCLK = 2.4MHz
fCLK = 24 • fSAMPLE
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
PD1 = PD0 = 0
10k 100k1k 1M
fSAMPLE (Hz)
Supply Current (µA)
0.00
0.09
14
0
2
4
6
8
10
12
CS LOW
(GND)
CS HIGH (+VCC)
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
fCLK = 24 • fSAMPLE
PD1 = PD0 = 0
FIGURE 7. Ideal Input Voltages and Output Codes.
Data Format
The ADS8341 output data is in straight binary format, as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
Operating the ADS8341 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
Output Code
0V
FS = Full-Scale Voltage = V
REF
1LSB = V
REF
/65,536
FS – 1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTE
(1)
: Voltage at converter input, after
multiplexer: +IN – (–IN). (See Figure 2.)
Input Voltage
(1)
(V)
POWER DISSIPATION
There are three power modes for the ADS8341: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS8341 is being operated.
For example, at full conversion rate and 24-clocks per
conversion, there is very little difference between full power
mode and auto power-down, a shutdown (SHDN LOW) will
not lower power dissipation.
When operating at full-speed and 24-clocks per conversion
(as shown in Figure 3), the ADS8341 spends most of its time
acquiring or converting. There is little time for auto power-
down, assuming that this mode is active. Thus, the differ-
ence between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK fre-
quency is kept at the maximum rate during a conversion, but
conversion are simply done less often, then the difference
between the two modes is dramatic. Figure 8 shows the
difference between reducing the DCLK frequency (“scal-
ing” DCLK to match the conversion rate) or maintaining
DCLK at the highest frequency and reducing the number of
conversion per second. In the later case, the converter
spends an increasing percentage of its time in power-down
mode (assuming the auto power-down mode is active).
If DCLK is active and CS is LOW while the ADS8341 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
ADS8341
16 SBAS136D
NOISE
The noise floor of the ADS8341 itself is extremely low, as
can be seen from Figures 10 thru 13, and is much lower than
competing A/D converters. The ADS8341 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low-level DC input was applied to the analog
input pins and the converter was put through 5,000 conver-
sions. The digital output of the A/D converter will vary in
output code due to the internal noise of the ADS8341. This
is true for all 16-bit SAR-type A/D converters. Using a
histogram to plot the output codes, the distribution should
appear bell-shaped with the peak of the bell curve represent-
ing the nominal code for the input value. The ±1σ, ±2σ, and
±3σ distributions will represent the 68.3%, 95.5%, and
99.7%, respectively, of all codes. The transition noise can be
calculated by dividing the number of codes measured by 6
and this will yield the ±3σ distribution or 99.7% of all codes.
Statistically, up to 3 codes could fall outside the distribution
when executing 1000 conversions. The ADS8341, with < 3
output codes for the ±3σ distribution, will yield a < ±0.5
LSB transition noise at 5V operation. Remember, to achieve
this low noise performance, the peak-to-peak noise of the
input signal and reference must be < 50µV.
FIGURE 10. Histogram of 5,000 Conversions of a DC Input at the
Code Transition, 5V operation external clock mode.
FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the
Code Center, 5V operation internal clock mode.
FIGURE 12. Histogram of 5,000 Conversions of a DC Input at the
Code Transition, 2.7V operation external clock mode.
FIGURE 13. Histogram of 5,000 Conversions of a DC Input at the
Code Center, 2.7V operation internal clock mode.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to ±0.25
LSBs. Averaging should only be used for input signals with
frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
4606
194
00
200
7FFC 7FFE 7FFF 8000 8001
Code
00
7FFC 7FFE 7FFF
4614
8000 8001
Code
203 183
31
683
3619
638
29
7FFD 7FFE 7FFF 8000 8001
Code
3572
586
790
22
30
7FFD 7FFE 7FFF 8000 8001
Code
ADS8341 17
SBAS136D
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8341 circuitry. This is particu-
larly true if the reference voltage is low and/or the conver-
sion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS8341 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8341 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8341 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high fre-
quency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS8341E ACTIVE SSOP/QSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341E/2K5 ACTIVE SSOP/QSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341E/2K5G4 ACTIVE SSOP/QSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341EB ACTIVE SSOP/QSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341EB/2K5 ACTIVE SSOP/QSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341EB/2K5G4 ACTIVE SSOP/QSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341EBG4 ACTIVE SSOP/QSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8341EG4 ACTIVE SSOP/QSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8341E/2K5 SSOP/
QSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS8341EB/2K5 SSOP/
QSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8341E/2K5 SSOP/QSOP DBQ 16 2500 346.0 346.0 29.0
ADS8341EB/2K5 SSOP/QSOP DBQ 16 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and www.ti.com/automotive
Automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprfTI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
