kyz_ 8GS-THOMSON M48T02 M48T12 CMOS 2K x 8 TIMEKEEPER SRAM = INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK and POWER-FAIL CONTROL CIRCUIT = BYTEWIDE RAM-LIKE CLOCK ACCESS = BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES and SECONDS = CLOCK ACCURACY oft 1 MINUTE a MONTH, @ 25C # SOFTWARE CONTROLLED CLOCK CALIBRATION for HIGH ACCURACY APPLICATIONS = AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION = CHOICE of TWO WRITE PROTECT VOLTAGES: M48T02:4.5V< Vpro< 4.75V M487T12:4.2V< Vpros 4.5V = SELF CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE = 10 YEARS of DATA RETENTION and CLOCK OPERATION in the ABSENCE cof POWER = PINand FUNCTION COMPATIBLE with JEDEC STANDARD 2K x 8 SRAMs DESCRIPTION The M48T02,12 TIMEKEEPER RAMis a 2K x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the MK48T02,12. Table 1. Signal Names AO-A10 Address Inputs DQo-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable Ww Write Enable Voec Supply Voltage Vss Ground itt { PCDIP24 (PC) Battery CAPHAT Figure 1. Logic Diagram Voc AO0-A10 M48To2 M48T12 mi th te Vss Alo1027 December 1994 1/14M48T02, M48T12 Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 C Tste Storage Temperature (Vcc Off, Oscillator Off) 40 to 85 C Vio Input or Output Voltages 0.3 to7 Vv Vec Supply Voltage 0.3 to7 lo Output Current 20 mA Pp Power Dissipation 1 W Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absoluis maximum ratings conditions for extanded periods of time may affect reliability. CAUTION: Negative undershoots below 0.3 volts are notaliowed on any pin while inthe Battery Back-up mode. Table 3. Operating Modes Mode Vec E G Ww DQo-DQ7 Power Deselect Vin x x High Z Standby 4.75V to 5.5V Write or Vit x Vit Din Active Read 4.5V to 5.5V Vit Vit Vin Dour Active Read Vit Vin Vin High 2 Active Deselect Vso to Vprp (min) x x x High 2 CMOS Standby Deselect < Vso x x x High Z Battery Back-up Mode Note: X = Vi or Vit Figure 2. DIP Pin Connections DESCRIPTION (cont'd) A special 24 pin 600mil DIP CAPHAT package houses the M487T02, 12 silicon with a quariz crystal and a long life lithium button cell to form a highly wo integrated battery backed-up memory and real time A7 1 2411Vcc clock solution. AG [2 23 f]A8 The M48T02, 12 button cell has sufficient capacity AS [3 22 f]A9 and storage life to maintain data and clock function- A4q4 210 Ww ality for an accumulated time pericd cf at least 10 A385 20G years in the absence of power over the operating A216 M4sTo2 19[ Ato temperature range. Aiq7 M48T12 igfE The M48T02,12 is a non-volatile pin and function Aogs 17] Daz equivalentto any JEDEC standard 2K x 8 SRAM. Dao qs 16 1] DQ6 It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of DQ1 f} 10 15 [J] DQS PROMs without any requirement for special write DQ2 11 14] DQ4 timing or limitations on the number of writes that Vee} 12 13 ]DQ3 can be performed. Alataze As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T02,12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory lo- cations to provide user accessible BYTEWIDE 2/4 S$GS-THOMSON JF MiCROELECLROMIES aM48T02, M48T12 Figure 3. Block Diagram Pts ' eee i 1 1 | ' ' ! 1 ' tt OSCILLATORAND [A_____| & x8 BiPORT ! 1 ! 1 t Lt 1 ' 32,768 Hz H 1 mm ttt ' : CRYSTAL |! ; Y no.aro it 7 ' tot POWER _ ! I it i i 1 DQO-DQ7 t 1! 2040 x8 1 1 oy SRAM ARRAY i LITHIUM {| 1 _ 1 CELL ot V rj1+-_. E i 1 PFD. ! 1 ' I * ' I | 4 VOLTAGE SENSE bh WwW i =ais:~ |S AND | w i i! SWITCHING BOK pt G 1 CIRCUITRY > G 1 | ' ' 1 1 ' : 1 beeen eeeeeee ee eee ee lee eee ee eee eee eee bee eee Vec Vss Alo1329 clock information in the bytes with addresses 7F8h- *FFh. The clock locations contain the year, month, date, day, hour, minute, and secondin 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BIPORT read/write memory cells. The M48T02,12 includes a clock control circuit which updatesthe clock bytes with current informa- tion once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T02, 12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When Vec is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system opera- tion brought on by low Vcc. As Vcc falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns. ky $SS;7H -THOMSON URLESTRORIGS AC MEASUREMENT CONDITIONS Input Rise and Fall Times <5ns Input Pulse Voltages 0.6V to 2.4V Input and Output Timing Ref. Voltages O0.8V to 2.2V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 4. AC Testing Load Circuit 5V 1.8k2 DEVICE UNDER OUT TEST a TKO mu, = 100PF C_ includes JIG capacitance Alo1019 3/14M48T02, M48T12 Table 4. Capacitance) (Ta = 25C, f=1 MHz) Symbol Parameter Test Condition Min Max Unit Cn Input Capacitance Vin =OV 10 pF Clo @ Input / Output Capacitance Vout = OV 10 pF Notes: 1. Effective capacitance calculated from the equation C = IAVAV with AV = 3V and power supply at 5V. 2. Outputsdeselacted Table 5. DC Characteristics (Ta =0 to 70C; Vec = 4.75V to 5.5V or 4.5V to 5.5V) Symbol Parameter Test Condition Min Max Unit my? Input Leakage Current OV < Vin< Vec H pA lLo a Output Leakage Current OV < Vout <= Vcc +5 BA loc Supply Current Outputs open 80 mA leer @ Supply Current (Standby) TTL E=Vn 3 mA loce Supply Current (Standby) CMOS E =Vcc0.2V 3 mA vii ) Input Low Voltage 0.3 0.8 V Vin Input High Voltage 2.2 Voc +0.3 V VoL Output Low Voltage lo. = 2.1mA 0.4 V Vou Output High Voltage lon =1mA 24 Vv Notes: 1. Outputs Deselected. 2. Measured with Control Bits setas follows: R ='1'; W, ST, KS, FT ='0". 3. Nagative spikes of -1V allowed for up to 10ns once per Cycle. Table 6. Power Down/Up Trip Points DC Characteristics") (Ta =0 to 70C) Symbol Parameter Min Typ Max Unit Veprp Power-fail Deselect Voltage (M48T02) 45 46 4.75 Vv VPFD Power-fail Deselect Voltage (M48T12) 42 43 45 Vv Vso Battery Back-up Switchover Voltage 3.0 Vv tor! Expected Data Retention Time 10 YEARS Notes: 1. All voltages referenced to Vss. 2. @ 25C 4/14 2 Gy SGS-THOMSON JF MiCROELECLROMIESM48T02, M48T12 Table 7. Power Down/Up Mode AC Characteristics (Ta =0 to 70C) Symbol Parameter Min Max Unit tpo E or W at Vin before Power Down 0 ps ip Verp (max) to Verb (min) Vcc Fall Time 300 us tre Veep (min) to Vso Vcc Fall Time 10 Us tr Veep{min) to Verb (max) Vcc Rise Time 0 ps tRE Vso to Vprp (min) Vec Rise Time 1 ps tREC E or W at Vin atter Power Up 2 ms Notes: 1. Verb (max) to Verb (min) fall time of less than t- may result in daselection/write protection not occurring until 50 ps after Vcc passes Veep (min). 2. Vero (min) to Vso fall time of less than t-3 may cause corruption of RAM data. Figure 5. Power Down/Up Mode AC Waveforms Vec VPFD (max) VpFp (min) Yso INPUTS OUTPUTS oneal Meee eee ceeeeee ener oT Te ee iF al 1DR ey tR iPD iFB tRB > tREC AECOGNIZED DON'T CARE x NOTE RECOGNIZED HIGH-Z VALID k sone 5 VALID (PER CONTROL INPUT) (PER CONTACL INPUT) AlOOBOB Note: Inputs may or may notbe recognized at this time. Caution should be taken to keep Ehigh as Vcc rises past Vero(min). Some systems may performs inadvertent write cycles after Vcc rises above Vprp{min) butbetore normal system operations begins Even though a power on raset is being applied to the processor a reset condition may not occur until after the system clock is running. }-THOMSON TRMECTARIES 5/14M48T02, M48T12 Table 8. Read Mode AC Characteristics (Ta = 0 to 70C; Voc =4.75V to 5.5V or 4.5V to 5.5V) M48T02 /12 Symbol Parameter -120 -150 -200 Unit Min Max Min Max Min Max tavav Read Cycle Time 120 150 200 ns tavav Address Valid to Output Valid 120 150 200 ns tELay Chip Enable Low to Output Valid 120 150 200 ns tetav Output Enable Low to Output Valid 75 75 80 ns tELax Ghip Enable Low to Output Transition 10 10 10 ns tetax Output Enable Low to Output Transition 5 5 5 ns tEHQzZ Chip Enable High to Output Hi-Z 30 35 40 ns teHaz Output Enable High to Output Hi-Z 30 35 40 ns taxax Address Transition to Output Transition 5 5 5 ns Figure 6. Read Mode AC Waveforms tAVAV 4 AO-A10 VALID tAvQY _ tt wr tAXQX et_#__ tELQv _* tEHQZ - _{ + }. 1ELGQX_ -}>) }?#. 1GLOV > 1GHQZ G A, # 1GLox * DQ@O-DQ7 4 VALIB - Al01330 6/14 Gy SGS-THOMSON JF MiCROELECLROMIESM48T02, M48T12 Table 9. Write Mode AC Characteristics (Ta =0 to 70C; Voc = 4.75V to 5.5V or 4.5V to 5.5V) M48TO2 / 12 Symbol Parameter -120 -150 -200 Unit Min Max Min Max Min Max tavaV Write Cycle Time 120 150 200 ns TAVWL Address Validto Write Enable Low 0 0 0 ns taveL Address Validto Chip Enable Low 0 0 0 ns twLWH Write Enable Pulse Width 75 90 120 ns tELEH Ghip Enable Low to Chip Enable High 75 90 120 ns twHax Write Enable High to Address Transition 10 10 10 ns tEHAX Chip Enable High te Address Transition 10 10 10 ns tovwH Input Valid to Write Enable High 35 40 60 ns tpVEH Input Valid to Chip Enable High 35 40 60 ns twHDx Write Enable High to Input Transition 5 5 5 ns teHDx Chip Enable High to Input Transition 5 5 5 ns twiaz Write Enable Low to Output Hi-Z 40 50 60 ns tavwu Address Validto Write Enable High 90 120 140 ns taVEH Address Validto Chip Enable High 90 120 140 ns twHox Write Enable High to Output Transition 10 10 10 ns READ MODE data will remain valid for taxax (Output Data Hold The M48T02, 12 is in the Read Mode whenever W {Write Enable} is high and E (Chip Enable) is low. The device architecture allows ripple-through ac- cess of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data |/O pins within tavav (Address Access Time) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the Eand G access times are not met, valid data will be available atter the latter of the Chip Enable Access Time (teLay} or Output Enable Access Time (tgLav). The state of the eight three-state Data I/O signals is controlled by E and. If the outputs are activated before tavay, the data lines will be driven to an indeterminate state until tavav. Ifthe Address Inputs are changed while E and G remain active, output S-THOMSON ROBLES RAGS 7 a Time) but will go indeterminate until the next Ad- dress Access. WRITE MODE The M48T02,12is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E_A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from Ghip Enable or twHax fromm Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tpvwu priorto the end of write and remain valid tor twHpx atterward.G should be kept high curing write cycles to avoid bus conten- tion; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs twLaz after Ww falls. TAAM48T02, M48T12 Figure 7. Write Enable Controlled, Write AC Waveforms A0-A10 ml =| DQO-DQ7 iaVAY > VALID k | 1AVEL tAVWH wi tWHAX - YH Ww iwdy -TMH tt hr TAVWL \. j ot wr tWLOZ 4. {WHaX * tWHDX t > DATA INPUT pt iDVWH __+| AlO1331 Figure 8. Chip Enable Controlled, Write AC Waveforms A0-A10 ml = DQO-DOQ7 a <_ TAVAV VALID tAVEH tAVWL Mi 1AVEL iELEH tEHAX Y_}__- f ee k tEHDX DATA INPUT -4_ iDVEH Al01332B 8/14 Gy SGS-THOMSON JF MiCROELECLROMIES a aM48T02, M48T12 DATA RETENTION MODE With valid Vcc applied, the M48T02, 12 operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-tail deselect, write protecting itself when Vec falls within the Vprp(max), Vero(min) window. All outputs become high impedance, and all inputs are treated as "don't care. Note: A power failure during a write cycle may corruptdata at the currently addressed location, but does not jeopardize the rest of the RAMs content. At voltages below Vprp(min}, the user can be as- sured the memory will be ina write protected state, provided the Vcc Tall time is not less than tr. The M48T02,12 may respond to transient noise spikes on Vcc that reach into the deselect window during the time the device is sampling Vcc. Therefore, decoupling of the power supply lines is recom- mended. The power switching circuit connects external Vec to the RAM and disconnectsthe battery when Voc rises above Vso. As Vcc rises, the battery voltage is checked. If the voltage is too low, an_internal Battery Net OK (BOK) flag will be set. The BOK flag can be checked atter power up. If the BOK flag is set, the first write attempted will be blocked. The flag is automatically cleared after the first write, and nermal RAM operation resumes. Figure 9 illus- trates how a BOK check routine could be struc- tured. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted betore clock data is read to prevent reading data in transition. Because the BiIPORT TIME- KEEPER cells in the RAM array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. Updating is halted when a1 is written to the READ bit, the seventh bit in the control register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count; thatis, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated si- multanecusly. A halt will netinterrupt an update in progress. Updating is within a second after the bit is reset toa 0. ST ROLES Fe GS-THOMSON LECT AGS . ri Figure 9. Checking the BOK Flag Status POWER-UP READ DATA AT ANY ADDRESS ! WRITE DATA COMPLEMENT BACK TO SAME ADDRESS i READ DATA AT SAME ADDRESS AGAIN ISDATA COMPLEMENT OFFIRST READ? NO (BATTERY LOW) NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED} .____| (BATTERY OK) WRITE ORIGINAL DATA BAGSK TQ SAME ADDRESS CONTINUE AlQ0607 Setting the Clock The eighth bit of the control register is the WRITE bit. Setting the WRITE bitto a1, like the READ bit, halts updates to the TIMEKEEPER registers. The user canthen load themwith the correct day, date, and time data in 24 hour BCD format (see Table 10). Resetting the WRITE bit to a0 thentransters the values of all time registers (7F9h-7FFh) to the actual TIMEKEEPER counters and allows normal operationto resume. The FT bit and the bits marked as '0in Table 10 must be written to 0 to allow for normal TIMEKEEPER and RAM operation. o/14M48T02, M48T12 Stopping and Starting the Oscillator The oscillator may be stopped at any time. It the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain onthe battery. The STOP bit is the MSB of the seconds register. Setting ittoa'1 stops the oscillator. The M48T02, 12is shipped fram SGS-THOMSON with the STOP bit set to a 1. When reset to a 0, the M48T02, 12 oscillator starts within 1 second. Calibrating the Clock The M487T02,12 is driven by a quarz controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T02, 12is accurate within +1 minute per month at 25C without calibration. The devices are tested not to exceed 35 PPM (parts per million} oscillator frequency error at25C, which equates to about + 1.53 minutes per month. Of course the oscillation rate of any crystal changes with tem- perature. Most clock chips compensate for crystal frequency and temperature shift error with cumber- some trim capacitors. The M48T02,12 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in Figure 10. The number of times pulses Table 10. Register Map are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between O and 31 in binary form. The sixth bit is a sign bit; '1 indicates positive calibration, 0 indicates negative calibration. Gali- bration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary 1 is loaded into the register, only the first 2 minutes in the 64 minute cycle will be moditied; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 PPM ot adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent+10.7 or- 5.35 seconds per month which corresponds to a total range of +5.5 or- 2.75 minutes per month. Address se Formae D7 D6 D5 D4 D3 D2 D1 Do 7FFA 10 Years Year Year 00-99 7FEh 0 0 0 10 M. Month Month 01-12 7FDh 0 a) 10 Date Date Date 01-31 7FCh 0 FT 0 0 0 Day Day 01-07 7FBh KS a) 10 Hours Hours Hour 00-23 7FAR 0 10 Minutes Minutes Minutes 00-59 7F9h ST 10 Seconds Seconds Seconds 00-59 7F8h Ww R S Calibration Control Keys: S =SIGN Bit FT = FREQUENCY TEST Bit (Set to 0 for normal clock operation) KS =KICK START Bit R_ =READ Bit W = WRITE Bit ST = STOP Bit 0 =Must be sat to 0 10/14 kyz SSS THOMS OMSON TELECT RNSM48T02, M48T12 Figure 10. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION TU] rT LI] rT LI] Alooso4 Two methods are available for ascertaining how much calibration a given M48T02, 12 may require. The first involves simply setting the clock, letting it run fora month and comparing it to a Known accu- rate reference (like WWV broadcasts). While that may seem crude, it allows the designerto give the end user the ability to calibrate his clock as his environment may require, even after the final prod- uct is packaged in a non-user serviceable enclo- sure. All the designer has to do is provide a simple utility that accesses the Calibration byte. The utility could even be menu driven and made fcolprcof. The second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. When the Frequency Test {FT) bit, the seventh-most significant bit in the Day Register, is set to a 1, and the oscillator is running at 32,768 Hz, the LSB (DQ0} of the Seconds Reg- ST ROLES Fe GS-THOMSON LECT AGS . ri ister will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For exam- ple, a reading of 512.01024 Hz would indicate a +20 PPM oscillator frequency errer, requiring a -10(001010)to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. Thedevice must be selected and addresses must stable at Address 7F9h when read- ing the 512 Hz on DQO. The FT bit must be set using the same method used to set the clock, using the Write bit. The LSB of the Seconds Register is monitored by holding the M48T02,12 in an extended read of the Seconds Register, without having the Read bit set. The FT bit MUST be reset to 0 fornormal clock operations to resume. 11/14M48T02, M48T12 ORDERING INFORMATION SCHEME Example: M48T02 -120 PC 1 Supply Voltage and Write Speed Package Temp. Range Protect Voltage 02 Vcc = 4.75V to 5.5V -120 = =120ns PC PCDIP24 1 0 to 70C Vprp = 4.5 to 4.75V 150 {50ns 12 Voc = 4.5V to 5.5V Vprp = 4.2V to 4.5 200 200ns For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory Shorttorm catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 1afi4 S$GS-THOMSON JF MiCROELECLROMIESM48T02, M48T12 PCDIP24 - 24 pin Plastic DIP, battery CAPHAT mm inches Symb Typ Min Max Typ Min Max A 8.89 9.65 0.350 0.380 Al 0.38 0.76 0.015 0.030 A2 8.36 8.89 0.329 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 0.20 0.31 0.008 0.012 D 34.29 34.80 1.350 1.370 E 17.83 18.34 0.702 0.722 el 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 24 24 PCDIP24 a a A2|A I | | Ait LT Cc | B1-wl{hw B Let eA P e3 aaa D i" N a E @ PCDIP Drawing is notto scale iy, 2GS-THOMSON 13/14 TF MiCkcELes poRnes salt nsM48T02, M48T12 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility tor the consequences of use of such information nor for any infringementof patents or other rights ofthird parties which may resulttrom its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSCON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved TIMEKEEPER, CAPHAT, BYTEWIDE and BiPORT are trademarks of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 14/14 S$GS-THOMSON JF MiCROELECLROMIES