Features * EE Reprogrammable 4,194,304 x 1 bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) * In-System Programmable via 2-wire Bus * Simple Interface to SRAM FPGAs * Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX(R) Devices, * * * * * * * * ORCA(R) FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan(R), Virtex(R) FPGAs Cascadable Read Back to Support Additional Configurations or Future Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available in PLCC Package (Pin Compatible Across Product Family) Emulation of Atmel's AT24CXXX Serial EEPROMs Available in 3.3V 10% LV and 5V 5% C Versions System-friendly READY Pin Low-power Standby Mode Description The AT17C040 and AT17LV040 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays (FPGA). The AT17 Series is packaged in the popular 44-pin TQFP and 44-pin PLCC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming internal EEPROM bytes. These devices also support a system-friendly READY pin, which signifies a "good" power level to the FPGA and can be used to ensure reliable system power-up. 4-megabit FPGA Configuration EEPROM Memory AT17C040 AT17LV040 Advance Information The AT17 Series Configurators can be programmed with industry-standard programmers or Atmel's ATDH2200E programming system. Pin Configurations 44 TQFP NC CLK NC GND DATA NC VCC NC NC SER_EN NC 44 43 42 41 40 39 38 37 36 35 34 NC NC NC NC NC NC NC NC NC NC NC 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 NC NC NC NC NC NC NC NC NC NC NC 12 13 14 15 16 17 18 19 20 21 22 NC NC NC NC NC NC NC NC NC NC NC WP1 RESET/OE WP2 CE NC NC GND NC NC CEO/A2 READY 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 WP1 RESET/OE WP2 CE NC NC GND NC NC CEO/A2 READY NC NC NC NC NC NC NC NC NC NC NC 6 5 4 3 2 1 44 43 42 41 40 NC CLK NC GND DATA NC VCC NC NC SERER NC 44 PLCC Rev. 2282C-06/01 1 Block Diagram SER_EN WP1 WP2 CEO (A2) FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In master mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Series Configuration EEPROM has been designed for compatibility with the master serial mode. This document discusses the AT40K FPGA interface. For more details or for AT6K FPGA applications, please reference the "AT40K Series Configuration" or the "AT6000 Series Configuration" application notes. Controlling the Highdensity AT17 Series Serial EEPROMs During Configuration Most connections between the FPGA device and the AT17 Series Configuration EEPROM are simple and self-explanatory: * The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices. * The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator. * The CEO output of any AT17C/LV040 drives the CE input of the next AT17C/LV040 in a cascade chain of EEPROMs. * SER_EN must be connected to VCC, (except during ISP). The READY pin is available as an open-collector indicator of the device's RESET status; it is driven Low while the device is in its POWER-ON RESET cycle and released (tri-stated) when the cycle is complete. 2 AT17C/LV040 AT17C/LV040 There are two different ways to use the inputs CE and OE. Condition 1 The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE(1) in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration. The AT17 Series Configurator does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle. Note: 1. For this condition, the reset polarity of the EEPROM must be set active High. Figure 1. Condition 2 Connection AT17C/LV040 AT40K RESET RESET M2 M1 M0 D<0> CCLK CON INIT DATA CLK CE RESET/OE VCC SER_EN READY GND Notes: Condition 2 1. Use of the READY pin is optional. 2. Reset polarity must be set to active Low. The FPGA CON pin drives only the CE input of the AT17 Series Configurator, while the OE input is driven by the FPGA INIT pin (Figure 1). This connection works under all normal circumstances, even when the user aborts a configuration before CON has gone High. A Low level on the RESET/OE(1) input - during FPGA reset - clears the configurator's internal address pointer, so that the reconfiguration starts at the beginning. Note: 1. For this condition, the reset polarity of the EEPROM must be set active Low. The AT17 Series Configurator does not require an inverter for either condition since the RESET polarity is programmable. Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. As the last bit from the first Configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (default High) level. If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to its inactive (default Low) level. For more details on programming the EEPROM's reset polarity, please reference "Programming Specification for Atmel's FPGA Configuration EEPROMs". 3 AT17 Series Reset Polarity The AT17 Series Configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry standard programmer algorithms. For more details on programming the EEPROM's reset polarity, please reference the "Programming Specification for Atmel's FPGA Configuration EEPROMs" application note. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. See the "Programming Specification for Atmel's FPGA Configuration EEPROMs" application note for further information. The AT17C parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal. Standby Mode The AT17C/LV040 enters a low-power standby mode whenever CE is asserted High. In this mode, the Configurator consumes less than 0.5 mA of current at 5.0 volts with CMOS level inputs. The output remains in a high impedance state regardless of the state of the OE input. 4 AT17C/LV040 AT17C/LV040 Pin Configurations 44 TQFP Pin 44 PLCC Pin Name I/O 40 2 DATA I/O 43 5 CLK I Clock input. Used to increment the internal address and bit counter for reading and programming. 12 18 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming. Disables by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. See the "Programming Specification for Atmel's FPGA Configuration EEPROMs" application note for more details. 13 19 RESET/OE I RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. 14 20 WP2 I WRITE PROTECT (2). Used to protect portions of memory during programming. Disables by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. See the Programming Specification for Atmel's FPGA Configuration EEPROMs" application note for more details. 15 21 CE I Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming Mode (i.e., when SER_EN is Low). 18 & 41 3 & 24 GND 21 Description Three-state DATA output for configuration. Open-collector bi-directional pin for programming. Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended. CEO O Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again. A2 I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low; see the "Programming Specification for Atmel's FPGA Configuration EEPROMs" application note for more details). 27 22 28 READY O Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (Recommend a 4.7 K pull-up on this pin if used). 35 41 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. 38 44 VCC +3.3V/+5V power supply pin. 5 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .............................-0.1V to VCC + 0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C Operating Conditions AT17C040 Symbol VCC 6 Description AT17LV040 Min Max Min Max Units Commercial Supply voltage relative to GND, -0C to +70C 4.75 5.25 3.0 3.6 V Industrial Supply voltage relative to GND, -40C to +85C 4.5 5.5 3.0 3.6 V Military Supply voltage relative to GND, -55C to +125C 4.5 5.5 3.0 3.6 V AT17C/LV040 AT17C/LV040 DC Characteristics for AT17C040 VCC = 5V 5% Commercial, 5V 10% Industrial/Military Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0 0.8 V VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) 0.4 V ICCA Supply Current, Active Mode 10 mA IL Input or Output Leakage Current(VIN = VCC or GND) 10 A Commercial 0.5 mA ICCS1 Supply Current, Standby Mode, CMOS Industrial/Military 0.5 mA ICCS2 Supply Current, Standby Mode, TTL Comm./Industrial 1.0 mA 3.86 V Commercial 0.32 3.76 V V Industrial 0.37 3.7 V V Military -10 DC Characteristics for AT17LV040 VCC = 3.3V 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +2.5 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current(VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 2.4 V V Military 0.4 V 5 mA 10 A Commercial 100 A Industrial/Military 100 A -10 7 AC Characteristics CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TOH TCAC TDF TCE DATA TOH AC Characteristics When Cascading RESET/OE CE CLK TCDF DATA LAST BIT TOCK FIRST BIT TOOE TOCE CEO TOCE 8 AT17C/LV040 AT17C/LV040 . AC Characteristics for AT17C040 VCC = 5V 5% Commercial, VCC = 5V 10% Industrial/Military Commercial Symbol Description TOE(2) OE to Data Delay (2) TCE TCAC (2) Min Max Industrial/Military(1) Max Units 30 35 ns CE to Data Delay 45 45 ns CLK to Data Delay 50 50 ns TOH Data Hold From CE, OE, or CLK TDF(3) CE or OE to Data Float Delay TLC CLK Low Time 20 20 ns THC CLK High Time 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 20 25 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 20 20 ns FMAX MAX Input Clock Frequency 15 15 MHz Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. AC Characteristics for AT17C040 When Cascading VCC = 5V 5% Commercial/VCC = 5V 10% Industrial/Military Commercial Symbol Description TCDF (3) CLK to Data Float Delay TOCK(2) TOCE(2) TOOE(2) FMAX Notes: Max Units 50 50 ns CLK to CEO Delay 35 40 ns CE to CEO Delay 35 35 ns RESET/OE to CEO Delay 30 30 ns MAX Input Clock Frequency Min 12.5 Max Industrial/Military(1) Min 12.5 MHz 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. 9 AC Characteristics for AT17LV040 VCC = 3.3V 10% Commercial Symbol Description TOE(2) OE to Data Delay (2) TCE TCAC (2) Min Max Industrial/Military(1) Max Units 50 55 ns CE to Data Delay 55 60 ns CLK to Data Delay 55 60 ns TOH Data Hold From CE, OE, or CLK TDF(3) CE or OE to Data Float Delay TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX MAX Input Clock Frequency 15 10 MHz Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. AC Characteristics for AT17LV040 When Cascading VCC = 3.3V 10% Commercial Symbol Description TCDF(3) CLK to Data Float Delay TOCK(2) TOCE(2) TOOE(2) FMAX Notes: 10 Max Units 50 50 ns CLK to CEO Delay 50 55 ns CE to CEO Delay 35 40 ns RESET/OE to CEO Delay 35 35 ns MAX Input Clock Frequency Min 12.5 Max Industrial/Military(1) Min 10 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. AT17C/LV040 MHz AT17C/LV040 Ordering Information - 5V Devices Memory Size Ordering Code Package Operation Range 4M AT17C040-10TQC 44A Commercial (0C to 70C) AT17C040-10TQI 44A Industrial (-40C to 85C) AT17C040-10BJC 44J Commercial (0C to 70C) AT17C040-10BJI 44J Industrial (-40C to 85C) Ordering Information - 3.3V Devices Memory Size Ordering Code Package Operation Range 4M AT17LV040-10TQC 44A Commercial (0C to 70C) AT17LV040-10TQI 44A Industrial (-40C to 85C) AT17LV040-10BJC 44J Commercial (0C to 70C) AT17LV040-10BJI 44J Industrial (-40C to 85C) Package Type 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 11 AT17C/LV040 Packaging Information 44A, 44-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in inches and (Millimeters)* JEDEC STANDARD MS-018 AC 12.21(0.478) SQ 11.75(0.458) PIN 1 ID 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC .045(1.14) X 45 PIN NO. 1 IDENTIFY .045(1.14) X 30 - 45 .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .500(12.7) REF SQ 0.20(.008) 0.09(.003) .630(16.0) .590(15.0) .656(16.7) SQ .650(16.5) .050(1.27) TYP 10.10(0.394) SQ 9.90(0.386) .012(.305) .008(.203) .021(.533) .013(.330) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) 1.20(0.047) MAX 0 7 .022(.559) X 45 MAX (3X) 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) *Controlling dimensions in millimeters 12 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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