LTC4227CUFD-2#PBF - ANALOG DEVICES

LTC4227

422712fa

For more information www.linear.com/LTC4227

Typical applicaTion

FeaTures DescripTion

Dual Ideal Diode and

Single Hot Swap Controller

The LT C

4227 offers ideal diode-OR and Hot Swap™

functions for two power rails by controlling external N-

channel MOSFETs. MOSFETs acting as ideal diodes replace

two high power Schottky diodes and the associated heat

sinks, saving power and board area. A Hot Swap control

MOSFET allows a board to be safely inserted and removed

from a live backplane by limiting inrush current. The supply

output is also protected against short-circuit faults with a

fast acting current limit and internal timed circuit breaker.

The LTC4227 regulates the forward voltage drop across

the MOSFETs to ensure smooth current transfer from one

supply to the other without oscillation. The ideal diodes

turn on quickly to reduce the load voltage droop during

supply switchover. If the input supply fails or is shorted,

a fast turn-off minimizes reverse-current transients.

The LTC4227 allows turn-on/off control, and reports fault

and power good status for the supply.

PART OVERCURRENT FAULT START-UP DELAY

LTC4227-1 LATCH OFF 100ms

LTC4227-2 RETRY 100ms

LTC4227-3 LATCH OFF 1.6ms

LTC4227-4 RETRY 1.6ms

Diode-OR with Hot Swap Application

applicaTions

n Power Path and Inrush Current Control for

Redundant Supplies

n Low Loss Replacement for Power Schottky Diodes

n Allows Safe Hot Swapping from a Live Backplane

n 2.9V to 18V Operating Range

n Controls N-Channel MOSFETs

n Limits Peak Fault Current in ≤1µs

n 0.5µs Ideal Diode Turn-On and Reverse Turn-Off Time

n Adjustable Current Limit with Circuit Breaker

n Smooth Switchover without Oscillation

n Adjustable Current Limit Fault Delay

n Fault and Power Status Output

n 20-Lead 4mm × 5mm QFN and 16-Lead SSOP Packages

n Redundant Power Supplies and Supply Holdup

n Computer Systems and Servers

n Telecom Networks

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

BACKPLANE

CONNECTOR

12V

CARD

CONNECTOR

CPO1

D2ON

PWRGD

FAULT

137k

100µF

12V

7.6A

20k

INTVCC GND

IN1 DGATE1 DGATE2

LTC4227

4227 TA01a

SiR462DP Si7336ADP0.006Ω

HGATE OUTSENSE+SENSE–

CPO2

0.1µF

IN2

0.1µF

SiR462DP

0.1µF0.1µF

TMR

Smooth Supply Switchover

200ns/DIV

IIN2

2A/DIV

IIN1

2A/DIV

IN2

1V/DIV

IN1

1V/DIV

4227 TA01b

LTC4227

422712fa

For more information www.linear.com/LTC4227

absoluTe MaxiMuM raTings

Supply Voltages

IN1, IN2 .................................................. –0.3V to 24V

INTVCC ..................................................... –0.3V to 7V

Input Voltages

ON, EN, D2ON ....................................... –0.3V to 24V

TMR ....................................... –0.3V to INTVCC + 0.3V

SENSE+, SENSE– ................................... –0.3V to 24V

Output Voltages

FA U LT, PWRGD ...................................... –0.3V to 24V

CPO1, CPO2 (Note 3) ............................. –0.3V to 35V

DGATE1, DGATE2 (Note 3) ..................... –0.3V to 35V

(Notes 1, 2)

20 19 18 17

7 8

TOP VIEW

UFD PACKAGE

20-LEAD (4mm × 5mm) PLASTIC QFN

9 10

SENSE–

SENSE+

IN1

INTVCC

GND

IN2

TMR

D2ON

FAULT

DGATE1

CPO1

HGATE

OUT

DGATE2

CPO2

PWRGD

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL

GN PACKAGE

16-LEAD PLASTIC SSOP NARROW

TOP VIEW

DGATE1

SENSE–

SENSE+

IN1

INTVCC

GND

IN2

DGATE2

CPO1

HGATE

OUT

TMR

D2ON

PWRGD

CPO2

TJMAX = 125°C, θJA = 110°C/W

pin conFiguraTion

HGATE (Note 4) ..................................... –0.3V to 35V

OUT ....................................................... –0.3V to 24V

Average Currents

FA U LT, PWRGD ....................................................5mA

INTVCC ................................................................. 1mA

Operating Temperature Range

LTC4227C ................................................ 0°C to 70°C

LTC4227I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

GN Package ...................................................... 300°C

LTC4227

422712fa

For more information www.linear.com/LTC4227

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4227CUFD-1#PBF LTC4227CUFD-1#TRPBF 42271 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4227CUFD-2#PBF LTC4227CUFD-2#TRPBF 42272 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4227CUFD-3#PBF LTC4227CUFD-3#TRPBF 42273 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4227CUFD-4#PBF LTC4227CUFD-4#TRPBF 42274 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4227IUFD-1#PBF LTC4227IUFD-1#TRPBF 42271 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4227IUFD-2#PBF LTC4227IUFD-2#TRPBF 42272 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4227IUFD-3#PBF LTC4227IUFD-3#TRPBF 42273 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4227IUFD-4#PBF LTC4227IUFD-4#TRPBF 42274 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4227CGN-1#PBF LTC4227CGN-1#TRPBF 42271 16-Lead Plastic SSOP 0°C to 70°C

LTC4227CGN-2#PBF LTC4227CGN-2#TRPBF 42272 16-Lead Plastic SSOP 0°C to 70°C

LTC4227IGN-1#PBF LTC4227IGN-1#TRPBF 42271 16-Lead Plastic SSOP –40°C to 85°C

LTC4227IGN-2#PBF LTC4227IGN-2#TRPBF 42272 16-Lead Plastic SSOP –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VIN Input Supply Range l2.9 18 V

IIN Input Supply Current l2 4 mA

VINTVCC Internal Regulator Voltage l4.5 5 5.6 V

VINTVCC(UVL) Internal VCC Undervoltage Lockout INTVCC Rising l2.1 2.2 2.3 V

∆VINTVCC(HYST) Internal VCC Undervoltage Lockout

Hysteresis

l30 60 90 mV

Ideal Diode Control

∆VFWD(REG) Forward Regulation Voltage

(VINn – VSENSE+)

l10 25 40 mV

∆VDGATE External N-Channel Gate Drive

(VDGATEn – VINn)

IN < 7V, ∆VFWD = 0.1V, I = 0, –1µA

IN = 7V to 18V, ∆VFWD = 0.1V, I = 0,

–1µA

ICPO(UP) CPOn Pull-Up Current CPO = IN = 2.9V

CPO = IN = 18V

–60

–50

–95

–85

–120

–110

µA

IDGATE(FPU) DGATEn Fast Pull-Up Current ∆VFWD = 0.2V, ∆VDGATE = 0V, CPO = 17V –1.5 A

IDGATE(FPD) DGATEn Fast Pull-Down Current ∆VFWD = – 0.2V, ∆VDGATE = 5V 1.5 A

IDGATE2(DN) DGATE2 Off Pull-Down Current D2ON = 2V, ∆VDGATE2 = 2.5V l40 100 200 µA

tON(DGATE) DGATEn Turn-On Delay ∆VFWD = 0.2V , CDGATE = 10nF l0.25 0.5 µs

tOFF(DGATE) DGATEn Turn-Off Delay ∆VFWD = –0.2V , CDGATE = 10nF l0.2 0.5 µs

tPLH(DGATE2) D2ON Low to DGATE2 High l40 100 µs

LTC4227

422712fa

For more information www.linear.com/LTC4227

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Hot Swap Control

∆VSENSE(CB) Circuit Breaker Trip Sense Voltage

(VSENSE+ – VSENSE–)

l47.5 50 52.5 mV

∆VSENSE(ACL) Active Current Limit Sense Voltage

(VSENSE+ – VSENSE–)

l60 65 70 mV

∆VHGATE External N-Channel Gate Drive

(VHGATE – VOUT)

IN < 7V, I = 0, –1µA

IN = 7V to 18V, I = 0, –1µA

4.8

∆VHGATE(PG) Gate-Source Voltage for Power Good l3.6 4.2 4.8 V

IHGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V l–7 –10 –13 µA

IHGATE(DN) External N-Channel Gate Pull-Down

Current

Gate Drive Off

OUT = 12V , HGATE = OUT + 5V

l150 300 500 µA

IHGATE(FPD) External N-Channel Gate Fast Pull-Down

Current

Fast Turn-Off

OUT = 12V , HGATE = OUT + 5V

l100 200 300 mA

tPHL(SENSE) Sense Voltage (SENSE+ – SENSE–)

High to HGATE Low

∆VSENSE = 300mV, CHGATE = 10nF l 0.5 1 µs

tOFF(HGATE) EN High to HGATE Low

ON Low to HGATE Low

SENSE+ Low to HGATE Low

µs

tD(HGATE) ON High, EN Low to HGATE Turn-On

Delay

LTC4227-1, LTC4227-2

LTC4227-3, LTC4227-4

0.8

100

1.6

150

2.4

tP(HGATE) ON to HGATE Propagation Delay ON = Step 0.8V to 2V l10 20 µs

Input/Output Pin

ISENSE+SENSE+ Input Current SENSE+ = 12V l1.2 2.2 mA

ISENSE–SENSE– Input Current SENSE– = 12V l10 50 100 µA

VSENSE+(UVL) SENSE+ Undervoltage Lockout SENSE+ Rising l1.75 1.9 2.05 V

∆VSENSE+(HYST) SENSE+ Undervoltage Lockout

Hysteresis

l10 50 90 mV

VON(TH) ON Pin Threshold Voltage ON Rising l1.21 1.235 1.26 V

∆VON(HYST) ON Pin Hysteresis l40 80 140 mV

VON(RESET) ON Pin Fault Reset Threshold Voltage ON Falling l0.55 0.6 0.65 V

VD2ON(H,TH) D2ON Pin High Threshold D2ON Rising l1.21 1.235 1.26 V

VD2ON(L,TH) D2ON Pin Low Threshold D2ON Falling l1.07 1.145 1.22 V

∆VD2ON(HYST) D2ON Pin Hysteresis l40 90 140 mV

IIN(LEAK) Input Leakage Current (ON, D2ON) ON = D2ON = 5V l0 ±1 µA

VEN(TH) EN Pin Threshold Voltage EN Rising l1.185 1.235 1.284 V

∆VEN(HYST) EN Pin Hysteresis l40 110 200 mV

IEN(UP) EN Pull-Up Current EN = 1V l –7 –10 –13 µA

VTMR(TH) TMR Pin Threshold Voltage TMR Rising

TMR Falling

1.198

0.15

1.235

0.2

1.272

0.25

ITMR(UP) TMR Pull-Up Current TMR = 1V, In Fault Mode l –75 –100 –125 µA

ITMR(DN) TMR Pull-Down Current TMR = 2V, No Faults l 1.4 2 2.6 µA

ITMR(RATIO) TMR Current Ratio ITMR(DN)/ITMR(UP) l 1.4 2 2.7 %

IOUT OUT Pin Current OUT = 11V, IN = 12V, ON = 2V

OUT = 13V, IN = 12V, ON = 2V

1.9

100

µA

VOL Output Low Voltage (FAULT, PWRGD) I = 1mA l0.15 0.4 V

LTC4227

422712fa

For more information www.linear.com/LTC4227

Typical perForMance characTerisTics

Diode Gate Voltage vs Current Diode Gate Voltage vs IN Voltage Hot Swap Gate Voltage vs Current

IN Supply Current vs Voltage INTVCC Load Regulation CPO Voltage vs Current

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of

the device pins are negative. All voltages are referenced to GND unless

otherwise specified.

Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of

10V above and a diode below IN. Driving these pins to voltages beyond the

clamp may damage the device.

Note 4: An internal clamp limits the HGATE pin to a minimum of 10V

above and a diode below OUT. Driving this pin to voltages beyond the

clamp may damage the device.

TA = 25°C, VIN = 12V, unless otherwise noted.

VIN (V)

IIN (mA)

3 6 9 12

4227 G01

15 18

0.5

1.5

2.5

VOUT = 3.3V VOUT = 12V

VOUT = 0V

ILOAD (mA)

INTVCC (V)

–2 –4 –6 –8

4227 G02

–10

VIN = 12V

VIN = 3.3V

ICPO (µA)

–2 –60 –100

4227 G03

–20 –40 –80 –120

VCPO – VIN (∆VCPO) (V)

VIN = 18V

VIN = 2.9V

IDGATE (µA)

–2 –60 –100

4227 G04

–20 –40 –80 –120

VDGATE – VIN (∆VDGATE) (V)

VIN = 18V

VIN = 2.9V

VSENSE+ = VIN – 0.1V

IHGATE (µA)

0–6 –10

4227 G05

–2 –4 –8 –12

GATE DRIVE (∆VHGATE) (V)

VIN = 12V

VOUT = VIN

VIN = 2.9V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOH Output High Voltage (FAULT, PWRGD) I = –1µA lINTVCC – 1 INTVCC – 0.5 V

IOH Input Leakage Current (FAULT, PWRGD) V = 18V l0 ±1 µA

IPU Output Pull-Up Current (FAULT, PWRGD) V = 1.5V l–7 –10 –13 µA

tRST(ON) ON Low to FAULT High l20 40 µs

VIN (V)

VDGATE – VIN (∆VDGATE) (V)

3 6 9 12

4227 G04b

15 18

VSENSE+ = VIN – 0.1V

LTC4227

422712fa

For more information www.linear.com/LTC4227

HGATE Pull-Up Current

vs Temperature

TMR Pull-Up Current

vs Temperature

PWRGD, FAULT Output Low

Voltage vs Current

Typical perForMance characTerisTics

TA = 25°C, VIN = 12V, unless otherwise noted.

TEMPERATURE (°C)

–50

–9.0

HGATE PULL-UP CURRENT (µA)

–9.5

–10.0

–10.5

–11.0

–25 0 25 50

4227 G10

75 100

TEMPERATURE (°C)

–50

–97

TMR PULL-UP CURRENT (µA)

–98

–99

–100

–101

–103

–25 0 25 50

4227 G11

75 100

–102

CURRENT (mA)

OUTPUT LOW VOLTAGE (V)

0.4

0.6

4227 G12

0.2

01235

0.8

OUT Current vs Voltage

Hot Swap Gate Voltage

vs IN Voltage

Circuit Breaker Trip Voltage

vs Temperature

Active Current Limit Sense

Voltage vs Temperature

Active Current Limit Delay

vs Sense Voltage

TEMPERATURE (°C)

–50

CIRCUIT BREAKER TRIP VOLTAGE (mV)

–25 0 25 50

4227 G07

75 100

TEMPERATURE (°C)

–50

ACTIVE CURRENT LIMIT SENSE VOLTAGE (mV)

–25 0 25 50

4227 G08

75 100

SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV)

0.1

ACTIVE CURRENT LIMIT DELAY (µs)

100

100 150 200 250 300

4227 G09

CHGATE = 10nF

VOUT (V)

2.0

1.6

1.2

0.8

0.4

–0.4 9 15

4227 G06

3 6 12 18

OUT

(mA)

VIN = 12V

VIN (V)

GATE DRIVE (∆VHGATE) (V)

3 6 9 12

4227 G05b

15 18

VOUT = VIN

LTC4227

422712fa

For more information www.linear.com/LTC4227

pin FuncTions

CPO1, CPO2: Charge Pump Output. Connect a capacitor

from CPO1 or CPO2 to the corresponding IN1 or IN2 pin.

The value of this capacitor is approximately 10× the gate

capacitance (CISS) of the external MOSFET for ideal diode

control. The charge stored on this capacitor is used to pull

up the gate during a fast turn-on. Leave this pin open if

fast turn-on is not needed.

DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Out-

put. Connect this pin to the gate of an external N-channel

MOSFET for ideal diode control. An internal clamp limits

the gate voltage to 12V above and a diode voltage below

IN. During fast turn-on, a 1.5A pull-up charges DGATE from

CPO. During fast turn-off, a 1.5A pull-down discharges

DGATE to IN.

D2ON: On Control Input. A voltage below 1.145V allows

the external ideal diode MOSFET in the IN2 supply path

to turn on and a voltage above 1.235V turns it off. Con-

nect this pin to an external resistive divider from IN1 to

make IN1 the higher priority input supply when IN1 and

IN2 are equal.

EN (UFD Package): Enable Input.

Ground this pin to enable

Hot Swap control. If this pin is pulled high, the MOSFET

is not allowed to turn on. A 10µA current source pulls this

pin up to a diode below INTVCC. Upon EN going low when

ON is high, an internal timer provides a 100ms start-up

delay for debounce, after which the fault is cleared.

Exposed Pad (UFD Package): Exposed pad may be left

open or connected to device ground.

FAULT (UFD Package): Fault Status Output. Open-drain

output that is normally pulled high by a 10µA current

source to a diode below INTVCC. It may be pulled above

INTVCC using an external pull-up. It pulls low when the

circuit breaker is tripped after an overcurrent fault timeout.

Leave open if unused.

GND: Device Ground.

HGATE: Hot Swap MOSFET Gate Drive Output. Connect

this pin to the gate of the external N-channel MOSFET for

Hot Swap control. An internal 10µA current source charges

the MOSFET gate. An internal clamp limits the gate volt-

age to 12V above and a diode voltage below OUT. During

turn-off, a 300µA pull-down discharges HGATE to ground.

During an output short or INTVCC undervoltage lockout, a

fast 200mA pull-down discharges HGATE to OUT.

IN1, IN2: Positive Supply Input and MOSFET Gate Drive

Return. Connect this pin to the power input side of the

external ideal diode MOSFET. The 5V INTVCC supply is

generated from IN1 and IN2 via an internal diode-OR. The

voltage sensed at this pin is used to control DGATE. The

gate fast pull-down current returns through this pin when

DGATE is discharged.

INTVCC: Internal 5V Supply Decoupling Output. This pin

must have a 0.1µF or larger capacitor. An external load of

less than 500µA can be connected at this pin.

NC (UFD Package): No Connection. Not internally

connected.

ON: On Control Input. A rising edge above 1.235V turns on

the external Hot Swap MOSFET and a falling edge below

1.155V turns it off. Connect this pin to an external resistive

divider from SENSE+ to monitor the supply undervoltage

condition. Pulling the ON pin below 0.6V resets the elec-

tronic circuit breaker.

OUT: MOSFET Gate Drive Return. Connect this pin to the

output side of the external Hot Swap MOSFET. The gate

fast pull-down current returns through this pin when

HGATE is discharged.

PWRGD: Power Status Output. Open-drain output that is

normally pulled high by a 10µA current source to a diode

below INTVCC. It may be pulled above INTVCC using an

external pull-up. It pulls low when the MOSFET gate drive

between HGATE and OUT exceeds the gate-to-source volt-

age of 4.2V. Leave open if unused.

SENSE+: Positive Current Sense Input. Connect this pin

to the diode-OR output of the external ideal diode MOS-

FETs and input of the current sense resistor. The voltage

sensed at this pin is used for monitoring the current limit

and also to control DGATE for forward voltage regulation

and reverse turn-off. This pin has an undervoltage lockout

threshold of 1.9V that will turn off the Hot Swap MOSFET.

SENSE–: Negative Current Sense Input. Connect this pin

to the output of the current sense resistor. The current

LTC4227

422712fa

For more information www.linear.com/LTC4227

block DiagraM

–

GA1

12V 12V

HGATE

OUT

CPO1

DGATE1

CPO2

DGATE2

65mV

IN1 SENSE+SENSE– IN2

10µA

–

50mV

ECB

–

25mV

HGATE ON

1.235V

0.6V

2.2V

10µA

INTVCC

CP1

25mV

–

100µA INTVCC INTVCC

100µA

–

INTVCC

–

CHARGE

PUMP 1

f = 2MHz

GATE

DRIVER

CHARGE

PUMP 2

f = 2MHz

GA2

100µA

INTVCC

2µA

INTVCC

–

FAULT RESET

CP2

CP3

–

1.235V

DGATE2 OFF

CP4

–

1.235V

0.2V

CP5

–

CP6

–

1.235V

CARD PRESENCE DETECT

LOGIC

–

D2ON

TMR

*UFD PACKAGE ONLY

EN*

10µA

UV1

GND

422712 BD

FAULT*

PWRGD

–

NC*

EXPOSED PAD*

1.9V

SENSE+

UV2

–

5V LDO

12V

limit circuit controls HGATE to limit the voltage between

SENSE+ and SENSE– to 65mV. A circuit breaker trips when

the sense voltage exceeds 50mV for more than a fault filter

delay configured at the TMR pin.

TMR: Timer Capacitor Terminal. Connect a capacitor

between this pin and ground to set a 12ms/µF duration

for current limit before the external Hot Swap MOSFET

is turned off. The duration of the off-time is 617ms/µF,

resulting in a 2% duty cycle.

pin FuncTions

LTC4227

422712fa

For more information www.linear.com/LTC4227

operaTion

The LTC4227 functions as an input supply diode-OR with

inrush current limiting and overcurrent protection by

controlling the external N-channel MOSFETs (MD1, MD2

and MH) on a supply path. This allows boards to be safely

inserted and removed in systems with a backplane powered

by redundant supplies. The LTC4227 has a single Hot Swap

controller and two separate ideal diode controllers, each

providing independent control for the two input supplies.

When the LTC4227 is first powered up, the gates of the

MOSFETs are all held low, keeping them off. As the DGATE2

pull-up can be disabled by the D2ON pin, DGATE2 will pull

high only when the D2ON pin is pulled low. The gate drive

amplifier (GA1, GA2) monitors the voltage between the

IN and SENSE+ pins and drives the respective DGATE pin.

The amplifier quickly pulls up the DGATE pin, turning on

the MOSFET for ideal diode control, when it senses a large

forward voltage drop. With the ideal diode MOSFETs acting

as an input supply diode-OR, the SENSE+ pin voltage rises

to the highest of the supplies at the IN1 and IN2 pins. The

stored charge in an external capacitor connected between

the CPO and IN pins provides the charge needed to quickly

turn on the ideal diode MOSFET. An internal charge pump

charges up this capacitor at device power-up. The DGATE

pin sources current from the CPO pin and sinks current

into the IN and GND pins.

Pulling the ON pin high and EN pin low initiates a debounce

timing cycle (100ms for LTC4227-1/LTC4227-2 and 1.6ms

for LTC4227-3/LTC4227-4). After this timing cycle, a 10µA

current source from the charge pump ramps up the HGATE

pin. When the Hot Swap MOSFET turns on, the inrush cur-

rent is limited at a level set by an external sense resistor

(RS) connected between the SENSE+ and SENSE– pins.

An active current limit amplifier (A1) servos the gate of

the MOSFET to 65mV across the current sense resistor.

Inrush current can be further reduced, if desired, by add-

ing a capacitor from HGATE to GND. When the MOSFET ’s

gate overdrive (HGATE to OUT voltage) exceeds 4.2V, the

PWRGD pin pulls low.

When the ideal diode MOSFET is turned on, the gate drive

amplifier controls DGATE to servo the forward voltage drop

(VIN – VSENSE+) across the MOSFET to 25mV . If the load

current causes more than 25mV of voltage drop, the gate

voltage rises to enhance the MOSFET. For large output

currents, the MOSFET ’s gate is driven fully on and the

voltage drop is equal to ILOAD • RDS(ON) of the MOSFET.

In the case of an input supply short-circuit when the

MOSFETs are conducting, a large reverse current starts

flowing from the load towards the input. The gate drive

amplifier detects this failure condition as soon as it ap-

pears and turns off the ideal diode MOSFET by pulling

down the DGATE pin.

In the case where an overcurrent fault occurs on the supply

output, the current is limited to 65mV/RS. After a fault filter

delay set by 100µA charging the TMR pin capacitor, the

circuit breaker trips and pulls the HGATE pin low, turning

off the Hot Swap MOSFET. The FAULT pin is latched low.

At this point, the DGATE pin continues to pull high and

keeps the ideal diode MOSFET on.

Internal clamps limit both the DGATE to IN and CPO to IN

voltages to 12V. The same clamp also limits the CPO and

DGATE pins to a diode voltage below the IN pin. Another

internal clamp limits the HGATE to OUT voltage to 12V

and also clamps the HGATE pin to a diode voltage below

the OUT pin.

Power to the LTC4227 is supplied from either the IN or

OUT pins, through an internal diode-OR circuit to a low

dropout regulator (LDO). That LDO generates a 5V supply

at the INTVCC pin and powers the LTC4227’s internal low

voltage circuitry.

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High availability systems often employ parallel-connected

power supplies or battery feeds to achieve redundancy

and enhance system reliability. Power ORing diodes are

commonly used to connect these supplies at the point of

load, but at the expense of power loss due to significant

diode forward voltage drop. The LTC4227 minimizes this

power loss by using external N-channel MOSFETs for the

pass elements, allowing for a low voltage drop from the

supply to the load when the MOSFETs are turned on (see

Figure 1). When the input source voltage drops below the

output common supply voltage, the appropriate MOSFET is

turned off, thereby matching the function and performance

of an ideal diode. By adding a current sense resistor and

a Hot Swap MOSFET after the parallel-connected ideal

diode MOSFETs, the LTC4227 enhances the ideal diode

performance with inrush current limiting and overcurrent

protection. This allows the boards to be safely inserted

and removed from a live backplane without damaging

the connector.

Internal VCC Supply

The LTC4227 can operate with input supplies from 2.9V

to 18V at the IN pins. The power supply to the device is

internally regulated at 5V by a low dropout regulator (LDO)

with an output at the INTVCC pin. An internal diode-OR

circuit selects the highest of the supplies at the IN and OUT

pins to power the device through the LDO. The diode-OR

scheme permits the device’s power to be temporarily kept

alive by the OUT load capacitance when the IN supplies

have collapsed or shut off.

An undervoltage lockout circuit prevents all of the MOSFETs

from turning on until the INTVCC voltage exceeds 2.2V. A

0.1µF capacitor is recommended between the INTVCC and

GND pins, close to the device for bypassing. No external

supply should be connected at the INTVCC pin so as not

to affect the LDO’s operation. A small external load of less

than 500µA can be connected at the INTVCC pin.

Turn-On Sequence

The board power supply at the OUT pin is controlled with

external N-channel MOSFETs (MD1, MD2 and MH). The

ideal diode MOSFETs connected in parallel on the supply

side function as a diode-OR, while MH on the load side

acts as a Hot Swap controlling the power supplied to the

output load. The sense resistor, RS, monitors the load

current for overcurrent detection. The HGATE capacitor,

CHG, controls the gate slew rate to limit the inrush current.

Resistor RHG with CHG compensates the current control

loop, while RH prevents high frequency oscillations in the

Hot Swap MOSFET.

Figure 1. Card Resident Diode-OR with Hot Swap Application

BACKPLANE

CONNECTOR

VIN1

12V

VIN2

12V

CARD

CONNECTOR

CPO1

D2ON

ON FAULT

PWRGD

680µF

12V

7.6A

20k

INTVCC

SMAJ13A

GND

IN1 DGATE1 DGATE2

LTC4227

4227 F01

MD2

SiR462DP

Si7336ADP

0.006Ω

HGATE OUTSENSE+SENSE–

CPO2

CCP2

0.1µF

IN2

137k

100k

10Ω

RHG

47Ω

CHG

15nF

CCP1

0.1µF

MD1

SiR462DP

0.1µF

10nF

SMAJ13A

TMR

LTC4227

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During a normal power-up, the ideal diode MOSFETs turn

on first. As soon as the internally generated supply, INTVCC,

rises above its 2.2V undervoltage lockout threshold, the

internal charge pump is allowed to charge up the CPO

pins. Because the ideal diode MOSFETs are connected in

parallel as a diode-OR, the SENSE+ pin voltage approaches

the highest of the supplies at the IN1 and IN2 pins. The

MOSFET associated with the lower input supply voltage

will be turned off by the corresponding gate drive amplifier.

Before the Hot Swap MOSFET can be turned on, EN must

remain low and ON must remain high for a tD(HGATE) de-

bounce timing cycle to ensure that any contact bounces

during the insertion have ceased. At the end of the debounce

cycle, the internal fault latches are cleared. The Hot Swap

MOSFET is then allowed to turn on by charging up HGATE

with a 10µA current source from the charge pump. The

voltage at the HGATE pin rises with a slope equal to 10µA/

CHG and the supply inrush current flowing into the load

capacitor, CL, is limited to:

IINRUSH =

CHG

•10µA

The OUT voltage follows the HGATE voltage when the Hot

Swap MOSFET turns on. If the voltage across the current

sense resistor, RS, becomes too high, the inrush current

will be limited by the internal current limiting circuitry. Once

the MOSFET gate overdrive exceeds 4.2V, the PWRGD pin

pulls low to indicate that the power is good. Once OUT

reaches the input supply voltage, HGATE continues to

ramp up. An internal 12V clamp limits the HGATE voltage

above OUT.

When the ideal diode MOSFET is turned on, the gate

drive amplifier controls the gate of the MOSFET to servo

the forward voltage drop across the MOSFET to 25mV.

If the load current causes more than 25mV of drop, the

MOSFET gate is driven fully on and the voltage drop is

equal to ILOAD • RDS(ON).

Turn-Off Sequence

The external MOSFETs can be turned off by a variety of

conditions. A normal turn-off for the Hot Swap MOSFET is

initiated by pulling the ON pin below its 1.155V threshold

(80mV ON pin hysteresis), or pulling the EN pin above

its 1.235V threshold. Additionally, an overcurrent fault

of sufficient duration to trip the circuit breaker also turns

off the Hot Swap MOSFET. Normally, the LTC4227 turns

off the MOSFET by pulling the HGATE pin to ground with

a 300µA current sink.

All of the MOSFETs turn off when INTVCC falls below its

undervoltage lockout threshold (2.2V). The DGATE pin is

pulled down with a 100µA current to one diode voltage

below the IN pin, while the HGATE pin is pulled down to

the OUT pin by a 200mA current. When D2ON is pulled

high above 1.235V, the ideal diode MOSFET in the IN2

supply path is turned off with DGATE2 pulled low by a

100µA current.

The gate drive amplifier controls the ideal diode MOSFET

to prevent reverse current when the input supply falls

below SENSE+. If the input supply collapses quickly, the

gate drive amplifier turns off the MOSFET with a fast pull-

down circuit as soon as it detects that IN is 25mV below

SENSE+. If the input supply falls at a more modest rate,

the gate drive amplifier controls the MOSFET to maintain

SENSE+ at 25mV below IN.

Figure 2. Ideal Diode Controller Start-Up Waveforms

Figure 3. LTC4227-1/LTC4227-2 Hot Swap Controller

Power-Up Sequence

VOLTAGE

10V/DIV

5ms/DIV 4227 F02

IN1

SENSE+

DGATE1

DGATE2

CP01

CP02

5V/DIV

HGATE

10V/DIV

OUT

10V/DIV

PWRGD

10V/DIV

50ms/DIV 4227 F03

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Board Presence Detect with EN

If ON is high when the EN pin goes low, indicating a board

presence, the LTC4227 initiates a debounce timing cycle

for contact debounce. Upon board insertion, any bounces

on the EN pin restart the timing cycle. When the debounce

timing cycle is done, the internal fault latches are cleared.

If the EN pin remains low at the end of the timing cycle,

HGATE is charged up with a 10µA current source to turn

on the Hot Swap MOSFET.

If the EN pin goes high, indicating a board removal, the

HGATE pin is pulled low with a 300µA current sink after

a 20µs delay, turning off the Hot Swap MOSFET, without

clearing any latched faults.

Overcurrent Fault

The LTC4227 features an adjustable current limit with

circuit breaker function that protects the external MOSFETs

against short circuits or excessive load current. The voltage

across the external sense resistor, RS, is monitored by an

electronic circuit breaker (ECB) and active current limit

(ACL) amplifier. The electronic circuit breaker will turn off

the Hot Swap MOSFET with a 300µA current from HGATE

to GND if the voltage across the sense resistor exceeds

∆VSENSE(CB) (50mV) for longer than the fault filter delay

configured at the TMR pin.

Active current limiting begins when the sense voltage

exceeds the ACL threshold ∆VSENSE(ACL) (65mV), which

is 1.3× the ECB threshold ∆VSENSE(CB). The gate of the

Hot Swap MOSFET is brought under control by the ACL

amplifier and the output current is regulated to maintain

the ACL threshold across the sense resistor. At this point,

the fault filter starts the timeout with a 100µA current

charging the TMR pin capacitor. If the TMR pin voltage

exceeds its threshold (1.235V), the external MOSFET

turns off with HGATE pulled to ground by 300µA, and its

associated FAULT pulls low.

After the Hot Swap MOSFET turns off, the TMR pin ca-

pacitor is discharged with a 2µA pull-down current until

its threshold reaches 0.2V. This is followed by a cool-off

period of 14 timing cycles at the TMR pin. For the latch-

off part (LTC4227-1/LTC4227-3), the HGATE pin voltage

does not restart at the end of the cool-off period, unless

the latched fault is cleared by pulling the ON pin low or

toggling the EN pin from high to low. For the auto-retry

part (LTC4227-2/LTC4227-4), the latched fault is cleared

automatically at the end of the cool-off period, and the

HGATE pin restarts charging up to turn on the MOSFET.

Figure 4 shows an overcurrent fault on the 12V output.

In the event of a severe short-circuit fault on the 12V

output as shown in Figure 5, the output current can surge

to tens of amperes. The LTC4227 responds within 1µs to

bring the current under control by pulling the HGATE to

OUT voltage down to zero volts. Almost immediately, the

gate of the Hot Swap MOSFET recovers due to the RHG

and CHG network, and current is actively limited until the

electronic circuit breaker times out. Due to parasitic sup-

ply lead inductance, an input supply without any bypass

capacitor may collapse during the high current surge and

then spike upwards when the current is interrupted. Figure 9

shows the input supply transient suppressors consisting

of Z1, RSNUB1, CSNUB1 and Z2, RSNUB2, CSNUB2 for the two

supplies if there is no input capacitance.

Figure 4. Overcurrent Fault on 12V Output

Figure 5. Severe Short-Circuit on 12V Output

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

20A/DIV

200µs/DIV 4227 F04

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

20A/DIV

2µs/DIV 4227 F05

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Active Current Loop Stability

The active current loop on the HGATE pin is compensated

by the parasitic gate capacitance of the external N-channel

MOSFET. No further compensation components are nor-

mally required. In the case when a MOSFET with CISS ≤

2nF is chosen, an RHG and CHG compensation network

connected at the HGATE pin may be required. The value

of CHG is selected based on the inrush current allowed for

the output load capacitance. The resistor, RHG, connected

in series with CHG accelerates the MOSFET gate recovery

for active current limiting after a fast gate pull-down due

to an output short. The value of CHG should be ≤100nF

and RHG should be between 10Ω and 100Ω for optimum

performance.

TMR Pin Functions

An external capacitor, CT

, connected from the TMR pin

to GND serves as fault filtering when the supply output is

in active current limit. When the voltage across the sense

resistor exceeds the circuit breaker trip threshold (50mV),

TMR pulls up with 100µA. Otherwise, it pulls down with 2µA.

The fault filter times out when the 1.235V TMR threshold

is exceeded, causing the corresponding FAULT pin to pull

low. The fault filter delay or circuit breaker time delay is:

tCB = CT • 12[ms/µF].

After the circuit breaker timeout, the TMR pin capacitor

pulls down with 2µA from the 1.235V TMR threshold

until it reaches 0.2V. Then, it completes 14 cooling cycles

consisting of the TMR pin capacitor charging to 1.235V

with a 100µA current and discharging to 0.2V with a 2µA

current. At that point, the HGATE pin voltage is allowed to

start up if the fault has been cleared as described in the

Resetting Faults section. When the latched fault is cleared

during the cool-off period, the corresponding FAULT pin

pulls high. The total cool-off time for the MOSFET after

an overcurrent fault is:

tCOOL = CT • 11[s/µF]

If the latched fault is not cleared after the cool-off period,

the cooling cycles continue until the fault is cleared.

After the cool-off period, the HGATE pin is only allowed

to pull up if the fault has been cleared for the latch-off

part. For the auto-retry part, the latched fault is cleared

automatically following the cool-off period and the HGATE

pin voltage is allowed to restart.

Resetting Faults (LTC4227-1/LTC4227-3)

For the latch-off part, an overcurrent fault is latched after

tripping the circuit breaker, and the FAULT pin is asserted

low. Only the Hot Swap MOSFET is turned off and the ideal

diode MOSFETs are not affected.

To reset a latched fault and restart the output, pull the ON

pin below 0.6V for more than 100µs and then high above

1.235V. The fault latches reset and the FAULT pin deas-

serts on the falling edge of the ON pin. When ON goes

high again, a debounce timing cycle is initiated before

the HGATE pin voltage restarts. Toggling the EN pin high

and then low again also resets a fault, but the FAULT pin

pulls high at the end of the debounce timing cycle before

the HGATE pin voltage starts up. Bringing all the supplies

below the INTVCC undervoltage lockout threshold (2.2V)

shuts off all the MOSFETs and resets all the fault latches.

A debounce timing cycle is initiated before a normal start-

up when any of the supplies is restored above the INTVCC

UVLO threshold.

Auto-Retry After a Fault (LTC4227-2/LTC4227-4)

For the auto-retry part, the latched fault is reset automati-

cally after a cool-off timing cycle as described in the TMR

Pin Functions section. At the end of the cool-off period,

the fault latch is cleared and FAULT pulls high. The HGATE

pin voltage is allowed to start up and turn on the Hot Swap

MOSFET. If the output short persists, the supply powers

up into a short with active current limiting until the cir-

cuit breaker times out and FAULT again pulls low. A new

cool-off cycle begins with TMR ramping down with a 2µA

current. The whole process repeats itself until the output

short is removed. Since tCB and tCOOL are a function of

TMR capacitance, CT,the auto-retry duty cycle is equal to

0.1%, irrespective of CT.

Figure 6 shows an auto-retry sequence after an overcur-

rent fault.

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There is a 10µs glitch filter on the ON pin to reject supply

glitches. By placing a filter capacitor, CF

, with the resis-

tive divider at the ON pin, the glitch filter delay is further

extended by the RC time constant to prevent any false fault.

Power Good Monitor

Internal circuitry monitors the MOSFET gate overdrive

between the HGATE and OUT pins. The power good sta-

tus for the supply is reported via the open-drain output,

PWRGD. It is normally pulled high by an external pull-up

resistor or the internal 10µA pull-up. The power good

output asserts low when the gate overdrive exceeds 4.2V

during the HGATE start-up. Once asserted low, the power

good status is latched and can only be cleared by pulling

the ON pin low, toggling the EN pin from low to high, or

INTVCC entering undervoltage lockout. The power good

output continues to pull low while HGATE is regulating in

active current limit, but pulls high when the circuit breaker

times out and pulls the HGATE pin low.

CPO and DGATE Start-Up

The CPO and DGATE pin voltages are initially pulled up

to a diode below the IN pin when first powered up. CPO

starts ramping up 7µs after INTVCC clears its undervolt-

age lockout level. Another 40µs later, DGATE also starts

ramping up with CPO. The CPO ramp rate is determined

by the CPO pull-up current into the combined CPO and

DGATE pin capacitances. An internal clamp limits the CPO

pin voltage to 12V above the IN pin, while the final DGATE

pin voltage is determined by the gate drive amplifier. An

internal 12V clamp limits the DGATE pin voltage above IN.

MOSFET Selection

The LTC4227 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFETs are

on-resistance, RDS(ON), the maximum drain-source volt-

age, BVDSS, and the threshold voltage.

The gate drive for the ideal diode MOSFET and Hot Swap

MOSFET is guaranteed to be greater than 5V and 4.8V

respectively when the supply voltages at IN1 and IN2 are

between 2.9V and 7V. When the supply voltages at IN1

and IN2 are greater than 7V, the gate drive is guaranteed

Figure 6. Auto-Retry Sequence After a Fault

Supply Undervoltage Monitor

The ON pin functions as a turn-on control and an input

supply monitor. A resistive divider connected between

the supply diode-OR output (SENSE+) and GND at the

ON pin monitors the supply undervoltage condition. The

undervoltage threshold is set by proper selection of the

resistors, and is given by:

VIN(UVTH) =1+R2









•VON(TH)

where VON(TH) is the ON rising threshold (1.235V).

An undervoltage fault occurs if the diode-OR output supply

falls below its undervoltage threshold for longer than 20µs.

The FAULT pin will not be pulled low. If the ON pin voltage

falls below 1.155V but remains above 0.6V, the Hot Swap

MOSFET is turned off by a 300µA pull-down from HGATE

to ground. The Hot Swap MOSFET turns back on instantly

without the debounce timing cycle when the diode-OR

output supply rises above its undervoltage threshold.

However, if the ON pin voltage drops below 0.6V, it turns

off the Hot Swap MOSFET and clears the fault latches. The

Hot Swap MOSFET turns back on only after a debounce

timing cycle when the diode-OR output supply is restored

above its undervoltage threshold. The ideal diode MOSFETs

are not affected by the undervoltage fault conditions.

If both IN supplies fall until the internally generated sup-

ply, INTVCC, drops below its 2.2V UVLO threshold, all the

MOSFETs are turned off and the fault latches are cleared.

Operation resumes from a fresh start-up cycle when the

input supplies are restored and INTVCC exceeds its UVLO

threshold.

TMR

1V/DIV

HGATE

5V/DIV

FAULT

10V/DIV

ILOAD

10A/DIV

100ms/DIV 4227 F06

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to be greater than 10V. The gate drive is limited to not

more than 14V. This allows the use of logic-level threshold

N-channel MOSFETs and standard N-channel MOSFETs

above 7V. An external Zener diode can be used to clamp

the potential from the MOSFET ’s gate to source if the rated

breakdown voltage is less than 14V.

The maximum allowable drain-source voltage, BVDSS,

must be higher than the supply voltages as the full sup-

ply voltage can appear across the MOSFET. If an input or

output is connected to ground, the full supply voltage will

appear across the MOSFET. The RDS(ON) should be small

enough to conduct the maximum load current, and also

stay within the MOSFET’s power rating.

CPO Capacitor Selection

The recommended value of the capacitor, CCP

, between

the CPO and IN pins is approximately 10× the input capaci-

tance, CISS, of the ideal diode MOSFET. A larger capacitor

takes a correspondingly longer time to charge up by the

internal charge pump. A smaller capacitor suffers more

voltage drop during a fast gate turn-on event as it shares

charge with the MOSFET gate capacitance.

Supply Transient Protection

When the capacitances at the input and output are very

small, rapid changes in current during an input or output

short-circuit event can cause transients that exceed the

24V absolute maximum ratings of the IN and OUT pins.

To minimize such spikes, use wider traces or heavier

trace plating to reduce the power trace inductance. Also,

bypass locally with a 10µF electrolytic and 0.1µF ceramic,

or alternatively clamp the input with a transient voltage

suppressor (Z1, Z2). A 10Ω, 0.1µF snubber damps the

response and eliminates ringing (See Figure 9).

Design Example

As a design example for selecting components, consider

a 12V system with a 7.6A maximum load current for the

two supplies (see Figure 1).

First, select the appropriate value of the current sense re-

sistor, RS, for the 12V supply. Calculate the sense resistor

value based on the maximum load current and the lower

limit for the circuit breaker threshold, ∆VSENSE(CB)(MIN):

RS=

∆V

SENSE(CB)(MIN)

ILOAD(MAX)

=47.5mV

7.6A =6.25mΩ

Choose a 6mΩ sense resistor with a 1% tolerance. The

minimum and maximum circuit breaker trip current is

calculated as follows:

ITRIP(MIN) =

∆V

SENSE(CB)(MIN)

RS(MAX)

=47.5mV

6.06mΩ=7.8A

ITRIP(MAX) =∆VSENSE(CB)(MAX)

RS(MIN)

=52.5mV

5.94mΩ=8.8A

For proper operation, ITRIP(MIN) must exceed the maximum

load current with margin, so RS = 6mΩ should suffice for

the 12V supply.

Next, calculate the RDS(ON) of the ideal diode MOSFET to

achieve the desired forward drop at maximum load. Assum-

ing a forward drop, ∆VFWD of 60mV across the MOSFET :

RDS(ON) ≤

∆V

FWD

ILOAD(MAX)

60mV

7.6A =7.9mΩ

The SiR462DP offers a good choice with a maximum

RDS(ON) of 7.9mΩ at VGS = 10V. The input capacitance,

CISS, of the SiR462DP is about 1155pF. Slightly exceeding

the 10× recommendation, a 0.1µF capacitor is selected for

CCP1 and CCP2 at the CPO pins.

Next, verify that the thermal ratings of the selected Hot

Swap MOSFET, Si7336ADP, are not exceeded during

power-up or an output short.

Assuming the MOSFET dissipates power due to inrush

current charging the load capacitor, CL, at power-up, the

energy dissipated in the MOSFET is the same as the energy

stored in the load capacitor, and is given by:

ECL =

•CL•V

IN2

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For CL = 680µF, the time it takes to charge up CL is cal-

culated as:

tCHARGE =

•V

INRUSH

680µF •12V

0.5A =16ms

The inrush current is set to 0.5A by adding capacitance,

CHG, at the gate of the Hot Swap MOSFET.

CHG =

•I

HGATE(UP)

INRUSH

=680µF •10µA

0.5A ≅15nF

The average power dissipated in the MOSFET is calculated

as:

PAVG =ECL

CHARGE

2•680µF •12V

( )

16ms =3W

The MOSFET selected must be able to tolerate 3W for

16ms during power-up. The SOA curves of the Si7336ADP

provide for 1.5A at 30V (45W) for 100ms. This is suffi-

cient to satisfy the requirement. The increase in junction

temperature due to the power dissipated in the MOSFET

is ∆T = PAVG • ZthJC where ZthJC is the junction-to-case

thermal impedance. Under this condition, the Si7336ADP

data sheet indicates that the junction temperature will

increase by 2.4°C using ZthJC = 0.8°C/W (single pulse).

The duration and magnitude of the power pulse during

an output short is a function of the TMR capacitance, CT

and the LTC4227’s active current limit. The short-circuit

duration is given as CT • 12[ms/µF] = 1.2ms for CT = 0.1µF.

The maximum short-circuit current is calculated using the

maximum active current limit threshold, ∆VSENSE(ACL)(MAX)

and minimum RS value.

SHORT(MAX) =

∆V

SENSE(ACL)(MAX)

RS(MIN)

=70mV

5.94mΩ=11.8A

So, the maximum power dissipated in the MOSFET is

11.8A • 12V = 142W for 1.2ms. The Si7336ADP data

sheet indicates that the worst-case increase in junc-

tion temperature during this short-circuit condition is

21.3°C using ZthJC = 0.15°C/W (single pulse). Choosing

CT = 0.1µF will not cause the maximum junction tempera-

ture of the MOSFET to be exceeded. The SOA curves of

the Si7336ADP provide for 6A at 30V (180W) for 10ms.

This also satisfies the requirement.

Next, select the resistive divider at the ON pin to provide

an undervoltage threshold of 9.6V for the 12V supply at

SENSE+. First, choose the bottom resistor, R1, to be 20k.

Then, calculate the top resistor value for R2:

R2 =V

IN(UVTH)

VON(TH)

– 1









•R1

R2 =9.6V

1.235V – 1









•20k =135k

Choose the nearest 1% resistor value of 137k for R2. In

addition, there is a 0.1µF bypass, C1, at the INTVCC pin

and a 10nF filter capacitor, CF

, at the ON pin to prevent the

supply glitches from turning off the Hot Swap MOSFET.

PCB Layout Considerations

For proper operation of the LTC4227’s circuit breaker,

Kelvin connection to the sense resistor is strongly rec-

ommended. The PCB layout should be balanced and

symmetrical to minimize wiring errors. In addition, the

PCB layout for the sense resistor and the power MOSFET

should include good thermal management techniques for

optimal device power dissipation. A recommended PCB

layout is illustrated in Figure 7.

Connect the IN and OUT pin traces as close as possible to

the MOSFET s’ terminals. Keep the traces to the MOSFETs

wide and short to minimize resistive losses. The PCB traces

associated with the power path through the MOSFETs

should have low resistance. The suggested trace width for

1oz copper foil is 0.03" for each ampere of DC current to

keep PCB trace resistance, voltage drop and temperature

rise to a minimum. Note that the sheet resistance of 1oz

copper foil is approximately 0.5mΩ/square, and voltage

drops due to trace resistance add up quickly in high cur-

rent applications.

It is also important to place the bypass capacitor, C1, for

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the INTVCC pin, as close as possible between INTVCC and

GND. Also place CCP1 near the CPO1 and IN1 pins, and

CCP2 near the CPO2 and IN2 pins. The transient voltage

suppressors, Z1 and Z2, when used, should be mounted

close to the LTC4227 using short lead lengths.

Prioritizing Supplies with D2ON

Figure 8 shows a diode-OR application where a resistive

divider connected from IN1 at the D2ON pin can suppress

the turn-on of the ideal diode MOSFET, MD2, in the IN2

supply path. When the IN1 supply voltage falls below 2.8V,

it allows the ideal diode MOSFET, MD2, to turn on, causing

the diode-OR output to be switched from the main 3.3V

supply at IN1 to the auxiliary 3.3V supply at IN2. This

configuration permits the load to be supplied from a lower

IN1 supply as compared to IN2 until IN1 falls below the

MD2 turn-on threshold. The threshold value used should

not allow the IN1 supply to be operated at more than one

diode voltage below IN2. Otherwise, MD2 conducts through

the MOSFET ’s body diode. The resistive divider connected

from SENSE+ at the ON pin provides the undervoltage

threshold of 2.6V for the diode-OR output supply.

D G

D S

S D

G D

S D

G D

•••

•

• •

•

•••

PowerPAK SO-8

MD1

PowerPAK SO-8

MD2

PowerPAK SO-8

WIN1

VIA TO IN1

CURRENT FLOW

TO LOAD

CCP2

4227 F07

20 19 18 17

8 9 10

LTC4227UFD

CCP1

OUT

WIN2

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03" PER AMPERE

ON 1oz Cu FOIL

VIA TO CPO1

VIA TO DGATE2

VIA TO GND PLANE

VIA TO DGATE1

Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor

LTC4227

422712fa

For more information www.linear.com/LTC4227

applicaTions inForMaTion

BACKPLANE

CONNECTOR

VMAIN

3.3V

VAUX

3.3V

CARD

CONNECTOR

CPO1

D2ON

ON FAULT

PWRGD

100µF

3.3V

INTVCC

SMAJ7A

GND

IN1 DGATE1 DGATE2

LTC4227

4227 F08

MD2

SiR462DP

Si7336ADP

0.008Ω

HGATE OUTSENSE+SENSE–

CPO2

CCP2

0.1µF

IN2

10k

20k

28.7k

CCP1

0.1µF

MD1

SiR462DP

0.1µF

CF1

0.1µF

SMAJ7A

TMR

CF2

10nF

20k

22.1k

BACKPLANE

CONNECTOR

VIN1

VIN2

CARD

CONNECTOR

CPO1

ON FAULT

PWRGD

100µF

10A

INTVCC

SMAJ13A

GND D1: GREEN LED LN1351C

D2: RED LED LN1261CAL

IN1 DGATE1 DGATE2

LTC4227

4227 F09

MD2

SiR462DP

Si7336ADP

0.004Ω

HGATE OUTSENSE+SENSE–

CPO2

CCP2

0.1µF

IN2

2.7k

CCP1

0.1µF

CSNUB1

0.1µF

MD1

SiR462DP

PWREN

47nF

0.1µF

SMAJ13A

TMRD2ON

RSNUB1

10Ω

CSNUB2

0.1µF

RSNUB2

10Ω

10k

Figure 8. Plug-In Card IN1 Supply Controls the IN2 Supply Turn-On Via D2ON Pin

Figure 9. 5V, 10A Card Resident Application

LTC4227

422712fa

For more information www.linear.com/LTC4227

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

4.00 ±0.10

(2 SIDES)

1.50 REF

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

19 20

BOTTOM VIEW—EXPOSED PAD

2.50 REF

0.75 ±0.05

R = 0.115

TYP

PIN 1 NOTCH

R = 0.20 OR

C = 0.35

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UFD20) QFN 0506 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

2.65 ±0.05

2.50 REF

4.10 ±0.05

5.50 ±0.05

1.50 REF

3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

R = 0.05 TYP

2.65 ±0.10

3.65 ±0.10

3.65 ±0.05

0.50 BSC

UFD Package

20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

LTC4227

422712fa

For more information www.linear.com/LTC4227

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN16 (SSOP) 0204

1 2 345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC4227

422712fa

For more information www.linear.com/LTC4227

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 07/13 Added LTC4227-3, LTC4227-4 information Multiple

Added specification: VD2ON(L,TH), D2ON Pin Low Threshold 4

Changed ∆VD2ON(HYST) typical value from 80mV to 90mV 4

Added two curves to G01; Added Diode and Hot Swap Gate Voltage vs IN Voltage graphs 5, 6

LTC4227

422712fa

For more information www.linear.com/LTC4227

LT 0713 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4227

relaTeD parTs

Typical applicaTion

Backplane Resident Diode-OR Application with Inrush Current Limiting at 12V Supply Inputs

BACKPLANE

VIN1

12V

VIN2

12V

PLUG-IN

CARD

CPO1

D2ON

ON FAULT

PWRGD

1000µF

12V

20k

INTVCC GND

IN1 DGATE1 DGATE2

LTC4227

422712 TA02

MD2

Si7336ADP

0.008Ω

HGATE OUTSENSE+SENSE–

CPO2

CCP2

0.1µF

IN2

137k

10Ω

RHG

47Ω

CHG

15nF

CCP1

0.1µF

TMR

0.1µF

MD1

Si7336ADP

10nF

BULK

SUPPLY

BYPASS

CAPACITOR

BULK

SUPPLY

BYPASS

CAPACITOR

PART NUMBER DESCRIPTION COMMENTS

LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

LTC4211 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10

LTC4215 Single Channel, Hot Swap Controller Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24

LTC4216 Single Channel, Hot Swap Controller Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12

LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16

LTC4221 Dual Channel, Hot Swap Controller Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16

LTC4222 Dual Channel, Hot Swap Controller Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32

LTC4223 Dual Supply Hot Swap Controller Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16

LTC4224 Dual Channel, Hot Swap Controller Operates from 2.7V to 6V, Active Current Limiting, MSOP-10 or DFN-10

LTC4226 Wide Operating Range Dual Hot Swap Controller Operates from 4.5V to 44V, Controls Tw o N-Channels, MSOP-16 or QFN-16

LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, Controls Four N-Channels, SSOP-28 or QFN-28

LTC4352 Low Voltage Ideal Diode Controller Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12

LTC4354 Negative Voltage Diode-OR Controller and Monitor 80V Operation, Controls Tw o N-Channels, SO-8 or DFN-8

LTC4355 Positive High Voltage Ideal Diode-OR and Monitor Operates from 9V to 80V, Controls Tw o N-Channels, S0-16 or DFN-14

LTC4357 Positive High Voltage Ideal Diode Controller Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6

LTC4358 5A Ideal Diode Operates from 9V to 26.5V, On-Chip N-Channel, TSSOP-16 or DFN-14