©2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.1
Features
•5V ±1% Reference
• Oscillator Sync Terminal
• Internal Soft Start
• Deadtime Control
• Und e r Voltage Lo ck out
Description
The KA3525A is a monolithic integrated circuit that
includes all of the control circuits necessary for a pulse width
modulating regulator. There are a voltage reference, an error
amplifier , a pulse width modulator, an oscillator, an under
voltage lockout, a soft start circuit, and the output driver in
the chip.
16-DIP
1
Internal Block Diagram
16
15
12
1
2
9
8
10 5
7
364
14
11
13
U.V.L.O.
BAND GAP
REF 5V
LATCH
SR
F/F Q
Q
5K
VC
OUTPUT A
OUTPUT B
OSCILLATOR
DISCHARGE
5K
ERR
AMP
PWM
COMP
_
+
_
+
CT
VREF
VCC
GND
EA(-)
EA(+)
EAOUT
C
(SOFT
START)
SHUT DOWN
SYNC RTOSC
OUTPUT
KA3525A
SMPS Controller
KA3525A
2
Absolute Maximum Ratings
Electrical Characteristics
(VCC = 20V, TA = 0 to +70°C, unless otherwise specified)
Parameter Symbol Value Unit
Supply Voltage VCC 40 V
Collector Supply Voltage VC40 V
Output Current, Sink or Source IO500 mA
Reference Output Current IREF 50 mA
Oscillator Charging Current ICHG(OSC) 5mA
Power Dissipation (TA = 25°C) PD1000 m/W
Operating Temperature TOPR 0 ~ +70 °C
Storage Temperature TSTG -65 ~ +150 °C
Lead Temperature (Soldering, 10sec) TLEAD +300 °C
Parameter Symbol Conditions Min. Typ. Max. Unit
REFERENCE SECTION
Reference Output Voltage VREF TJ = 25°C5.05.15.2V
Line Regulation ∆VREF VCC = 8 to 35V - 9 20 mV
Load Regulation ∆VREF IREF = 0 to 20mA - 20 50 mV
Short Circuit Output Current ISC VREF = 0, TJ = 25°C - 80 100 mA
Total Output Variation (Note1) ∆VREF Line, Load and Temperature 4.95 - 5.25 V
Temperature Stability (Note1) STT--2050mV
Long Term Stability (Note1) ST TJ = 125°C ,1KHRS-2050mV
OSCILLATOR SECTION
Initial Accuracy (Note1, 2) ACCUR TJ = 25°C-±3±6%
Frequency Change With Voltage ∆f/∆VCC VCC = 8 to 35V (Note1, 2) - ±0.8 ±2%
Maximum Frequency f(MAX) RT = 2kΩ, CT = 470pF 400 430 - kHz
Minimum Frequency f(MIN) RT = 200kΩ, CT = 0.1uF - 60 120 Hz
Clock Amplitude (Note1, 2) V(CLK) -34-V
Clock Width (Note1, 2) tW(CLK) TJ = 25°C0.30.61µs
Sync Threshold VTH(SYNC) -1.2 2 2.8 V
Sync Input Current II(SYNC) Sync = 3.5V - 1.3 2.5 mA
KA3525A
3
Electrical Characteristics (Continued)
(VCC = 20V, TA = 0 to +70°C, unless otherwise specified)
Note :
1. These parameters. although guaranteed over the recommended operating conditions, are not 100% tested in production
2. Te sted at fOSC=40kHz (RT =3.6K, CT =0.01uF, RI = 0Ω)
Parameter Symbol Conditions Min. Typ. Max. Unit
ERROR AMPLIFIER SECTION (VCM = 5.1V)
Input Offset Voltage VIO --1.510mV
Input Bias Current IBIAS --110µA
Input Offset Current IIO --0.11µA
Open Loop Voltage Gain GVO RL ≥ 10MΩ60 80 - dB
Common Mode Rejection Ratio CMRR VCM = 1.5 to 5.2V 60 90 - dB
Power Supply Rejection Ratio PSRR VCC = 8 to 3.5V 50 60 - dB
PWM COMPARATOR SECTION
Minimum Duty Cycle D(MIN) ---0%
Maximum Duty Cycle D(MAX) -45 49 - %
Input Threshold Voltage (Note2) VTH1 Zero Duty Cycle 0.7 0.9 - V
Input Threshold Voltage (Note2) VTH2 Max Duty Cycle - 3.2 3.6 V
SOFT-START SECTION
Soft Start Current ISOFT VSD = 0V, VSS = 0V 25 51 80 µA
Soft Start Low Level Voltage VSL VSD = 25V - 0.3 0.7 V
Shutdown Threshold Voltage VTH(SD) -0.9 1.3 1.7 V
Shutdown Input Current IN(SD) VSD = 2.5V - 0.3 1 mA
OUTPUT SECTION
Low Output Voltage I VOL I ISINK = 20mA - 0.1 0.4 V
Low Output Voltage II VOL II ISINK = 100mA - 0.05 2 V
High Output Voltage I VCH I ISOURCE = 20mA 18 19 - V
High Output Voltage II VCH II ISOURCE = 100mA 17 18 - V
Under Voltage Lockout VUV V8 and V9 = High 678V
Collector Leakage Current ILKG VCC = 35V - 8 0 200 µA
Rise Time (Note1) tRCL = 1uF, TJ = 25°C - 80 600 ns
Fall Time (Note1) tFCL = 1uF, TJ = 25°C - 70 300 ns
STANDBY CURRENT
Supply Current ICC VCC = 35V - 12 20 mA
KA3525A
4
Test Circuit
16
15
12
1
2
9
8
10
57
13
11
14
36
BAND GAP
REF 5V U.V.L.O.
A
B
0.1
Vcc 0.1
3k
RWM
ADJ
10k
1.5K
10K
0.01
5.0uF
5.0k
5.0k 5.0k
100
F/F
ERR
AMP ERR
AMP
OSCILLATOR
LATCH
SS R
SOFT START +
SHUTDOWN
VREF
CT
RAMP
0.009 0.1
+
3.6k
0.001
DEAD
TIME
OUT B
10k
10k
OUT A
VC
CLOCK
_
++
_
RT
KA3525A
5
Mechanical Dimensions
Package
#1
#8 #9
#16
6.40
±0.20
7.62
0.300
2.54
0.100
0.252
±0.008
0~15°
0.25
+0.10
–0.05
0.010
+0.004
–0.002
3.30
±0.30
0.130
±0.012
3.25
±0.20
0.128
±0.008
19.40
±0.20
0.764
±0.008
19.80
0.780 MAX
5.08
0.200
0.38
0.014
MAX
MIN
0.81
0.032
()
0.46
±0.10
0.018
±0.004
0.059
±0.004
1.50
±0.10
16-DIP
KA3525A
10/2/02 0.0m 001
Stock#DSxxxxxxxx
2002 Fairchild Semicond uctor Corporation
LIFE SU PP ORT POL ICY
FAIRCHILD’S PRODUCTS AR E NOT AUTHORIZED FOR USE AS C RITICAL COMPONENTS I N LIFE S UPPORT DEVICE S
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORA TION. As used he rein :
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or syst em who se failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effec tiv ene ss.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRO DUCTS HEREIN TO IMPROVE RELIABILITY, FUN C TION OR DESIGN . FAIRCHILD DO ES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Product Number Package Operating Temperature
KA3525A 16-DIP 0 ~ +70°C
