T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
1
Description
The TS256MSQ64V6U-I is a 256M x 64bits DDR2-667
2Rank SO-DIMM. The TS256MSQ64V6U-I consists of
16pcs 128Mx8bits DDR2 SDRAMs in FBGA packages
and a 2048 bits serial EEPROM on a 200-pin printed
circuit board. The TS256MSQ64V6U-I is a Dual In-Line
Memory Module and is intended for mounting into 200-pin
edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
Operating Temperature : -40C to +85C
Gold plating of PCB gold finger is 30u
RoHS compliant products.
JEDEC standard 1.8V ± 0.1V Power supply
VDDQ=1.8V ± 0.1V
Max clock Freq: 333MHZ; 667Mb/s/Pin.
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency :0, 1, 2, 3 and 4
Write Latency (WL) = Read Latency (RL)-1
Burst Length: 4,8(Interleave/nibble sequential)
Programmable sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
Off-Chip Driver (OCD) Impedance Adjustment
MRS cycle with address key programs.
On Die Termination
Serial presence detect with EEPROM
Placement
AB
D
E
C
F
G
H
I
J
K
PCB: 09-2166
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2
25
5
56
6
6M
M
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Q6
6
64
4
4V
V
V6
6
6U
U
U-
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-I
I
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200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
2
Dimensions
Side
Millimeters
Inches
A
67.60.15
2.6610.006
B
63.6
2.503
C
11.4
0.449000
D
47.4
1.866
E
4.2
0.1650
F
2.150.15
0.0850.006
G
6
0.236
H
18
0.709
I
4
0.157
J
30
1.181
K
1.00.075
0.0390.003
(Refer Placement)
Pin Identification
Symbol
A0~A13, BA0~BA2
DQ0~DQ63
DQS0~DQS7
/DQS0~/DQS7
CK0, /CK0
CK1, /CK1
CKE0, CKE1
ODT0, ODT1
/CS0, /CS1
/RAS
/CAS
/WE
DM0~DM7
VDD
VDDQ
VREF
VDDSPD
SA0~SA2
SCL
SDA
VSS
NC
T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
3
Pinouts:
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
01
VREF
69
NC
137
DQ35
02
VSS
70
DQS3
138
VSS
03
VSS
71
VSS
139
VSS
04
DQ4
72
VSS
140
DQ44
05
DQ0
73
DQ26
141
DQ40
06
DQ5
74
DQ30
142
DQ45
07
DQ1
75
DQ27
143
DQ41
08
VSS
76
DQ31
144
VSS
09
VSS
77
VSS
145
VSS
10
DM0
78
VSS
146
/DQS5
11
/DQS0
79
CKE0
147
DM5
12
VSS
80
*CKE1
148
DQS5
13
DQS0
81
VDD
149
VSS
14
DQ6
82
VDD
150
VSS
15
VSS
83
*/CS2
151
DQ42
16
DQ7
84
*A15
152
DQ46
17
DQ2
85
*BA2
153
DQ43
18
VSS
86
*A14
154
DQ47
19
DQ3
87
VDD
155
VSS
20
DQ12
88
VDD
156
VSS
21
VSS
89
A12
157
DQ48
22
DQ13
90
A11
158
DQ52
23
DQ8
91
A9
159
DQ49
24
VSS
92
A7
160
DQ53
25
DQ9
93
A8
161
VSS
26
DM1
94
A6
162
VSS
27
VSS
95
VDD
163
NC, TEST
28
VSS
96
VDD
164
CK1
29
/DQS1
97
A5
165
VSS
30
CK0
98
A4
166
/CK1
31
DQS1
99
A3
167
/DQS6
32
/CK0
100
A2
168
VSS
33
VSS
101
A1
169
DQS6
34
VSS
102
A0
170
DM6
35
DQ10
103
VDD
171
VSS
36
DQ14
104
VDD
172
VSS
37
DQ11
105
A10/AP
173
DQ50
38
DQ15
106
BA1
174
DQ54
39
VSS
107
BA0
175
DQ51
40
VSS
108
/RAS
176
DQ55
41
VSS
109
/WE
177
VSS
42
VSS
110
/CS0
178
VSS
43
DQ16
111
VDD
179
DQ56
44
DQ20
112
VDD
180
DQ60
45
DQ17
113
/CAS
181
DQ57
46
DQ21
114
ODT0
182
DQ61
47
VSS
115
*/CS1
183
VSS
48
VSS
116
*A13
184
VSS
49
/DQS2
117
VDD
185
DM7
50
NC
118
VDD
186
/DQS7
51
DQS2
119
*ODT1
187
VSS
52
DM2
120
*/CS3
188
DQS7
53
VSS
121
VSS
189
DQ58
54
VSS
122
VSS
190
VSS
55
DQ18
123
DQ32
191
DQ59
56
DQ22
124
DQ36
192
DQ62
57
DQ19
125
DQ33
193
VSS
58
DQ23
126
DQ37
194
DQ63
59
VSS
127
VSS
195
SDA
60
VSS
128
VSS
196
VSS
61
DQ24
129
/DQS4
197
SCL
62
DQ28
130
DM4
198
SA0
63
DQ25
131
DQS4
199
VDDSPD
64
DQ29
132
VSS
200
SA1
65
VSS
133
VSS
66
VSS
134
DQ38
67
DM3
135
DQ34
68
/DQS3
136
DQ39
* Please refer Block Diagram
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S2
2
25
5
56
6
6M
M
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SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
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-I
I
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200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
4
Block Diagram
DQ S0
DM0
/DQS0
/C S0
/C S1
DM /CS DQS /DQS
U1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S1
DM1
/DQS1
DM /CS DQS /DQS
U3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S2
DM2
/DQS2
DM /CS DQS /DQS
U5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U13
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S3
DM3
/DQS3
DM /CS DQS /DQS
U7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S4
DM4
/DQS4
DM /CS DQS /DQS
U2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U10
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S5
DM5
/DQS5
DM /CS DQS /DQS
U4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S6
DM6
/DQS6
DM /CS DQS /DQS
U6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ S7
DM7
/DQS7
DM /CS DQS /DQS
U8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
U16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
VDDSPD
VDD/VDDQ
VREF
VSS
EEPROM
U1~U16
U1~U16
U1~U16
SDA
SCL
SA0 SA1
EEPROM
CK0,/CK0
A0~A13
BA0~BA2
CKE0
CKE1
/RAS
/CAS
/WE
ODT0
ODT1
U1~U16
U1~U16
U1~U8
U9~U16
U1~U16
U1~U16
U1~U16
U1~U8
U9~U16
CK1,/CK1
U1~U4
Note:
1.DQ,DM,DQS & /DQS resistors :22 Ohms±5%
2.Bx,Ax,CKEx,ODTx,CSx,/RAS,
/CAS&/WEresistors :3 Ohms±5%
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
A0 A1 A2
U9~U12
U5~U8
U13~U16
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
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T
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S
S2
2
25
5
56
6
6M
M
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Q
Q6
6
64
4
4V
V
V6
6
6U
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U-
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-I
I
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200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
5
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Notes
Voltage on VDD relative to Vss
VDD
-1.0 ~ 2.3
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.5 ~ 2.3
V
1
Voltage on VDDL pin relative to Vss
VDDL
-0.5 ~ 2.3
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 2.3
V
1
Storage temperature
TSTG
-55~+100
C
1,2
Note:
1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.8)
Parameter
Symbol
Rating
Unit
Notes
Min
Typ.
Max
Supply voltage
VDD
1.7
1.8
1.9
V
Supply voltage for DLL
VDDL
1.7
1.8
1.9
V
4
Supply voltage for Output
VDDQ
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
V
1,2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
DC Input logic high
VIH(DC)
VREF+0.125
-
VDDQ+0.3
V
DC Input logic low
VIL(DC)
-0.3
-
VREF-0.125
V
Note:
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all
conditions VDDQ must be less than or equal to VDD.
1.The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track
variations in VDDQ.
2.Peak to peak AC noise on VREF may not exceed +/-2% VREF (DC).
3.VTT of transmitting device must track VREF of receiving device.
4.AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Note
Operating Temperature
TOPER
-40 to 85
C
1,2
Note:
1. Operating Temperature is the ambient temperature.
2. At -40 - 85C, operation temperature range are the temperature which all DRAM specification will be
supported.
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S2
2
25
5
56
6
6M
M
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Q6
6
64
4
4V
V
V6
6
6U
U
U-
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-I
I
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200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
6
IDD Specification parameters Definition
( IDD values are for full operating range of voltage and Temperature)
Parameter
Symbol
Max.
Unit
Note
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0
536
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
IDD1
576
mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P
160
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2Q
320
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
384
mA
Active power - down current; All banks open; tCK
= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0mA
IDD3P-F
352
mA
Slow PDN Exit MRS(12) = 1mA
IDD3P-S
320
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD3N
472
mA
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
IDD4R
752
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING IDD4R
IDD4W
712
mA
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD5
992
mA
Self refresh current; CK and CK\ at 0V; CKE ≒ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6
160
mA
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during Deselects; Data pattern is same
as IDD4R; Refer to the following page for detailed timing conditions
IDD7
1,352
mA
Note:
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading capacitor.
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S2
2
25
5
56
6
6M
M
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Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
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-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
7
Input AC Logic Level
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.200
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
VREF - 0.200
V
AC Input Test Condition
Condition
Symbol
Value
Unit
Note
Input reference voltage
VREF
0.5*VDDQ
V
1
Input signal maximum peak to peak swing
VSWING(MAX)
1.0
V
1
Input signal minimum slew rate
SLEW
1.0
V/ns
2,3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising
edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions
and VIH(AC) to VIL(AC) on the negative transitions.
V
SWING(MAX)
delta TF delta TR
VDD
V
IH
(AC)
min
V
IH
(DC)
min
VREF
V
IL
(DC)
max
V
IL
(AC)
max
VSS
Falling Slew= VREF -V IL (AC) max
delta TF Rising Slew= VIH (AC) min- VREF
delta TR
AC Input Test Signal Waveform
Input/Output Capacitance (VDD = 1.8V, VDDQ = 1.8V, TA = 25C)
Parameter
Symbol
Min
Max
Unit
Input capacitance (CK0 and /CK0)
Input capacitance (CK1 and /CK1)
Input capacitance (CKE and /CS)
Input capacitance (A0~A13, BA0~BA2, /RAS, /CAS, /WE)
Input capacitance (DQ, DM, DQS, /DQS)
CCK0
CCK1
CI1
CI2
CIO
-
-
-
-
-
48
48
42
42
9
pF
pF
pF
pF
pF
Note:
DM is internally loaded to match DQ and DQS identically.
T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
8
Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter
Symbol
Min
Max
Unit
Note
DQ output access time from CK & /CK
tAC
-450
+450
ps
DQS output access time from CK & /CK
tDQSCK
-400
+400
ps
CK high-level width
tCH
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
tCK
CK half period
tHP
min(tCL,tCH)
X
ps
Clock cycle time, CL=x
tCK
3000
8000
ps
DQ and DM input hold time
tDH
175
x
ps
DQ and DM input setup time
tDS
100
X
ps
Control & Address input pulse width for each input
tIPW
0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
X
tCK
Data-out high-impedance time from CK/CK
tHZ
X
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
TAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
X
240
ps
DQ hold skew factor
tQHS
X
340
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
X
ps
Write command to first DQS latching transition
tDQSS
-0.25
+0.25
tCK
DQS input high pulse width
tDQSH
0.35
X
tCK
DQS input low pulse width
tDQSL
0.35
X
tCK
DQS falling edge to CK setup time
tDSS
0.2
X
tCK
DQS falling edge hold time from CK
tDSH
0.2
X
tCK
Mode register set command cycle time
tMRD
2
X
tCK
Write postamble
tWPST
0.4
0.6
tCK
Write preamble
tWPRE
0.35
X
tCK
Address and control input hold time
tIH
275
X
ps
Address and control input setup time
tIS
200
X
ps
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
tCK
Active to active command period for 1KB page size
products
tRRD
7.5
X
ns
Active to active command period for 2KB page size
products
tRRD
10
X
ns
Four Activate Window for 1KB page size products
tFAW
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
ns
T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
9
/CAS to /CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
X
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
X
tCK
Internal write to read command delay
tWTR
7.5
X
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read command
tXP
2
X
tCK
Exit active power down to read command
tXARD
2
X
tCK
Exit active power down to read command (Slow exit,
Lower power)
tXARDS
7 - AL
tCK
CKE minimum pulse width (high and low pulse width)
tCKE
3
tCK
ODT turn-on delay
tAOND
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+0.7
ns
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+2
2tCK+
tAC(max)+1
ns
ODT turn-off delay
tAOFD
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
2.5tCK+
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK+tIH
ns
T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
10
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
# of Serial PD Bytes written during module production
128bytes
80
1
Total # of Bytes of S.P.D Memory Device
256bytes
08
2
Fundamental Memory Type
DDR2 SDRAM
08
3
# of Row Addresses on this Assembly
14
0E
4
# of Column Addresses on this Assembly
10
0A
5
# of Module Rows on this Assembly
2 ROW, Planar,
30.0mm
61
6
Data Width of this Assembly
64bits
40
7
Reserved
-
00
8
VDDQ and Interface Standard of this Assembly
SSTL 1.8V
05
9
DDR2 SDRAM cycle time at Max. Supported CAS
latency=X
3.00ns
30
10
DDR2 SDRAM Access time from clock at CL=X
±0.45ns
45
11
DIMM configuration type (non-parity, Parity, ECC)
Non ECC
00
12
Refresh Rate
7.8us
82
13
Primary DDR2 SDRAM Width
X8
08
14
Error Checking DDR2 SDRAM Width
N/A
00
15
Reserved
-
00
16
DDR2 SDRAM device attributes: Burst lengths
supported
4,8
0C
17
DDR2 SDRAM device attributes: # of banks on each
DDR2 SDRAM device
8 banks
08
18
DDR2 SDRAM device attributes:CAS Latency
supported
5,4,3
38
19
DIMM Mechanical Characteristics
X=<3.80
01
20
DIMM type information
SODIMM
04
21
DDR2 SDRAM Module Attributes
Analysis probe not
installed, FET switch
external not enable
00
22
DDR2 SDRAM Device Attributes: General
Supports weak driver
03
23
DDR2 SDRAM Cycle Time CL=X-1
3.75ns
3D
24
DDR2 SDRAM Access from Clock CL=X-1
±0.5ns
50
25
DDR2 SDRAM Cycle Time CL=X-2
5.0ns
50
26
DDR2 SDRAM Access from Clock CL=X-2
±0.6ns
60
27
Minimum Row Precharge Time (tRP)
15ns
3C
28
Minimum Row Active to Row Activate delay (tRRD)
7.5ns
1E
29
Minimum RAS to CAS Delay (tRCD)
15ns
3C
30
Minimum active to Precharge time (tRAS)
45ns
2D
31
Module ROW density
1GB
01
32
Command and address setup time before clock(=tIS)
0.20ns
20
33
Command and address hold time after clock(=tIH)
0.27ns
27
34
Data input setup time before strobe(=tDS)
0.10ns
10
35
Data input hold time after strobe(=tDH)
0.17ns
17
T
T
TS
S
S2
2
25
5
56
6
6M
M
MS
S
SQ
Q
Q6
6
64
4
4V
V
V6
6
6U
U
U-
-
-I
I
I
200PIN DDR2 667 SO-DIMM
2Rank 2GB With 128Mx8 CL5
Transcend Information Inc.
11
36
Write recovery time(=tWR)
15ns
3C
37
Internal write to read command delay(=tWTR)
7.5ns
1E
38
Internal read to precharge command delay(=tRTP)
7.5ns
1E
39
Memory analysis probe characteristics
-
00
40
Reserved
-
06
41
DDR2 SDRAM Minimum Active to Active/Auto Refresh
Time(tRC)
60ns
3C
42
DDR2 SDRAM Minimum Auto-Refresh to
Active/Auto-Refresh Command Period (tRFC)
127ns
7F
43
DDR2 SDRAM Maximum Device Cycle Time (tCK
max)
8ns
80
44
DDR2 SDRAM DQS-DQ Skew for DQS and associated
DQ signals (tDQSQ max)
0.24ns
18
45
DDR2 SDRAM Read Data Hold Skew Factor (tQHS)
0.34ns
22
46
PLL Relock Time
-
00
47~61
Superset Information
-
00
62
SPD Data Revision Code
REV 1.2
12
63
Checksum for Bytes 0-62
-
15
64-71
Manufacturers JEDEC ID
Transcend
7F, 4F
72
Manufacturing Location
T
54
73-90
Manufacturers Part Number
TS256MSQ64V6U-I
54
53
32
35
36
4D
53
51
36
34
56
36
55
2D
49
20
20
20
91-92
Revision Code
-
-
93-94
Manufacturing Date
By Manufacturer
Variable
95-98
Assembly Serial Number
By Manufacturer
Variable
99-127
Manufacturer Specific Data
-
-
128~255
Open for customer use
Undefined
-