MECL 10,000 sERn MIEGIE INTEGRATED CIRCUITS FROM MOTOROLA Md EGE MC10,100/10,200 Series (-30 to +85C) MC10,500/10,600 Series (-55 to +125C) MECL 10,000 has an excellent speed-power product, Circuit design with MECL 10,000 is unusually con- has relatively slow rise and fall times, and transmission- venient. The differential amplifier input and emitter- line drive capability. The combination of versatile logic follower output permit high fanout, the wired-OR option, D functions and the 2.0 ns propagation delay make MECL and compfementary outputs. MECL [ft is directly com- 10,000 a versatile family for data handling and processing patible with MECL 10,000, and can be used to extend the systems. speed capability of the MECL 10,000 series. cemawne PACKAGE 7 PLASTIC PACKAGE 3 LE ceRanic PACKAGE cage 623 | ii CASE 648 Le CASE 650 P SUFFIX L SUFFIX AL SUFFIX PLASTIC PACKAGE CERAMIC PACKAGE CERAMIC PACKAGE F SUFFIX CASE 649 CASE 620 CASE 690 CERAMIC PACKAGE CASE 652 FUNCTIONS AND CHARACTERISTICS (Vcc = 0, Veg = -5.2 V, Ta = 25C) Typ) Propagawon Power oration Function -30 to +85C | -55 to +125C ns typ typ/pkg* Case Quad 2-Input NOR Gate with Strobe Mc10160 - 2.0 400 620 Quad OR/NOR Gate Mc10101 Mc10501 2.0 100 620,648,650 Quad 2-Input NOR Gate Mc10102 MC10802 2.0 100 620,648,650 Quad 2-Input OR Gate MC10103 ~ 2.0 100 620 Quad 2-Input AND Gate MC10104 MC10504 2.7 140 620,648,650 Triple 2-3-2-Input OR/NOR Gate Mc10105 MC 10505 2.0 90 620,648,650 Triple 4-3-3-input NOR Gate MCtTat0G MC 10506 2.0 90 620,648,650 Triple 2-Input Exclusive OR/Exclusive NOR MC10107 MC10507 2.5 110 620,648 650 Dual 4-5-Input OR/NOR Gate mMc10109 MC 10509 2.0 60 620,648,650 Dual 3-Input 3-Output OR Gate Mct0110 - 2.4 160 620,648 Dual 3-Input 3-Output NOR Gate mctoi11 - 2.4 160 620,648 Quad Exclusive OR Gate Mc10113 - 2.5 175 620 Triple Line Receiver Mc10114 MC 10514 2.4 145 620,648,650 Quad Line Receiver Mct10115 MC10515 2.0 410 620,648 650 Triple Line Receiver Mc10116 MC 10516 2.0 85 620,648,650 Dual 2-Wide 2-3-Input OR-AND/OR-AND.- MC10117 MC10517 2.3 100 620,648,650 INVERT Gate Dual 2-Wide 3-Input OR-AND Gate Mc10118 MC10518 2.3 100 620,648,650 4-Wide 4-3-3-3-Input OR-AND Gate Mc10119 MC10519 2.3 100 620,644,650 | 4-Wide OR-AND/OR-AND-INVERT Gate Mc10121 MC10521 2.3 100 620,648,650 Triple 4-3-3-Input Bus Driver McC10123 ~ 3.0 310 620 Quad MTTL to MECL Translator MC10124 MC 10524 3.5 380 620,648,650 Quad MECL to MTTL Translator Mc10125 MC 10525 4.5 380 620,648 650 Dua) MECL to MOS Translator Mc10127 _ _ = 620 Bus Driver Mmic10128 - 12.0 700 620 Quad Bus Receiver MC10129 = 10.0 750 620 Oual Latch MC10130 MC 10530 2.5 455 620,648,650 Dual Type DB Master-Stave Flip-Fiop MCTOISt MC10531 f= 160 MHz 235 620,648,650 Dual Multiplexer With Latch and Common Reset Mc10132 = 3.0 225 620,648 Quad Latch MC10133 MC 10533 4.0 310 620,648,650 Multiplexer with Latch McC10134 _ 3.0 225 620,648 Dual J-K Master-Slave Flip-Flop Mc10135 MC 10835 f= 140 MHz 280 620,648 650 Universal Hexadecimal Counter MC10136 MC 10536 f= 180 MHz 625 620,650 @ L suffix denotes Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package (i.e., MC10100L = Ceramic Dual In-Line Package, MC10100P = Plastic Dual In-Line Package and MC10S00F = Ceramic F lat Package.) External Load Power not included. 2-11LOGIC DIAGRAMS (continued) COUNTERS (14) 10 Tin 20) (9) 134c (146)1200 2 (18) 11-4D1 (1a) 61o2 % (9) 54103 3 (13) 94s81 (11) 74s2 Court Decrement FUNCTION SELECT TABLE MC 10136. MC 10536 Universal Hexadecimal b 14 (2) Counter SEQUENTIAL TRUTH TABLE* t 15 (3) INPUTS QUTPUTS Carry | Clock Carry r 2 (6) $1|$2|Do| 01/02] 03] in ** | aola1| a2] a3] Gut L L L L H H cs H L Lt H 4 L 3 (7) clH]ofolelojoe ee oe oe LPHJ@] op ole L H LC ]HI HTH H CTH]e]ofeie L H H}H{ HH u r 4 (8) tfayolelofe] x ct JHiwfH{H] ou L H cd oo H H H H H H H H}/H]|o@]]e]e o q H|]HE HI] R H LPL] HH] H] eye o H H|HEOEqL L H]/L}@} of o]o L H LyHyLPeL H Hit {ot o}fofoy oe H tH}olife] # HILI@ [of ole L rt LPpefeye L HiL pol ofp ots L H H]H] HI H H = Don't care. "Truth table shows logic states assuming inputs vary in sequence Increment Decrement Pp = 625 mW typ/pkg ( feount = 150 MHz typ No Load) Pp = 625 mW typ/pkg (No Load) shown from top to bottom. foount = 150 MHz typ TA clock H is defined as a clock input transition from a low to a high logic level. MC 10137 Universal Decade 10 4Gj, Q0- 14 Counter SEQUENTIAL TRUTH TABLE* 413ac INPUTS QUTPUTS 12 Qatr 15 Gan bo arry | Clock Carry "1 D1 $1) $2] 00|D1{ D203] In aie QO 41] a2] Qa} Our 6 D2 Q2 2 LJef>rfafuyeTl oe H [HpH Ho] # we tJHfefeleleye Ho fuefetefH] x 57D3 a3} 3 LTH] o@]ole@le] ec H fRpPoUPe Pape 9g1$1 c{H{[ofofele]e HH fefefefe]# tJHtololfele]e # fulefeofetu 7 $2 Cout 4 L]H]oleolelo] wo fapvetde fey a t|H]elelele] 4 H [Hi efefecl H/H]/ oo] o}e o H Hpepouyeo rH cfefuta[eol ey] H [ofpHi ele] FUNCTION SELECT TABLE micleteoletelo wo TUT Toro HiL [oe ;o] oe kL H H?eP ope H HJL[@] oto] e L H bpedege i o = Dont care. *Truth table shows logic states assuming inputs vary in sequence shown from top to bottom. ** A clock H is defined as a clock input transition from a low to a high logic tevel. (Clock connected to C2 and Q3 connected to C1} H L L H H H Pp = 370 mW typ/pkg frog = 150 MHz typ MC 10138 Bi-Quinary Counter 124C1 aQoh15 94R Q1}+- 13 74C2 a2}t 4 4+s0 a3} 2 104 $1 Gor 14 6S2 Gsar 3 51s3 COUNTER TRUTH TABLES BI-QUINARY BCD (Clock connected to C1 and QO connected to C2) L H (No Load) MC 10178 Binary Counter 11s0 aor 15 TRUTH TABLE 7 $1 Q1 13 INPUTS. OUTPUT: _ bee Urs 6 S2 Q2 4 [eso] st]s2] 3]1| c2| a0] ai] a2] os 5 _S3 Q3; 2 Hoole pele te fee yefere 12C1 Qoh 14 L 4 H}|HT HT eto} HT HPA] aw a L L L r 10-jC2 a3t- 3 bPetetefe $ 4 Ne Geunt g93IR L tl Ll L L oe L tL t L L L L L L H L L L ul L L L t oe L H Lt L cfpeyveqefec o fadafode Pp = 370 mW typ/pkg LPePepefu a LCL yey aye L . (No Load) tlefc}elc Di tyal atc = epofyefere H] frog = 150 MHz (Typ) thefefefe city cya tyefetepe efele|x cfepefete ceRyot aR Ll L L L L H H L H epefuperde eyefaya LPetetege . w]e] Ha Lt L L t u . t aH H H cfetetepe [aitalate ** b= Don't Care Sf." Clock transition from Vi_ to Vi ty Vit may be applied to C1 or C2 or both for same effect. 2-23UNIVERSAL HEXADECIMAL COUNTER MECL 10,000 series MC10536 SEQUENTIAL TRUTH TABLE* INPUTS OUTPUTS Carry | Clock Carry $1] $2} DO} D1 {| D2] D3 In * Q0} Q1| 02, Q3] Out cpe}yuey_LP HH o H LJupHypH L LJ[H]/o]le]ele L H H{[UL]uH|H H LlIH{e@letole u 4 LPH PHISH 4 LI HI od | o]o feo u H H [HHH L CLIH|@ oi ole H u HHH RH H tlH]|@le}fo|le H H Hj{HI]H]H H HIHig@ | @ lo] oe % H H/|HIHIH H ete | Ht ufete H HHP Ede u H}L [Oo] ot oO] L H LPHJoefte H H}tL}o]]o)] L H HiJeEfeIeL H HIL[o 1 oo] o] L H tL toeJueye L H] Lo ot o]e L H H{H|H{[H H @ = Don't care. * Truth table shows logic states assuming inputs vary in sequence shown from top to bottom, ** A clock H is detined as a clock input transition from a low toa high logic Jevel. The MC10536 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 100 MHz. This binary counter is useful in high speed central processors and peripheral controllers, minicomputers, high speed digital commu- nications equipment and instrumentation. The fiexi- bility of this device allows the designer to use one basic counter for most applications, and the synchron- ous count feature makes the MC10536 suitable for either computers or instrumentation. . Three contro lines (S1, $2, and Carry in) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up}, decrement (count down}, or hold {stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (DO, D1, D2, and D3) will be entered into the counter. Carry Out goes low on the terminal count, or when the counter is being preset. When an output is not needed, it can be left open to conserve system power. (The open emitter output will require no power if left open). The counter changes state only on the positive going edge of the clock. Any other input may change at any time except during the positive transition of the clock. This device is not designed for use with gated clocks. Control is via $1 and $2. A prescaler can be constructed using the MC 10536 in conjunction with the MC10631 which will operate at over 200 MHz input frequency. A500 MHz prescater is possible using an MC 1690 500 MHz D Flip-Flop, an MC 1670 300 MHz D Flip-Flop, and the MC 10536. (14)10 Cin oo} 14 (2) (13 (16.12 ba 7 D1 Mou Q2-- 2 (6) {10} 6 02 oO Qi- 15 (3) {9} 5~ 03 a3}- 3 (7) 3) 34s1 (4) 7482 Surb-4 Numbers at ends of terminals denote pin numbers for L package {Case 620). Numbers in parenthesis denote pin numbers for F package (Case 650). L FUNCTION SELECT TABLE $1 $2 Operating Mode L Lt Preset (Program) L H Increment (Count Up) H u Decrement (Count Down) H H Hold (Stap Count) Pp = 625 mW typ/pkg (No Load) fcount = 150 MHz typ Case | Veci | Vec2 | VEE 620 | Fini | Pin16 | Ping 650 | Pins [| Pina | Pin 12 See General Information section for packaging. 3-296L6C-& ELECTRICAL CHARACTERISTICS Each fuli temperature range MECL 10,000 10 Cin a0 14 series circuit has been designed to meet the 1341C ! de specifications shown inthe test table, 12 bo Qt} 15 L SUFFIX after thermal equilibrium has been estab- CERAMIC PACKAGE lished. The circuit is in a test socket or 1 o1 o2|. 2 CASE 620 mounted on a printed circuit board and +6 j D2 transverse air flow greater than 500 linear 5+1 D3 a3 3 fpm is maintained. Outputs are terminated 9 st TEST VOLTAGE VALUES " _ through a 100-ohm resistor to -2.0 voits. 1 (Voits) Test procedures are shown for only one 7\4 82 C, 4 @ Test p . ny. out Temperature | Vitimax | Vitmin | VtHAmin | VILA max vee input, or for one set of input conditions. , Other inputs or outputs are tested in the ~s5c | 0.880 =1820 ~1285 21510 $2 sare man er pu 425C | 0.780 -1.850 71.105 1.475 52 faner. : +125c | _-0.630_| -1.820 | 1.000 =1.400 2 Pi TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under ~55C +125C Vec) Characteristic Symbol Test Min Max Min Typ Mex Min Max Unit Vitimax | Vicmin_| VIHA min | VILA max Vee Grd Power Supply Drain Current le 8 - 165 - 120 180 - 165 mAdc - - - - 1,16 input Current ln .6,11,12 - 375 - = 220 - 220 wade 5.6,11,12 ~ = ~ 1,16 7 - 450 - - 265 - 265 7 - - - 9,10 - 415 - 245 - 245 9,10 - - 13 - 495 - - 290 - 290 13 - - - link All 05 - O05 =. 03 - wAdc - @ - = 1,16 Logic 1 Vou 4@ -1.080 | -0.880 | -0.930 = -0.780 | -0.828 | -0.630 Vdc 12 7,9 - = 1,16 Output Voltage Logic 0 ~ Vor 14@ -1.920 | -1.655 | -1.850 - 1.620 | -1.820 | -1.545 Vde - 7.9 = = 1.16 Output Voltage Logie "1" : VoHA 4@ =1.100 - -0.950 - - -0.845 - Vde - 7.9 12 = 1.16 Threshold Voltage Logic 0 VOLA 4@ = 1.636 - - -1.600 1.525 Vde = 7,9 = 12 1,16 Threshold Voltage Switching Times aatVv [| 031V Pulse In [ Pulse Our -3.2V 420V (100-ohm Load) Propagation Oelay . Clock Input taaetas 14 os 46 10 33 45 14 .2 ns 12 - 13 14 1.16 t13414- 14 08 46 10 33 45 14 5.2 - - 14 1344+ 4 2.0 11.0 25 70 10.5 24 12.6 7 4 t1344- 4 2.0 11.0 25 7.0 10.5 2.4 12.6 7 - Carry In To Carry Out t10-4- 4@ 16 7A 16 50 69 19 76 7 13, 10 eae 4 16 7A 16 5.0 69 1.9 76 7 8 10 Set Up Time Data Inputs 1924134 14 = = 3.5 - - ~ = = 7.9 12,13 4 192-134 14 - - 3.5 - - - - - 7,9 12,13 Select Inputs 9413+ 14 - - 75 - - - - - 9,13 7413+ 14 - - 78 - - - - - - 7,13 Carry In Input 40-134 14 - 37 - - - - 7 3 10, t3 (134104 14 - - -1.0 - - - - 7 9 10, 13 Hold Time Data Inputs | 134124 14 - -1.0 - - - - - 1.9 12,13 tyge12- f. 14 - - 1.0 - - ~ - - 7,9 12,13 Select inputs 143494 14 - - -2.5 - ~ - - - 9,13 1347+ 14 - - 72.5 - - - - - - 7,13 Carry In Input 13410- 14 16 - ~ - = 7 9 10,13 tro+134 14 - - 34 - - - 7 9 10,13 Counting Frequency feountup 4 115 - 125 150 - 115 - MHz 7 - 13 countdown 4 115 126 150 - 115 MHz 9 - Rise Time tae 4 og 33 ww 2.0 33 12 37 ns 7 - 4 {20% to 80%) tat 14 7 Fall Time tq 4 | | _ 4 (20% to 80%) 14- 14 - 14 @ individually appty VL min to pin under test. ViH @ Measure output after clock pulse ViL S appears at clock input (pin 13) @ Before test set all Q outputs to a logic high. (panunuos) 9EGOLOIN862- ELECTRICAL CHARACTERISTICS Each full temperature range MECL 10,000 14 Cin Qor 2 series circuit has been designed to meet the mt 3 1c F SUFFIX de specifications shown in the test table, or 3 chet 16 40do CERAMIC PACKAGE after thermal equilibrium has been estab- CASE 650 lished. The circuit is in a test socket or 16 D1 02 mounted on a printed circuit board and 10 : D2 & transverse air flow greater than 500 linear q is maintai i 9 53 |__ - fpm is maintained. Outputs are terminated a3 7 TEST VOLTAGE VALUES through a 100-ohm resistor to -2.0 voits. 18 4S1 vols? Test procedures are shown for only one "4 $2 Cour 8 @ Test input, or for one set of input conditions. ou Temperature | Vitimax | Vitmin | VinAmin | VILA mex VEE Other inputs or outputs are tested in the -55C | -0.880 -1.920 1.255 -1,510 52 same manner. #25C | -0780 -1.850 -1.105, 1.475 52 _ +125% | -0.630 -1.820 -1.000 1,400 $2 MC10536: imi Pin S BOG Fest birnits s TEST VOLTAGE APPLIEO TO PINS LISTED BELOW Under -55C +25C +125C Vee! Characteristic Symbol Test Min Max Min Tye Max Min Max Unit Vittmax | Viemin | Vinamin | Vicamax Vee Gad Power Supply Drain Current ie 12 - 165 - 120 150 - 165 mAdc - = - - 12 45 input Current lin | 9,10,15,16 = 365 = ~ 215 - 215 uAdc 9,10,15,16 = = = 12 45 "1 - 445 - ~ 260 - 260 | "1 - - - 13,14 - 410 - ~ 240 - 240 t 13,14 - - = i - 485 - 285 - 288 1 - - - fink All os = 0.5 ~ - 03 - nAdc - oO - = 12 45 } Logic 1 Vou 20 -1.080 | -0.880 [-0.930 ~ -0.780 | -0.825 | -0.630 Vde 16 11,13 = = 12 45 Output Voltage Logic 0 Vou 2@ -1.920 | -1.655 | -1.850 ~ -1.620 [ -1.820 | -1.545 vac = 1113 = = 12 45 Output Voltage Logic 1 VoHA 20 -1.100 - -0.950 ~ - -0.845 - Vde - 11,13 16 - 12 45 Threshold Voltage Logic 0 VOLA 20 - =1.635 = ~ -1,600 = =1.525 vde = 11,13 = 16 12 45 Threshold Voltage Switching Times atv | 031V Pulse tn | Pulse Out 32V +200 (100-ohm Load) Propagation Delay Clock Input tq425 2 - - 1.0 33 45 - - ns 16 - 1 2 12 4s 42. 2 - - 1.0 33 45 - - - - 2 thege 8 - - 25 7.0 10.5 - - " 8 44g. 8 - - 25 70 10.5 - - " - Carry In To Carry Out 14-8 8 - - 16 5.0 69 - - ch 1 14 trat+Be 8 ~ - 16 50 69 - - " 1 14 Set Up Time Data Inputs tre+1+ 2 - = 35 - - - - - 11,13 1,16 ~ 2 t16-1+ 2 - - 35 - - - - 18,43 1,16 Select inputs 143444 2 - - 78 _ - - - - - 1413 test 2 - 78 - - - - - - 1,14 . Garry In Input 14-14 2 - - 3.7 - - - - "1 13 1,14 4414+ 2 - - 1.0 - - - - 1" 13 114 Hold Time Data inputs t1+16+ 2 - - -10 - - - - = 12,13 1,16 . t1+16- 2 - - -1.0 ~ - - - - 11,13 1,16 Select Inputs | ty+13+ 2 - - -2.5 - - - - - _ 1,13 tye 2 - - -25 7 - - - - - 1,14 Carry In input tH14- 2 - - 16 - - ~ - 4 13 144 Matte 2 - - 3 - - - - WW 13 114 Counting Frequency foountup 8 = - 125 150 = = - MHz rs - 1 fcountdown 8 - - 128 150 - ~ - MHz 13 - Rise Time tae 8 - - V1 20 3.3 - - ns WV - 8 {20% to 80%) toy 2 - - = - _ 2 Fall Time & 8 ~ - - - - 8 {20% to 80%) t2. 2 = - = = - 2 @ Individually spply Vj, min to Pity under test, sys @ Measure output after clock pulse Vj_ appeers at clock input (pin 13) @ Before test set 4il.C outputs to a lagic high. (penunuocs) 9ESOLOINMC 10536 (continued) SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C (bp) is the minimum time before the counter has been disabled that it may be clocked. NOTE: tsetup is the minimum time before the positive transition of the clock pulse (C! that information must Vie Voc1= Yoo2 = +2.0 Vde Vout be present at the input O or S. * Thotd is the minimum time after the positive tran- sition of the clock pulse (C} that information must remain unchanged at the input D or 5. Coax Coax 50 Input Pulse te=t=2.0nst O.2ns (20 to 80%} Clock Input + +-0 \ +14 TPin TPout Ctock 50% +O.31V tc+a- Q Output ta- Veg = -3.2 Vde +tEdV c +0.31V thoid & 50-ohm termination to ground to- cated iin each scope channel input. Dors : All input and output cables to the scope are equal lengths of 50-ohm setup H coaxial cable. Wire length should c be <1/4 inch from TPj, to input Qa pin and TP oy to Output pin. Vout is 2:1 attenuated. Unused outputs are connected to a 100-ohm resistor to ground. SET UP AND HOLD TIMES n 4 {b) Garvin | i ' (9) is the minimum time to wait after the | counter hat been enabled to clock it, 1 | 1 {c) is the minimum time before the counter is enabled that a ciock pulse may be applied with no effect on the state of the counter, (d} is the minimum tims to wait after the counter is disabled thet a clock pulse may be applied with no effect in the state of the counter. (bd) and (c) may be negetive numbers Carry In te} Clock 3-299MC 10536 (continued) COUNT FREQUENCY TEST CIRCUIT Vin Veo1= Voc2=+2.0 Vde Vout Coax Coax Clock Input input Pulse oe = vers | All input and output cables to the uty Cycle = 50% scope are equal lengths of 50-cohm coaxial cable. Wire length should be <1/4 inch from TPj, to input pin and TPout to output pin. Vout is 2:1 attenuated. 0.1 wR 50-ohm termination to ground io- cated in each scope channel input. Unused outputs are connected to a 100-ohm resistor to ground. 44,100 Veg ==3.2 Vde UNIVERSAL BINARY UP/DOWN COUNTER $1 90-9 )4 <7 $2 7 Carry In 100 - | r T ait 7 Gir iF a3 T Foot Faz} 730 [' Tell | : [| Te TT c Glock 130 i | 12 DO 4400 4101 15a 6 D2 202 5 D3 3.03 4 Tarry OutMC10536 (continued) APPLICATIONS INFORMATION To provide more than four bits of counting capability several MC10536 counters may be cascaded. The Carry In input overrides the clock when the counter is either tn the increment mode or the decrement mode of operation. This input allows several devices to be cascaded in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between stages as shown with no external gating. The Carry In of the first device may be jeft open. The system clock is common to al! devices, The various operational modes of the counter make it useful for a wide variety of applications. If used with MECL III devices, prescalers with input toggle frequencies in excess of 300 MHz are possible. Figure 2 shows such a prescaler using the MC10536 and MC1670. Use of the MC10631 in place of the MC1670 permits 200 MHz operation. The MC10536 may also be used as a programmable counter. The configuration of Figure 3 requires no additional gates, although maximum frequency is limited to about 50 MHz. The divider modulus is equal to the program input plus one (M = N + 1}, there- fore, the counter will divide by a modulus varying from 1 to 16. A second programmable configuration is also illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up to 110 MHz typically. The divider modulus for this figure is equal to the program input (M = N). The minimum modulus is 2 because of the pulse swallowing technique, and the modulus may vary from 2 to 15. This programmable configuration requires an additional gate, such as 4MC10509 and a flip-flop such as %MC 10831. FIGURE 1 12 BIT SYNCHRONOUS COUNTER LSB MSB a ao a1 G2 A385 c ao ai a Qa3e =. a ai a2 Cin Cout Cin 2 a3 Cout Cin as c c c System Clock ~ Note: S1 and $2 are set either for increment or decrement operation. FIGURE 2 300 MHz PRESCALER Logic High MC10536 $1 js2 D Qa c Q3 Input | Input Frequency Frequency c 32,O a MC1670 3-301MC 10536 (continued) FIGURE 3 50 MHz PROGRAMMABLE COUNTER Program Input DO Dt D2 D3 fin Cout fout fin Program Input + 1 2 fmax S24 50 MHz Typ. 1 fout = 3 Divide Ratio is from 1 to 16. FIGURE 4 100 MHz PROGRAMMABLE COUNTER Program Input DO D1 D2 03 MC10536 Qo a2 a3 fout %MC 10509 %MC10531 f; in 1 fout = Program Input 2) fmax = 110 MHz Typ. 3 Divide Ratio is from 2 to 15. 3-302