16-Bit, Isolated Sigma-Delta Modulator
Enhanced Product
AD7403-EP
Rev. 0 Document Feedback
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FEATURES
5 MHz to 16 MHz external clock input rate
16 bits, no missing codes
Signal-to-noise ratio (SNR): 88 dB typical
Effective number of bits (ENOB): 14.2 bits typical
Offset drift vs. temperature: 1.6 µV/°C typical
On-board digital isolator
On-board reference
Full-scale analog input range: ±320 mV
High common-mode transient immunity: >25 kV/µs
Wide-body SOIC with increased creepage package
Slew rate limited output for low EMI
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 1250 VPEAK
ENHANCED PRODUCT FEATURES
Defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Data acquisition systems
Analog-to-digital and optoisolator replacements
GENERAL DESCRIPTION
The AD7403-EP1 is a high performance, second-order, Σ-Δ
modulator that converts an analog input signal into a high
speed, single-bit data stream, with on-chip digital isolation
based on Analog Devices, Inc., iCoupler® technology. The
device operates from a 5 V (VDD1) power supply and accepts a
differential input signal of ±250 mV (±320 mV full-scale). The
differential input is ideally suited to shunt voltage monitoring in
high voltage applications where galvanic isolation is required.
FUNCTIONAL BLOCK DIAGRAM
V
DD1
V
DD2
AD7403-EP
BUF
REF
CLK
DECODER
GND
1
GND
2
MDAT
MCLKIN
(5MHz
TO 16MHz)
V
IN+
V
IN–
CLK
ENCODER
DATA
ENCODER DATA
DECODER
Σ-Δ ADC
13395-001
Figure 1.
The analog input is continuously sampled by a high performance
analog modulator, and converted to a ones density digital output
stream with a data rate of up to 16 MHz. The original
information can be reconstructed with an appropriate digital
filter to achieve 88 dB signal to noise ratio (SNR) at 78.1 kSPS.
The serial interface is digitally isolated. High speed complementary
metal oxide semiconductor (CMOS) technology, combined with
monolithic transformer technology, means the on-chip isolation
provides outstanding performance characteristics, superior to
alternatives such as optocoupler devices. The AD7403-EP
device is offered in a 16-lead, wide-body SOIC package and has
an operating temperature range of −55°C to +125°C.
Additional application and technical information can be found
in the AD7403 data sheet.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
AD7403-EP Enhanced Product
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 5
Insulation and Safety Related Specifications ............................ 5
Regulatory Information ............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics ...............................................................................6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ..............................................9
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
4/16—Revision 0: Initial Version
Enhanced Product AD7403-EP
Rev. 0 | Page 3 of 12
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 4.5 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, T A = −55°C to +125°C, fMCLKIN = 5 MHz to 16 MHz, tested
with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits Filter output truncated to 16 bits
Integral Nonlinearity (INL)1 ±2 ±12 LSB
Differential Nonlinearity (DNL)1 ±0.99 LSB Guaranteed no missed codes to 16 bits
Offset Error1 ±0.2 ±0.9 mV
Offset Drift vs. Temperature
2
1.6
µV/°C
1.3 3.1 µV/°C 0°C to 85°C
Offset Drift vs. VDD12 50 µV/V
Gain Error1 ±0.2 ±0.95 % FSR
Gain Error Drift vs. Temperature2 65 95 ppm/°C
40 60 µV/°C
Gain Error Drift vs. VDD12 ±0.6 mV/V
ANALOG INPUT
Input Voltage Range −320 +320 mV Full-scale range
−250
mV
For specified performance
Input Common-Mode Voltage Range −200 to +300 mV
Dynamic Input Current ±45 ±50 µA VIN+ = ±250 mV, VIN− = 0 V
0.05 µA VIN+ = 0 V, VIN− = 0 V
DC Leakage Current ±0.01 ±0.6 µA
Input Capacitance
14
pF
DYNAMIC SPECIFICATIONS1 VIN+ = 1 kHz
Signal-to-Noise-and-Distortion Ratio (SINAD) 82 87 dB
Signal-to-Noise Ratio (SNR) 86 88 dB
Total Harmonic Distortion (THD) −94 dB
Peak Harmonic or Spurious Noise (SFDR) −95 dB
Effective Number of Bits (ENOB) 13.1 14.2 Bits
Noise Free Code Resolution
14 Bits
ISOLATION TRANSIENT IMMUNITY1 25 30 kV/µs
LOGIC INPUTS CMOS with Schmitt trigger
Input Voltage
High (VIH) 0.8 × VDD2 V
Low (VIL) 0.2 × VDD2 V
Input Current (IIN) ±0.6 µA
Input Capacitance (CIN) 10 pF
LOGIC OUTPUTS
Output Voltage
High (V
OH
)
V
DD2
− 0.1
V
I
O
= −200 µA
Low (VOL) 0.4 V IO = 200 µA
POWER REQUIREMENTS
V
DD1
4.5
V
VDD2 4.5 5.5 V
IDD1 30 36 mA VDD1 = 5.5 V
IDD2 12 18 mA VDD2 = 5.5 V
Power Dissipation 231 297 mW VDD1 = VDD2 = 5.5 V
1 See the Terminology section of the AD7403 datasheet.
2 Not production tested. Sample tested during initial release to ensure compliance.
AD7403-EP Enhanced Product
Rev. 0 | Page 4 of 12
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 4.5 V to 5.5 V, TA = −55°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure
compliance. It is recommended to read MDAT on the MCLKIN rising edge.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit Description Min Typ Max
fMCLKIN 5 16 MHz Master clock input frequency
t11 45 ns Data access time after MCLKIN rising edge
t21 12 ns Data hold time after MCLKIN rising edge
t3 0.45 × tMCLKIN ns Master clock low time
t4 0.45 × tMCLKIN ns Master clock high time
1 Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V or when the output crosses 0.8 V or 0.7 ×
VDD2 for VDD2 = 4.5 V to 5.5 V as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance.
MCLKIN
MDAT
1
SEE NOTE 1 OF TABLE 3 FOR FURTHER DETAILS.
t
4
t
1
t
2
t
3
80%
2.0V OR 0.7 × V
DD21
0.8V
13395-002
Figure 2. Data Timing
Enhanced Product AD7403-EP
Rev. 0 | Page 5 of 12
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)
1
R
I-O
10
12
Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1 The device is considered a 2-terminal device. For AD7403-EP, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Test Conditions/Comments
Input to Output Momentary Withstand Voltage VISO 5000 min V 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.3 min1, 2 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.3 min1 mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.034 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 13
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I)3
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
3 CSA CTI rating for the AD7403-EP is >575 V and therefore Material Group II isolation group.
REGULATORY INFORMATION
Table 5.
UL1 CSA VDE2
Recognized under 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
5000 V rms Isolation Voltage
Single Protection
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
830 V rms (1173 VPEAK), maximum working voltage3
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 VPEAK
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1. 415 V rms (586 VPEAK) maximum working
voltage3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 VPEAK) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each AD7403-EP is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7403-EP is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC).
3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7403-EP RI-16-2 package material is rated by CSA to a CTI of >575 V and therefore
Material Group II.
AD7403-EP Enhanced Product
Rev. 0 | Page 6 of 12
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms I to IV
For Rated Mains Voltage ≤450 V rms I to IV
For Rated Mains Voltage ≤600 V rms I to IV
For Rated Mains Voltage ≤1000 V rms I to IV
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE
V
IORM
1250
V
PEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC VPD(M) 2344 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD A VPR(M)
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC 2000 VPEAK
After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC 1500 VPEAK
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, t
TR
= 10 Seconds)
V
IOTM
8000
V
PEAK
SURGE ISOLATION VOLTAGE VIOSM VPEAK
1.2 µs Rise Time, 50 μs, 50% Fall Time 7500 VPEAK
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3)
Case Temperature TS 150 °C
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation PSO 2.78 W
INSULATION RESISTANCE AT TS, VIO = 500 V RIO >109 Ω
0
1
2
3
4
050 100 150 200
SAFE OPERATING POW ER (W)
AMBI E NT TE M P E RATURE (°C)
13395-003
Figure 3. Thermal Derating Curve, Dependence of Safety
Limiting Values with Case Temperature per DIN V VDE V 0884-10
Enhanced Product AD7403-EP
Rev. 0 | Page 7 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 7.
Parameter Rating
VDD1 to GND1 −0.3 V to +6.5 V
VDD2 to GND2 −0.3 V to +6.5 V
Analog Input Voltage to GND1 −1 V to VDD1 + 0.3 V
Digital Input Voltage to GND2 −0.3 V to VDD2 + 0.5 V
Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb-Free Temperature, Soldering
Reflow 260°C
ESD 2 kV
FICDM
2
±1250 V
HBM3 ±4000 V
1 Transient currents of up to 100 mA do not cause SCR to latch up.
2 JESD22-C101; RC network: 1 Ω, Cpkg; Class: IV.
3 ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 8. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage
Bipolar Waveform
1250
V
PEAK
20-year minimum
lifetime (VDE approved
working voltage)
Unipolar Waveform 1250 VPEAK 20-year minimum
lifetime
DC Voltage 1250 VPEAK 20-year minimum
lifetime
1 Maximum continuous working voltage refers to continuous voltage
magnitude imposed across the isolation barrier.
ESD CAUTION
AD7403-EP Enhanced Product
Rev. 0 | Page 8 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
V
IN+ 2
V
IN– 3
GND
14
GND
2
16
NIC
2
15
V
DD2
14
MCLKIN
13
NIC
15
NIC
2
12
NIC
16
MDAT
11
V
DD1 7
NIC
2
10
GND
18
GND
2
9
1
NIC = NOT INTERNALLY CONNECTED. CONNECT TO V
DD1
, GND
1
, OR LEAVE FLOATING.
2
NIC = NOT INTERNALLY CONNECTED. CONNECT TO V
DD2
, GND
2
, OR LEAVE FLOATING.
AD7403-EP
TOP VIEW
(Not to Scale)
13395-004
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 7 VDD1 Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7403-EP and is relative to
GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to
GND1 with a 10 μF capacitor in parallel with a 1 nF capacitor.
2 VIN+ Positive Analog Input.
3 VIN− Negative Analog Input. Normally connected to GND1.
4, 8 GND1 Ground 1. This pin is the ground reference point for all circuitry on the isolated side.
5, 6 NIC Not Internally Connected. These pins are not internally connected. Connect to VDD1, GND1, or leave floating.
9, 16 GND2 Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side.
10, 12, 15 NIC Not Internally Connected. These pins are not internally connected. Connect to VDD2, GND2, or leave floating.
11 MDAT
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge.
13 MCLKIN
Master Clock Logic Input. 5 MHz to 20 MHz frequency range. The bit stream from the modulator is propagated on
the rising edge of the MCLKIN.
14 VDD2 Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Decouple
this supply to GND2 with a 100 nF capacitor.
Enhanced Product AD7403-EP
Rev. 0 | Page 9 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, V DD2 = 5 V, V IN+ = −250 mV to +250 mV, VIN− = 0 V, f MCLKIN = 16 MHz, using a sinc3 filter with a 256 oversampling
ratio (OSR), unless otherwise noted.
–140
–120
–100
–80
–60
–40
–20
0
PSRR (dB)
200mV p - p SI NE WAVE ON VDD1
1nF DECO UP LING MCL KIN = 16MHz
MCL KIN = 10MHz
SUPPLY RIPPLE FREQUENCY (kHz)
0200 400 600 800 1000
13395-005
Figure 5. PSRR vs. Supply Ripple Frequency
–140
–120
–100
–80
–60
–40
–20
0
0.1 110 100 1000
CMRR (dB)
RIPPLE FREQUENCY (kHz)
SHORTED INPUT S
200mV p - p SI NE WAVE ON I NP UTS
MCL KIN = 16MHz , SI NC3 DE CIMATION RAT E = 256
MCL KIN = 10MHz , SI NC3 DE CIMATION RAT E = 256
MCL KIN = 16MHz , UNFIL TERED
MCL KIN = 10MHz , UNFIL TERED
13395-006
Figure 6. CMRR vs. Common-Mode Ripple Frequency
80
81
82
83
84
85
86
87
88
89
90
100 1k 10k
SINAD (dB)
ANALOG INPUT FREQUENCY ( Hz )
16MHz M CLKIN, 4.5V V
DD1
16MHz M CLKIN, 5V V
DD1
16MHz M CLKIN, 5.5V V
DD1
13395-007
Figure 7. SINAD vs. Analog Input Frequency
–160
–140
–120
–100
–80
–60
–40
–20
0
0510 15 20 25 30
MAG NI TUDE ( dB)
FRE Q UE NCY ( kHz )
f
IN
= 1kHz
SNR = 88. 6dB
SINAD = 88.3d B
THD = –100.5d B
13395-008
Figure 8. Typical Fast Fourier Transform (FFT)
010 20 30 40 50 60
DNL ERROR (LSB)
CODE (k)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
MCL K = 16M Hz
13395-009
Figure 9. Typical DNL Error
010 20 30 40 50 60
INL ERROR ( LSB)
CODE ( k)
–1.0
–0.5
0
0.5
1.0
1.5
13395-010
Figure 10. Typical INL Error
AD7403-EP Enhanced Product
Rev. 0 | Page 10 of 12
01147
144470
692381
160941
1061 0
0
100
200
300
400
500
600
700
800
32764 32765 32766 32767 32768 32769 32770
HITS PER CODE (k)
CODE
MCLKIN = 10MHz
V
IN+
= V
IN–
= 0V
1M SAMPLES
13395-011
Figure 11. Histogram of Codes at Code Center
60
70
80
100
90
–50 –25 0 25 50 75 100 125 150
SNR AND SINAD (dB)
TEMPERATURE (°C)
SNR
SINAD
f
IN
= 1kHz
13395-012
Figure 12. SNR and SINAD vs. Temperature
–120
–110
–100
–90
–80
–70
–
60
–50 –25 0 25 50 75 100 125 150
SNR AND SINAD (dB)
TEMPERATURE (°C)
THD, MCLK = 16MHz
SFDR, MCLK = 16MHz
f
IN = 1kHz
13395-013
Figure 13. THD and SFDR vs. Temperature
–150
–100
–50
0
50
100
150
250
200
–60 –35 –10 15 40 65 90 115 140
OFFSET (µV)
TEMPERATURE (°C)
V
DD1
= 5V 10MHz
16MHz
13395-014
Figure 14. Offset vs. Temperature
–5
–4
–2
–3
–1
0
1
2
3
5
4
–60 –35 –10 15 40 65 90 115 140
GAIN (mV)
TEMPERATURE (°C)
MCLKIN = 10MHz
MCLKIN = 16MHz
13395-015
Figure 15. Gain Error vs. Temperature
0
5
10
15
20
25
30
35
4.50 4.75 5.00 5.25 5.50
I
DD1
(mA)
V
DD1
(V)
MCLKIN = 16MHz, –55°C
MCLKIN = 16MHz, 0°C
MCLKIN = 16MHz, +25°C
MCLKIN = 16MHz, +125°C
MCLKIN = 10MHz, –55°C
MCLKIN = 10MHz, 0°C
MCLKIN = 10MHz, +25°C
MCLKIN = 10MHz, +125°C
13395-016
Figure 16. IDD1 vs. VDD1 at Various Temperatures and Clock Rates
Enhanced Product AD7403-EP
Rev. 0 | Page 11 of 12
22
23
24
25
26
27
28
29
30
–250 –125 0125 250
I
DD1
(mA)
V
IN+
DC INPUT (mV )
DC INPUT
T
A
= –55° C
T
A
= –40° C
T
A
= 0° C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
13395-017
Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures
0
2
4
6
8
10
12
14
3.0 4.0
3.5 4.5 5.0 5.5
IDD2 (mA)
VDD2 (V)
MCL KIN = 16MHz , –55° C
MCL KIN = 16MHz , 0° C
MCL KIN = 16MHz , +85°C
MCL KIN = 10MHz , –55° C
MCL KIN = 10MHz , 0° C
MCL KIN = 10MHz , +85°C
MCL KIN = 16MHz , –40° C
MCL KIN = 16MHz , +25°C
MCL KIN = 16MHz , +125°C
MCL KIN = 10MHz , –40° C
MCL KIN = 10MHz , +25°C
MCL KIN = 10MHz , +125°C
13395-018
Figure 18. IDD2 vs. VDD2 at Various Temperatures and Clock Rates
10
10
11
12
–250 –125 0
V
IN+
DC INPUT (mV ) 125 250
IDD2 (mA)
DC INPUT
TA = –55° C
TA = –40° C
TA = 0° C
TA = +25°C
TA = +85°C
TA = +125°C
13395-019
Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures
–50
–40
–30
–20
–10
0
10
20
30
40
50
–320 –240 –160 –80 080 160 240 320
IIN+ (µA)
VIN+ DC INP UT (mV)
DC INPUT
MCL KIN = 5MHz
MCL KIN = 10MHz
MCL KIN = 16MHz
13395-020
Figure 20. IIN+ vs. VIN+ DC Input at Various Clock Rates
AD7403-EP Enhanced Product
Rev. 0 | Page 12 of 12
OUTLINE DIMENSIONS
11-15-2011-A
16 9
81
SEATING
PLANE
COPLANARITY
0.1
1.27 BSC
12.85
12.75
12.65
7.60
7.50
7.40
2.64
2.54
2.44
1.01
0.76
0.51
0.30
0.20
0.10
10.51
10.31
10.11
0.46
0.36
2.44
2.24
PIN 1
MARK
1.93 REF
8°
0°
0.32
0.23
0.71
0.50
0.31 45°
0.25 BSC
GAGE
PLANE
COMPLIANT TO JEDE C S TANDARDS MS-013-AC
Figure 21. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7403TRIZ-EP −55°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
AD7403TRIZ-EP-RL7 −55°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
EVAL-AD7403FMCZ AD7403 Evaluation Board
EVAL-SDP-CH1Z System Demonstration Platform
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13395-0-4/16(0)