FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
ICS844011
IDT™ / ICS™ LVDS CLOCK GENERATOR 1 ICS844011AG REV A OCTOBER 6, 2006
PRELIMINARY
GENERAL DESCRIPTION
The ICS844011 is a Fibre Channel Clock Generator
and a member of the HiPerClocksTM family of high
performance devices from IDT. The ICS844011
uses an 18pF parallel resonant crystal over the
range of 20.4MHz - 28.3MHz. For Fibre Channel
applications, a 26.5625MHz crystal is used. The ICS844011
has excellent <1ps phase jitter performance, over the 637kHz
- 10MHz integration range. The ICS844011 is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
FEATURES
•One differential LVDS output
•Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
•Output frequency range: 81.66MHz - 113.33MHz
•VCO range: 490MHz - 680MHz
•RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
•3.3V or 2.5V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
VDDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
VDD
Q
nQ
OE
8
7
6
5
BLOCK DIAGRAM
OSC Phase
Detector
VCO
490MHz - 680MHz
M = ÷24 (fixed)
N = ÷6 (fixed)
Q
nQ
OE
XTAL_IN
XTAL_OUT
Pullup
COMMON CONFIGURATION TABLE - FIBRE CHANNEL
PIN ASSIGNMENT
stupnI ycneuqerFtuptuO
)zHM(
)zHM(ycneuqerFlatsyrCMN
noitacilpitluM
N/MeulaV
5265.62426 4 52.601
52426 4 001
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
ICS844011
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™ LVDS CLOCK GENERATOR 2 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
ADD
rewoP.nipylppusgolanA
2DNGrewoP.dnuorgylppusrewoP
4,3 ,TUO_LATX
NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoehtsiTUO_LATX
5EOtupnIpulluP Qn/Qeht,WOLnehW.evitcasituptuoQn/Q,HGIHnehW.nipelbanetuptuO
.slevelecafretniLTTVL/SOMCVL.etatsecnadepmihgihanisituptuo
7,6Q,QntuptuO.slevelecafretniSDVL.stuptuokcolclaitnereffiD
8V
DD
rewoP.nipylppuseroC
:ETON
pulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
IDT™ / ICS™ LVDS CLOCK GENERATOR 3 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
DD
I–
ADD
01* Ω3.3V
DD
V
I
DD
tnerruCylppuSrewoP DBTAm
I
ADD
tnerruCylppuSgolanA DBTAm
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, IO (LVDS)
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI V
DD
V3.3=2V
DD
3.0+V
V
DD
V5.2=7.1V
DD
3.0+V
V
LI
egatloVwoLtupnI V
DD
V3.3=3.0-8.0V
V
DD
V5.2=3.0-7.0V
I
HI
tnerruChgiHtupnIEOV
DD
V=
NI
V526.2roV564.3=5Aµ
I
LI
tnerruCwoLtupnIEOV
DD
V,V526.2roV564.3=
NI
V0=051-Aµ
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 573.25.2526.2V
V
ADD
egatloVylppuSgolanAV
DD
I–
ADD
01* Ω5.2V
DD
V
I
DD
tnerruCylppuSrewoP DBTAm
I
ADD
tnerruCylppuSgolanA DBTAm
IDT™ / ICS™ LVDS CLOCK GENERATOR 4 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
TABLE 4. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 4.023.82zHM
)RSE(ecnatsiseRseireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
leveLevirD 1Wm
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 66.1833.311zHM
t
)Ø(tij ;)modnaR(rettiJesahPSMR
1ETON
:egnaRnoitargetnI@zHM52.601
zHM01-zHk736 DBTsp
:egnaRnoitargetnI@zHM001
zHM01-zHk736 57.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02572sp
cdoelcyCytuDtuptuO 05%
.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:1ETON
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 66.1833.311zHM
t
)Ø(tij ;)modnaR(rettiJesahPSMR
1ETON
:egnaRnoitargetnI@zHM52.601
zHM01-zHk736 DBTsp
:egnaRnoitargetnI@zHM001
zHM01-zHk736 39.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02592sp
cdoelcyCytuDtuptuO 05%
.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:1ETON
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DO
egatloVtuptuOlaitnereffiD 053Vm
∆V
DO
V
DO
egnahCedutingaM 05Vm
V
SO
egatloVtesffO 2.1V
∆V
SO
V
SO
egnahCedutingaM 05Vm
.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DO
egatloVtuptuOlaitnereffiD 053Vm
∆V
DO
V
DO
egnahCedutingaM 05Vm
V
SO
egatloVtesffO 52.1V
∆V
SO
V
SO
egnahCedutingaM 05Vm
.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON
IDT™ / ICS™ LVDS CLOCK GENERATOR 5 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
SCOPE
Qx
nQx
LVD S
3.3V±5%
POWER SUPPLY
+-
Float GND
Q
nQ
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
out
out
LVD S
DC Input
➤
➤
➤
V
OS
/∆ V
OS
V
DD
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
DIFFERENTIAL OUTPUT VOLTAGE SETUP
SCOPE
Qx
nQx
LVD S
2.5V±5%
POWER SUPPLY
+-
Float GND
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
IDT™ / ICS™ LVDS CLOCK GENERATOR 6 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS844011 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844011 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required.
Figure 1
illustrates how a 10Ω resistor along with a
10µF and a .01µF bypass capacitor should be connected to
each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10µF
.01µF
3.3V or 2.5V
.01µF
VDD
FIGURE 2. CRYSTAL INPUT INTERFACE
IDT™ / ICS™ LVDS CLOCK GENERATOR 7 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
2.5V or 3.3V
+
-
VDD
100 Ohm Differential Transmission Line
R1
100
LVDS_Driv er
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3.
The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTA L _ I N
XTA L _ O U T
.1uf
Rs
IDT™ / ICS™ LVDS CLOCK GENERATOR 8 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS844011 is: 2533
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
IDT™ / ICS™ LVDS CLOCK GENERATOR 9 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°0°8
aaa--01.0
IDT™ / ICS™ LVDS CLOCK GENERATOR 10 ICS844011AG REV A OCTOBER 6, 2006
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
TABLE 8. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
GA110448SCIA1104POSSTdael8ebutC°07otC°0
TGA110448SCIA1104POSSTdael8leer&epat0052C°07otC°0
FLGA110448SCIDBTPOSST"eerF-daeL"dael8ebutC°07otC°0
TFLGA110448SCIDBTPOSST"eerF-daeL"dael8leer&epat0052C°07otC°0
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
Innovate with IDT and accelerate your future networks. Contact:
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For Sales
800-345-7015
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For Tech Support
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Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS844011
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY
