Microchip PCD8572 1K (128 X 8) Serial Electrically Erasable PROM FEATURES Organization as 128 bytes (128 x 8} Two wire serial interface bus 5 volt only operation + Compatible with the l?C bus + Fully TTL compatible inputs and outputs Unlimited read access ESD Protection: Inputs are designed to meet 1.0kV per test method 3015.1, MIL-STD 883 Highly reliable N-Channel SNOS technology Designed for 10 year data retention after 10,000 read/write cycles per word * 8-pin DIP package Available for extended temperature ranges: Commercial: 0 C to 70 C industrial: -40 C to 85 C DESCRIPTION The PCD8572 is a 1K EEPROM manufactured using Microchip Technology's highly reliable SNOS technol- ogy. The key features of this device are its +5 volt only operation and inter-integrated circuit (I?C) bus compati- bility. This revotutionary bus provides the facilities of a local area network within a single system or equipment. Each IC serves as both transmitter and receiver in the synchronous data transfer of up to 100K bits per second. The use of I?C compatible devices make possible modular circuit design with up to 600 feet of separation allowable between IC's (400pf maximum bus capacitance). Chip select is accomplished by means of the three address inputs AO, A1 and A2. Each of these inputs must be connected externally to either +5V or GND and each chip is then selected through software by placing its 3- bit chip select address on the serial data input line (SDA) at the appropriate time in the bus protocol. Up to eight PCD8572s may be connected to the I?C bus. PIN CONFIGURATION WT ao [1 8 (1) vec ai C2 7) Rc a2 C3 6 J set vss C]4 5 CJ soa BLOCK DIAGRAM HIGH VOLTAGELJ ERASE/WRITE L ac MULTIPLIER CONTROL ADDR. POINTER SENSE AMPS DATA LATCHES SCL SDA SHIFT REG. ADDRESS COMPARATOR TT VeaLo> AO Al A2 Vssoe 1989 Microchip Technology Inc. 0$20016E-1PCD8572 ELECTRICAL CHARACTERISTICS Maximum Ratings* All inputs and outputs w.r.t. Vss ... ...-0.3V to +7.0V Voltage on any input pin........... Vss -0.8 to Vcc +0.8V Storage temperature (unpowered and without data re- TOMRION) oo. ecceeseceeetecsnestessteneeeees -65C to +150C Ambient operating temperature with power applied oo... eee -65C to +125C Current into any input pin .... 1004 (max.) Output SINK CUTTONt ...... ee cccsesaceeeteeees 3 mA (max.) Soldering temperature of leads (10 S@ECONAS) oo. eeeccscetecssesseesseeseeessoeesstesees +300C ESD protection on all pins .................. 1.0kV (typical) Notice: Strasses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TABLE Name Function AO, A1, A2 Chip address Inputs Vss Ground SDA Serial Data/Address, Input/Output SCL Serial Clock Input RC Time Constant Network Input Vcc +5V Power Supply DC CHARACTERISTICS Veco = +5V+10% Vss = OV (GND) Commercial (C): Tamb = 0C to 70C Industrial (1): Tamb = -40C to 85C Parameter Sym Min Typ Max Units Conditions Operating Supply Current READ Mode IccR _ 15 _- mA Operating Supply Current WRITE/ERASE Mode lccw _ 15 _ mA Operating supply current STANDBY Mode Ieco _ 12 = mA Input Leakage Current (AO, A1, A2, SCL Pins) ts _ _- 1 HA Output Leakage Current HIGH loH - _- 1 pA SCL Input and SDA Input/ Output Pins: HIGH Level Input Voltage VIH 3.0 _ Vcc+0.8 Vv Low Level input Voltage Vit -0.3 _ 1.5 Vv Low Level Output Voltage VoL _ - 0.4 Vv lol =3 mA Vcc = 4.5V AO, A1, A2, Pins: High Level Input Voltage VIH Vcc-0.5 = Voc+0.5 Vv Low Level Input Voltage VIL 0.3 05 Vv DS20016E-2 1-162 1989 Microchip Technology Inc.PCD8572 AC CHARACTERISTICS Parameter Sym Min Typ Max Units | Conditions SCL Clock Frequency fs 0 _ 100 kHz The LOW Period of the Clock tLlow 4.7 _ _ us The HIGH Period of the Clock tHIGH 4.0 _ _ us SDA and SCL Rise Time tr _ _ 1 ps SDA and SCL Fall Time tr 300 Hs START condition Hold Time. After this period the first clock pulse is generated. tHD;STA 4.0 _ _ ys Setup Time for Start Condition (Only relevant for a repeated start condition) tSU:STA 4.7 _ _ BS Data Setup Time tSU:DAT 250 _ _ ns Data Hold Time for I?C Devices tHD;DAT 0 _ us See note 2 STOP Condition Setup Time {Su:STO 4.7 _ _ ps Time the bus must be free before a new transmission can start tBUF 47 _ _ us Erase/Write Cycle Time (per word)! Tew 20 30 100 ms C=2500pf, R=10K Endurance (Number of erase/write cycles) New _ 10,000 |EWcycles| Per byte Data Retention Time Ts 10 _ _ years Input Capacitance on SCL, SDA Ci _ _ 7 pf Noise Suppression Time Constant at SCL and SDA input TI 0.25; 05 1.0 us NOTES: (1) All vaiues referred to ViH and Vit levels. (2) Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300ns) of the falling edge of SCL. 1989 Microchip Technology Inc. 1-163 DS20016E-3PCD8572 FUNCTIONAL DESCRIPTION PC Bus Interface Figure 1 below shows the typical manner in which the PCD8572 is interfaced to the I?C bus. For purposes of illustration chip address A2,A1, AO = 100 is shown. This is only one of eight possible addresses since up to eight PCD8572s can be connected ta the [?C bus of a single system. The erase/write cycle time of this device TEw is determined by an external resistor and capacitor: Rew and Cew . NOTE: When the PCD8572 is not used in an 1C bus configu- ration, pull-up resistors for SDA and SCL are required. FIGURE 1 - TYPICAL INTERFACE +5V Ad=0 Al=0 A2=1 racteristi fthe ?CB The C bus is intended for communication between different ICs. This serial bus consists of two bi-direc- tional lines: one for data signals (SDA) and one for clock signats (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as contro! signals. Accordingly, the following bus conditions have been defined: BUS NOT BUSY Both data and clock lines remain HIGH. START DATA TRANSFER Achange in the state of the data line, from HIGH toLOW, while the clock is HIGH, defines the START condition. STOP DATA TRANSFER A change in the state of the data line, from LOW to HIGH, while the clock is HIGH, defines the STOP condition. DATA VALID The state of the data line represents valid data when. after a start condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line may be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop Condition; the number of the data bytes, transterred between the start and stop conditions is limited to two bytes in the ERASE + WRITE mode and is not limited in the READ mode. The information is transmitted bytewise and each receiver acknowledges with a ninth bit of which must be provided by the user Within the I?C bus specifications a low speed mode (2 kHz ciock rate) and a high speed mode (100 kHz clock rate) are defined. The PCD8572 works in both modes. By definition a device that gives out a message is called transmitter, the receiving device that controls the message is called receiver. The device that controls the message is called master. The devices that are controlled by the master are called slaves. ACKNOW Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to gener- ate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that had been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the high period of the acknowledge related clock pulse. Of course setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the siave. In this case the transmitter must leave the data line HIGH to enabie the master to generate the STOP condition. DS20016E-4 1989 Microchip Technology Inc.PCD8572 FIGURE 2A - DATA TRANSFER SEQUENCE ON THE SERIAL BUS CLOCK fake HIGH \__ L Low DATA 4 t HIGH XL / x \ lA START CONDITION DATALINE CHANGE OF. SOP STABLE DATA ALLOWED CONDITION DATA VALID FIGURE 2B - ACKNOWLEDGEMENT CLOCK PULSE FOR START CONDITION ACKNOWLEDGEMENT SCLK FROM MASTER 1 1 2 8 8 1 0 1 DATA x DATA2 =X "x paras / ACKNOWLEDGEMENT: An extra clock pulse is generated during which the receiver pulls the data line LOW. FIGURE 2C - BUS FIMING REQUIREMENTS tr tHiGH tsu'sto! SCL SDA >| tsu:DAT 1 tHD-DaT (SA! 4 = START, P = STOP 1989 Microchip Technology Inc. DS20016E-5 1-165PCD8572 I ri A thorough description of the inter-IC bus specification appears in the Philips document number TVE 81107 which is available upon request from Microchip Technol- ogy. The following is a condensed description of each mode of operation. CHIP ADDRESS (SLAVE ADDRESS) ALLOCATION The three chip address inputs of each PCD8572 (A2, A1, AQ) must be externally connected to either +5V (Vcc) of ground (Vss) thereby assigning to each PCD8572 a unique three-bit chip address. Up to eight PCD8572s may be connected to the I?C bus. Chip selection is then accomplished through software by setting the least significant three bits of the slave ad- dress to the corresponding hard-wired logic levels of the selected PCD8572. The correct bus protocol shown in Figure 3. FIGURE 3 - SLAVE ADDRESS ALLOCATION START T_T _Tt T_T | | SLAVE ADDRESS po 7 / f \ Z N AAW it 1 0 1 0 A2 7 Al AQ ERASEWRITE MODE In this mode the master transmitter transmits to the PCD8572 slave receiver. Bus protocol is shown in Figure 4. Following the START condition and siave address a logic 0 (R/W=0) is placed on the bus and indicates to the addressed device that word address AN will follow and is to be written to the on-chip address pointer. The data word to be written to the nonvolatile memory is strobed in next, and is loaded in the address pointer. A second data byte may be strobed in following this the address pointer. In the erase/write mode no more than two successive data bytes may be strobed into the PCD8572. The PCD8572 slave receiver will send an acknowledge bit to the master transmitter after it has received the slave address and again after it has received the word address and each data byte. After the STOP condition the erase/write cycle starts. Its duration is approximately 20ms. if only one byte is written, and 40ms. if two bytes are written. READ MODE In this mode the master reads the PCD8572 slave after setting the slave address. See Figure 5. Following the write mode control bit (R/W=0) and the acknowledge bit, the word address An is written to the on-chip address pointer. Next, the START condition and slave address are repeated followed by the READ mode control bit (R/ W=1). At this point the master transmitter becomes the master receiver and the PCD8572 slave receiver be- comes the slave transmitter. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The PCD8572 slave transmitter will now piace the data byte at address AN-+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to AN+2. This cycle of reading consecutive addresses will con- tinue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ mode may also be implemented whereby the master reads the PCD8572 slave without first writing to the (Volatile) address pointer. The first address that is read is the last one stored in the pointer. See Figure 6. FIGURE 4 - ERASE + WRITE MODE ACKNOWLEDGES FROM SLAVE TEUETT TEP START o > WORD ADDRESS botitis SLAVE ADDRESS pitiitt TUTPrriryd A DATA Lp A DATA A} STOP Le t RW AUTO INCREMENT WORD ADDRESS eS DS20016E-6 1-166 1989 Microchip Technology Inc.PCD8572 FIGURE 5 - READ MODE ACKNOWLEDGES FROM SLAVE ACKNOWLEDGES FROM MASTER TTTttrt PRTTri ty Triretl TYTTTTR! TTTTTTy 3 SLAVE WORD START ADDRESS OyA ADDRESS AISTART SLAVE OA DATA Ajeee e886 DATA A] STOP Piipidt pitti dEtiil putitil Petit tt aw At this moment, the master |: NBYTES J transmitter becomes tne Ww LAST BYTE master recewer and the AUTO INCREMENT PC08572 slave receiver WORD ADDRESS becomes the transmitter FIGURE 6 - ALTERNATE READ MODE ACKNOWLEDGE ACKNOWLEDGE NO ACKNOWLEDGE FROM MASTER EROM SLAVE FROM MASTER BEFORE A STOP CONDITION Prrerdt Prrerdg PUTT dd SLAVE START ADDRESS tA DATA A DATA x] STOP fp bt tL PoE y by put bij A RAW LL. wavres LAST BYTE AUTO INCREMENT WORD ADDRESS ED 1989 Microchip Technology Inc. 1-167 DS20016E-7PCD8572 SALES AND SUPPORT To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NUMBERS PCD8572 -1/P PACKAGE TEMPERATURE RANGE DEVICE PCD8572 J P Blank I CERDIP PLASTIC DIP Oo Ctao 70C -40 C to 85 C 1K SNOS SERIAL EEPROM DS20016E-8 1-168 1989 Microchip Technology Inc.