100336PCX - Fairchild Semiconductor

August 1989

Revised August 2000

100336 Low Power 4-Stage Counter/Shift Register

100336

Low Power 4-Stage Counter/Shift Regist er

General Description

The 100336 operates as either a modulo-16 up/down

counter or as a 4-bit bidirectional shift register. Three

Select (Sn) inputs determine the mode of operation, as

shown in the Function Select table. Two Count Enable

(CEP, CET) inputs are provided for ease of cascading in

multistage counters. One Count Enable (CET) input also

doubles as a Serial Data (D0) input for shift-up operation.

For shift-down operation, D3 is the Serial Data input. In

counting operations the Terminal Count (TC) output goes

LOW when the counter reaches 15 in the count/up mode or

0 (zero) in the count/down mode. In the shift modes, the TC

output repeats the Q3 output. The dual nature of this TC/Q3

output and the D0/CET input means that one interconne c-

tion from on e stage to th e next hig her stage serve s as the

link for multistage counting or shift-up operation. The indi-

vidual Pre set (Pn) inputs ar e used to enter data in para llel

or to pre set the coun ter in program mable counter applica-

tions. A HI GH signal on the Mas ter Reset (M R) inp ut over-

rides all other inputs and asynchronously clears the flip-

flops. In ad dition, a synchronou s clear is provided, as well

as a c omplement fu nction wh ich s ynchron ously i nverts the

contents of the flip-flops. All inputs have 50 kΩ pull-down

resistors.

Features

■40% power reduction of the 100136

■2000V ESD protection

■Pin/function compatible with 100136

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

Ordering Code:

Devices also available in Tape and Reel. S pecify by ap pending th e s uffix let t er “X” to the o rdering c ode.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Logic Symbol

Order Number Package Number Package Description

100336SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100336PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100336QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100336QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

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Function Select Table Pin Descriptions

Truth Table

Q0 = LSB

1 = L if Q0–Q3 = LLLL

H if Q0–Q3 ≠ LLLL

2 = L if Q0–Q3 = HHHH

H if Q0–Q3 ≠ HHHH

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Don't Care



= LOW-to-HIGH Tr ansition

Note 1: Before the clock, TC is Q3

After the clock, TC is Q2

S2S1S0Function

L L L Parallel Load

L L H Complement

L H L Shift Left

L H H Shift Right

H L L Count Down

HLHClear

H H L Count Up

HHHHold

Pin Names Description

CP Clock Pulse Input

CEP Count Enable Parallel Input (Active LOW)

D0/CET Serial Data Input/Count Enable

Trickle Input (Active LOW)

S0–S2Select Inputs

MR Master Rese t Input

P0–P3Preset Inputs

D3Serial Data Input

TC Terminal Count Output

Q0–Q3Data Outputs

Q0–Q3Complementary Data Outputs

Inputs Outputs

MR S2S1S0CEP D0/CET D3CP Q3Q2Q1Q0TC Mode

LLLL X X X



P3P2P1P0L Preset (Parallel Load )

LLLHX X X



Q3Q2Q1Q0LInvert

LLHL X X X



D3Q3Q2Q1D3Shift to LSB

LLHHX X X



Q2Q1Q0D0Q3 (Note 1) Shift to MSB

LHLL L L X



(Q0–3) minus 1 1 Count Down

LHLL H L XXQ

3Q2Q1Q01 Count Down with CEP not active

LHLL X H XXQ

3Q2Q1Q0H Count Down with CET not active

LHLH X X X



LLLL H Clear

LHHL L L X



(Q0–3) plus 1 2 Count Up

LHHL H L XXQ

3Q2Q1Q02 Count Up with CEP not active

LHHL X H XXQ

3Q2Q1Q0H Count Up with CET not activ e

L HHH X X X XQ

3Q2Q1Q0HHold

HLLL X X XXLLLL L

HLLH X X XXLLLL L

HLHL X X XXLLLL L

H L H H X X X X L L L L L Asynchronous

H H L L X L X X L L L L L Master Reset

HHLL X H XXLLLL H

HHLH X X XXLLLL H

HHHL X X XXLLLL H

H HHH X X X X L L L L H

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Logic Diagram

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Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are those values beyond which the

device may be damaged or have its useful life impaired. Functional opera-

tion under these conditions is not implied.

Note 3: ESD te s ti ng c onforms t o M I L-STD-8 83, Meth od 3015.

Commercial Version

DC Electrical Characteristics (Note 4)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 4: The specified limits represe nt the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

Storage Temper atur e (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltag e (DC) VEE to +0.5V

Output Curren t (DC Output HIGH) −50 mA

ESD (Not e 3) ≥ 2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltag e (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Vo ltage −1025 −955 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

VIH Input HIGH V olta ge −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW V olta ge −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 µAV

IN = VIL (Min)

IIH Input HIGH Current 240 µAV

IN = VIH (Max)

IEE Power Supply Current −165 −80 Inputs Open

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Commercial Version (Continued)

DIP AC Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 5: The propag at ion delay s pec ified is for s ingle output switc hing. Del ay s m ay v ary up to 250 ps w it h m ultiple out puts switc hing.

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

fSHIFT Shift Frequency 300 300 300 MHz Figures 2, 3

tPLH Propagation Delay 1.00 2.00 1.00 2.00 1.00 2.00 ns Figures 1, 3

tPHL CP to Qn, Qn(Note 5)

tPLH Propagation Delay 2.10 3.50 2.10 3.50 2.10 3.70 ns Figures 1, 7, 8

tPHL CP to TC (Shift) (Note 5)

tPLH Propagation Delay 2.40 4.40 2.40 4.40 2.60 4.70 ns Figures 1, 9

tPHL CP to TC (Count) (Note 5)

tPLH Propagation Delay 1.40 2.50 1.40 2.50 1.50 2.60 ns Figures 1, 4

tPHL MR to Qn, Qn(Note 5)

tPLH Propagation Delay 2.80 5.10 2.90 5.20 3.10 5.50 ns Figures 1, 12

tPHL MR to TC (Count) (Note 5)

tPHL Propagation Delay 2.40 4.00 2.40 4.00 2.50 4.10 ns Figures 1, 10, 11

MR to TC (Shift) (Note 5)

tPLH Propagation Delay 1.80 3.10 1.80 3.10 1.90 3.30 ns

tPHL D0/CET to TC Figures 1, 5

tPLH Propagation Delay 1.90 4.10 1.90 4.10 2.10 4.40 ns (Note 5)

tPHL Sn to TC

tTLH Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D31.00 1.00 1.00

Pn1.50 1.50 1.50

D0/CET 1.30 1.30 1.30 ns Figures 6, 4

CEP 1.40 1.40 1.40

Sn3.40 3.40 3.40

MR (Release Time) 2.60 2.60 2.60

tHHold Time

D30.40 0.40 0.40

Pn0.30 0.30 0.30 ns Figure 6

D0/CET 0.30 0.30 0.30

CEP 0.20 0.20 0.20

Sn0.10 0.10 0.10

tPW(H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4

CP, MR

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SOIC and PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 6: The prop agation delay specif ied is for single output switching. Delays may v ary up to 250 ps w ith m ult iple outputs switc hing.

Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged d evice . The sp ecificatio ns appl y to an y output s swit ching in th e sam e direc tion eithe r HIGH- to-LOW (tOSHL), or LOW-to-H IGH (tOSLH), or in opp osite

direc ti ons both H L and LH (tOST). Parameters tOST and tps guara nt eed by des ign

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

fSHIFT Shift Frequency 350 350 350 MHz Figures 2, 3

tPLH Propagation Delay 1.00 1.80 1.00 1.80 1.00 1.80 ns Figure s 1, 2

tPHL CP to Qn, Qn(Note 6)

tPLH Propagation Delay 2.10 3.30 2.10 3.30 2.10 3.50 ns Figure s 1, 7, 8

tPHL CP to TC (Shift) (Note 6)

tPLH Propagation Delay 2.40 4.20 2.40 4.20 2.60 4.50 ns Figure s 1, 9

tPHL CP to TC (Count) (Note 6)

tPLH Propagation Delay 1.40 2.30 1.40 2.30 1.50 2.40 ns Figure s 1, 4

tPHL MR to Qn, Qn(Note 6)

tPLH Propagation Delay 2.80 4.90 2.90 5.00 3.10 5.30 ns Figure s 1, 12

tPHL MR to TC (Count) (Note 6)

tPHL Propagation Delay 2.40 3.80 2.40 3.80 2.50 3.90 ns Figures 1, 10, 11

MR to TC (Shift) (Note 6)

tPLH Propagation Delay 1.80 2.90 1.80 2.90 1.90 3.10 ns

tPHL D0/CET to TC Figures 1, 5

tPLH Propagation Delay 1.90 3.90 1.90 3.90 2.10 4.20 ns (Note 6)

tPHL Sn to TC

tTLH Transition Time 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D30.90 0.90 0.90

Pn1.40 1.40 1.40

ns Figures 4, 6

D0/CET 1.20 1.20 1.20

CEP 1.30 1.30 1.30

Sn3.30 3.30 3.30

MR (Release Time) 2.50 2.50 2.50

tHHold Time

D30.30 0.30 0.30

Pn0.20 0.20 0.20 ns Figure 6

D0/CET 0.20 0.20 0.20

CEP 0.10 0.10 0.10

Sn0.00 0.00 0.00

tPW(H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4

CP, MR

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 200 200 200 ps (Note 7)

Clock to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 200 200 200 ps (Note 7)

Clock to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 230 230 230 ps (Note 7)

Clock to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 245 245 245 ps (Note 7)

Clock to Output Path

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Industri a l Versi on

PLCC DC Electrical Characteristics (Note 8)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C

Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 9: The propag at ion delay s pec ified is for s ingle output switc hing. Del ay s m ay v ary up to 250 ps w it h m ultiple out puts switc hing.

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Vo ltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1565 −1610 mV or VIL (Max) 50Ω to −2.0V

VIH Input HIGH V olta ge −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 0.50 µAV

IN = VIL (Min)

IIH Input HIGH Current 240 240 µAV

IN = VIH (Max)

IEE Power Supply Current −165 −75 −165 −80 mA Inputs Open

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

MinMaxMinMaxMinMax

fSHIFT Shift Frequency 325 350 350 MHz Figures 2, 3

tPLH Propagation Delay 1.00 1.80 1.00 1.80 1.00 1.80 ns Figures 1, 3

tPHL CP to Qn, Qn(Note 9)

tPLH Propagation Delay 2.00 3.30 2.10 3.30 2.10 3.50 ns Figures 1, 7, 8

tPHL CP to TC (Shift) (Note 9)

tPLH Propagation Delay 2.40 4.20 2.40 4.20 2.60 4.50 ns Figures 1, 9

tPHL CP to TC (Count) (Note 9)

tPLH Propagation Delay 1.40 2.30 1.40 2.30 1.50 2.40 ns Figures 1, 4

tPHL MR to Qn, Qn(Note 9)

tPLH Propagation Delay 2.80 4.90 2.90 5.00 3.10 5.30 ns Figures 1, 12

tPHL MR to TC (Count) (Note 9)

tPHL Propagation Delay 2.40 3.80 2.40 3.80 2.50 3.90 ns Figures 1, 10, 11

MR to TC (Shift) (Note 9)

tPLH Propagation Delay 1.70 2.90 1.80 2.90 1.90 3.10 ns

tPHL D0/CET to TC Figures 1, 5

tPLH Propagation Delay 1.80 3.90 1.90 3.90 2.10 4.20 ns (Note 9)

tPHL Sn to TC

tTLH Transition Time 0.20 1.90 0.35 1.10 0.35 1.10 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D31.40 0.90 0.90

Pn1.70 1.40 1.40

ns Figure 6

D0/CET 1.80 1.20 1.20

CEP 1.80 1.30 1.30

Sn3.30 3.30 3.30

MR (Release Time) 2 .60 2.50 2.50

tHHold Time

D30.90 0.30 0.30

Pn1.00 0.20 0.20 ns Figure 6D0/CET 0.70 0.20 0.20

CEP 0.60 0.10 0.10

Sn0.00 0.00 0.00

tPW(H) Pulse Width HIGH CP, MR 2.20 2.00 2.00 ns Figures 3, 4

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Test Circuitry

Notes:

VCC, VCCA = +2V, VEE = −2.5V

L1, L2 and L3 = equal lengt h 50Ω impedance lines

RT = 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to VCC and VEE

All unus ed out put s are loade d w it h 50Ω to G ND

CL = Fixture and stray capacita nc e ≤ 3 pF

FIGURE 1. AC Test Circuit

Notes:

For shift right mode, +1.05V is applied at S0.

The feedback path from output to input should be as short as possible.

FIGURE 2. Shif t Freque ncy Test Circuit (Shift Left)

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Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

FIGURE 4. Propagation Delay (Reset)

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Switching Waveforms (Continued)

FIGURE 5. Propagation Delay (Serial Data, Selects)

Notes:

tS is the minimum time before the transition of the clock that information must be present at the data input.

tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.

FIGURE 6. Setup and Hold Time

Note: Shift Right Mode; S0 = H, S 1 = H, S2 = L.

FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode)

Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.

FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode)

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Switching Waveforms (Continued)

Note:

*Decimal representation of binary outputs.

Count Up: S0 = L, S1 = H, S2 = H; Count Down: S0 = L, S1 = L, S2 = H.

Measuremen t tak en at 50% point of wav eform.

FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)

Note: Shift Right Mode; S 0 = H, S1 = H, S2 = L.

FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)

Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.

FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)

Note:

*Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H.

Note:

*Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H.

FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)

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Applications

3-Stage Divider, Preset Count Down Mod e

Note: If S0 = S1 = S2 = LOW, then TC = LOW

Slow Expansion Scheme

Fast Expansion Scheme

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100336 Low Power 4-Stage Counter/Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r systems a re devices or syste ms

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical com ponent in any com ponen t of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.