ie 1IS41C16128 128K x16 (2-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES * Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs * Refresh Interval: 512 cycles/8 ms * Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden JEDEC standard pinout * Single +5V + 10% power supply * Byte Write and Byte Read operation via two CAS * Available in 40-pin SOJ and TSOP (Type II) * Industrial temperature available FUNCTIONAL BLOCK DIAGRAM AUGUST 1998 DESCRIPTION The/SS71S41C16128 is a 131,072 x 16-bit high-performance CMOS Dynamic Random Access Memory. The IS41016128 offers an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 256 random accesses within a single row with access cycle time as short as 12 ns per 16- bit word. The Byte Write control, of upper and lower byte, makes the IS41C 16128 ideal for use in 16-, 32-bit wide data bus systems. These features make the 1S41C16128 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The 1841016128 is packaged in a 40-pin 400-mil SOJ and TSOP (Type Il). OE WE LCAS >| CAS > WE > OE CLOCK CAS CONTROL WE CONTROL UCAS ] GENERATOR } LOGICS > LOGIC Oo y vy" Ras >} RAS) FG CLOCK GENERATOR sv DATA I/O BUS COLUMN DECODERS REFRESH [Ke COUNTER SENSE AMPLIFIERS V00-1/015 AA ADDRESS BUFFERS ROW DECODER AO-A8 DATA I/O BUFFERS MEMORY ARRAY 131,072 x 16 This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 _ KEY TIMING PARAMETERS Parameter -35 -40 -45 -50 -60 Max. RAS Access Time (trac) 35 ns 40 ns 45 ns 50 ns 60 ns Max. CAS Access Time (tcac) 10 ns 12 ns 13 ns 14 ns 15 ns Max. Column Address Access Time (taa) 18 ns 20 ns 22 ns 25 ns 30 ns Min. EDO Page Mode Cycle Time (trc) 12 ns 15 ns 17 ns 20 ns 25 ns Min. Read/Write Cycle Time (trc) 60 ns 75 ns 80 ns 90 ns 110 ns PIN CONFIGURATIONS 40-Pin TSOP (Type Il) 40-Pin SOJ Nf vec [1 @ 40-1] GND e~ voo [L]2 30-1] 015 vec (1 40] GND vo1 [3 381 vot4 voo Jj 2 391] 015 vo2 [Ly4 s7CD] 013 voi 3 38] vo14 vo3 [5 36] v012 vo2 [4 371] vo1s vec [6 351-11 GND vos 5 36[] 012 vo4 [[]7 341] voit vec [6 35] GND vos [[]8 33_I] vo10 vo4 7 34] vo11 vos [L]9 32_L] vog vo5 8 33] 010 vo7 [LT] 10 311] vos voe [9 32[] og vo7 [J 10 311] vos Ne O11 30] Nc Ne (11 sof T] NC | Ne [12 29] LCAS Ne [1] 2 2of 1] LCAS WE [| 13 28 [] UCAS we 18 asf 1] UCAS RAS [J 14 27[] OE RAS [| 14 27|_]] OE Ne TH 15 26-1) AB Ne [] 15 26] As ao [H16 ost T] A7 Ao [] 16 251] 47 at (117 os FT] AS At 17 24[] a6 a2 [18 o3T] AS A2 [] 18 23[] a5 A3 [L119 221] A4 a3 [] 19 22[] Ad vec [L] 20 21] GND vec [] 20 211] GND PIN DESCRIPTIONS A0-A8& Address Inputs /00-15 Data Inputs/Outputs Write Enable Output Enable Row Address Strobe | 2a] UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vec Power GND Ground NC No Connection Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/981S41C16128 __ TRUTH TABLE Function RAS LCAS UCAS WE OE Addresstritc 1/0 Standby H H H X X X High-Z Read: Word L L L H L ROW/COL Dout Read: Lower Byte L L H H L ROW/COL Lower Byte, Dout Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, Dout Write: Word (Early Write) L L L L Xx ROW/COL DIN Write: Lower Byte (Early Write) L L H L Xx ROW/COL Lower Byte, Din Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L Xx ROW/COL Lower Byte, High-Z Upper Byte, Din Read-Write" L L L H>L L>H ROW/COL Dour, Din EDO Page-Mode Read + 1stCycle: L Ho>L HoL H L ROW/COL Dout 2nd Cycle: =L H>L HL H L NA/COL Dout Any Cycle: = L L>H L>H H L NA/NA Dout EDO Page-Mode Write 1stCycle: L Ho>L HoL L Xx ROW/COL DIN 2nd Cycle: =L H>L HL L X NA/COL DIN EDO Page-Mode 1st Cycle: =L HoeL Holt Hol L>H ROW/COL Dour, Din Read-Write" 2nd Cycle: =L HoeL Holt Holt LOH NA/COL Dour, Din Hidden Refresh? Read L-H->L L L H L ROW/COL Dout Write L>H->L L L L X ROW/COL Dout RAS-Only Refresh L H H X X ROW/NA High-Z CBR Refresh H->L L L X X X High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS). Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 RE Functional Description The IS41C16128 is a CMOS DRAM optimized for high- speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 17 address bits. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits. The 1S41C16128 has two CAScontrols, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 128K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls 1/00 through I/O7 and UCAS controls 1/08 through 1/015. The IS41C16128 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the 1S$41C16128 both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tras time has expired. Anew cycle must not be initiated until the minimum precharge time tap, tcp has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time speci- fied by tak. Data Out becomes valid only when trac, taa, tcac and toea are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle Awrite cycleis initiated by the falling edge of CASand WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Refresh Cycle To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory. 1. Byclocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the ad- dressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 256 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycles falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. There- fore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write opera- tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the Vcc supply, an initial pause of 200 us is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with Vcc or be held at a valid ViH to avoid current surges. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 ABSOLUTE MAXIMUM RATINGS Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND 1.0 to +7.0 Vv Vcc Supply Voltage 1.0 to +7.0 Vv lout Output Current 50 mA Pb Power Dissipation 1 Ww TA Operation Temperature Com. 0 to +70 C Ind. 40 to +85 TsTG Storage Temperature 55 to +125 C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Min. Typ. Max. Unit Vcc Supply Voltage 4.5 5.0 5.5 Vv VIH Input High Voltage 2.4 Vvec+1.0 Vv ViL Input Low Voltage -1.0 _ +0.8 Vv TA Ambient Temperature Com. 0 _ +70 C Ind. 40 +85 CAPACITANCE) Symbol Parameter Max. Unit Cint Input Capacitance: A0-A8 5 pF Cin2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7 pF Clo Data Input/Output Capacitance: I/00-1/015 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vcc = 5.0V + 10%. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit iL Input Leakage Current Any input OV < Vin < 5.5V -10 10 LA Other inputs not under test = OV lio Output Leakage Current Output is disabled (Hi-Z) 10 10 LA OV < VouT < 5.5V VoH Output High Voltage Level loH = -2.5 mA 2.4 Vv VoL Output Low Voltage Level loL=+2.1 mA _ 0.4 Vv Ioct Stand-by Current: TTL RAS, LCAS, UCAS > Vin 2 mA Icc2 Stand-by Current: CMOS RAS, LCAS, UCAS = Vcc 0.2V 1 mA loc Operating Current: RAS, LCAS, UCAS, -35 230 mA Random Read/Write?#) Address Cycling, tac = tre (min.) -40 _ 130 Average Power Supply Current -45 _ 120 -50 _ 110 -60 _ 100 loca Operating Current: RAS = Vit, LCAS, UCAS, -35 220 mA EDO Page Mode@:#4) Cycling tec = tec (min.) -40 90 Average Power Supply Current -45 _ 85 -50 _ 80 -60 _ 70 loos Refresh Current: RAS Cycling, LCAS, UCAS = Vin -35 230 mA RAS-Only2) tac = tac (min.) -40 130 Average Power Supply Current -45 _ 120 -50 _ 100 -60 _ 100 loc6 Refresh Current: RAS, LCAS, UCAS Cycling -35 230 mA CBR@?5) tre = tre (min.) -40 _ 130 Average Power Supply Current -45 _ 120 -50 _ 100 -60 100 Notes: 1. An initial pause of 200 ps is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the trer refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98AC CHARACTERISTICS 2:34:5) (Recommended Operating Conditions unless otherwise noted.) IS41C16128 -35 -40 -45 -50 -60 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units tRe Random READ or WRITE Cycle Time 60 75 80 90 110 ns tRAC Access Time from RAS? 3% 40 4 5 60 ns toac Access Time from CAS:: #5) 10 12 - 13 14 15 ns TAA Access Time from Column-Address) 18 20 22 2 30 ns tRAS RAS Pulse Width 35 10K 40 10K 45 10K 50 10K 60 10K ns tap RAS Precharge Time 20 -- 2 2 3 4 nos tcas CAS Pulse Width 6 10K 6 10K 7 10K 8 10K 10 10K = os top CAS Precharge Time) 5 5 7 = 8 10 ns tcsH CAS Hold Time @" 3 400 45 50 60 ns taco RAS to CAS Delay Time. 20 11 28 17 2 18 32 619 36 20 45 ons tASR Row-Address Setup Time oO oO oO 0. 0. ns {RAH Row-Address Hold Time 6 6 7 - 8 10 ns tasc Column-Address Setup Time oO oO oO oO oO ns {CAH Column-Address Hold Time) 6 6 7 = 8 10 ns TAR Column-Address Hold Time 300 OC 300 OC 3 40 40 ns (referenced to RAS) {RAD RAS to Column-Address Delay Time 12 20 12 20 13 22 14. 25 15 30 ns {RAL Column-Address to RAS Lead Time 18 20 220 2a 300 ns trec RAS to CAS Precharge Time 0 0 0 0 0 os tas RAS Hold Time? 8 12 1 - 114 - 15 ns tez CAS to Output in Low-Z'"5.9 30 30 30 3 0 3 ns torp CAS to RAS Precharge Time") 5 5 5 5 5 ns top Output Disable Time"* 8.) 3 15 3 15 3 15 3. 15 3. 15 ns toe Output Enable Time": "9 10 10 12 15 15 ns toeHc = OEHIGH Hold Time from CAS HIGH 10 10 1 1 1 # os toEP OE HIGH Pulse Width 10 10 10 10 10 ns toes OE LOW to CAS HIGH Setup Time 5 5 5 5 5 ns trcs Read Command Setup Time: oO oO oO oO oO ns {RRH Read Command Hold Time 0 0 0 0 0 ns (referenced to RAS)" {RCH Read Command Hold Time 0 0 0 0 0 ns (referenced to CAS)": 17.20 twcH Write Command Hold Time"? 2? 5 OF 6 7 = 8 10 ns twcrR Write Command Hold Time 300 300 350 400 50 ns (referenced to RAS)" twp Write Command Pulse Width"? 5 OF 6 7 = 8 10 ns twez WE Pulse Widths to Disable Outputs 10 10 10 10 10 ns tRWL Write Command to RAS Lead Time? 8 12 13 14 15 ns tow. Write Command to CAS Lead Time"?2 8 12 13 14 15 ns twcs Write Command Setup Time"* "7.20 oO oO oO oO oO ns tOHR Data-in Hold Time (referenced to RAS) 30 300 35 400. 400. ns Integrated Silicon Solution, Inc. 7 PRELIMINARY DR002-1D 08/20/98IS41C16128 RE AC CHARACTERISTICS (Continued)":2345 (Recommended Operating Conditions unless otherwise noted.) 35 -40 45 -50 -60 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units tACH Column-Address Setup Time to CAS 15 15 15 15 15 ns Precharge during WRITE Cycle toeH OE Hold Time from WE during 8 8 8 1 15 ns READ-MODIFY-WRITE cycle tos Data-In Setup Time" 2) oO oO oO oO oO ns {DH Data-In Hold Time's: 2 6 6 7 = 8 = 10 ns trwe READ-MODIFY-WRITE Cycle Time 80 100 145 125 140 ns tawo RAS to WE Delay Time during 4 5 6 7 8: fs READ-MODIFY-WRITE Cycle) towo CAS to WE Delay Time" 2 3 3 3 8% ns tawo Column-Address to WE Delay Time 30 30 40. 420 49 ns tPc EDO Page Mode READ or WRITE 120 15 7 20 a ns Cycle Time) tRASP RAS Pulse Width in EDO Page Mode 35 100K 40 100K 45 100K 50 100K 60 100K = os tcPA Access Time from CAS Precharge") 2 23 2 27 34 ns tPRWC EDO Page Mode READ-WRITE 40. 45 46 47 56 ns Cycle Time) tcou Data Output Hold after CAS LOW 30 30 30 30 30 ns torr Output Buffer Turn-Off Delay from 3. 15 3. 15 3. 15 3. 15 3. 15 ns CAS or RAS(13:15:19, 29) tWHZ Output Disable Delay from WE 3. 15 3. 15 3. 15 3. 15 3. 15 ns tcicH _ Last CAS going LOW to First CAS 170 10 - 10 10 10 ns returning HIGH tcsR CAS Setup Time (CBR REFRESH) 8 10 10 10 10 ns tcHR CAS Hold Time (CBR REFRESH) 8 10 10 10 10 ns torp OE Setup Time prior to RAS during 0 0 0 0 0 ns HIDDEN REFRESH Cycle tREF Refresh Period (512 Cycles) 8 8 8 8 8 ms tr Transition Time (Rise or Fall):? 1 50 1 50 1 50 1 50 1 50 ns 8 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 Notes: 1. An initial pause of 200 ps is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the trer refresh requirement is exceeded. 2. VIH(MIN) and Vit (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and ViL (or between Vi_ and ViH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between ViH and Vi (or between ViL and ViH) ina monotonic manner. 4. If CAS and RAS = Vin, data output is High-Z. 5. If CAS = Vi, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that trcp < trcp (MAX). If taco is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcp exceeds the value shown. 8. Assumes thattrcp =trcp (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tcp. 10. Operation with the tacp (MAX) limit ensures that trac (MAX) can be met. taco (MAX) is specified as a reference point only; if taco is greater than the specified tacp (MAX) limit, access time is controlled exclusively by tcac. 11. Operation within the trap (MAX) limit ensures that tacb (MAX) can be met. trap (MAX) is specified as a reference point only; if trap is greater than the specified trap (MAX) limit, access time is controlled exclusively by taa. 12. Either tRcH or taRH must be satisfied for a READ cycle. 13. torr (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Vou or VoL. 14. twcs, trwo, tawo and tewp are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs > twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tawo = trwo (MIN), tawp = tawp (MIN) and tcewp 2 tcwp (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vin) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/00-I/O7 by LCAS and 1/08-1/015 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, aLATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. __ 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both top and toeH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after toEH is met. 19. The I/Os are in open during READ cycles once top or torr occur. 20. The first yCAS edge to transition LOW. 21. The last yCAS edge to transition HIGH. _ 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ- MODIFY-WRITE cycles. ___ 23. Last falling xCAS edge to first rising yCAS edge. 24. Last rising xCAS edge to next cycles last rising xCAS edge. 25. Last rising yCAS edge to first falling xCAS edge. 26. Each yCAS must meet minimum pulse width. 27. Last xCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. 9 PRELIMINARY DR002-1D 08/20/98IS41C16128 READ CYCLE RAS tRSH tCAS-tCL' UCAS/LCAS ADDRESS WE tOFF() 0 Valid Data Open = toD OE XY Undefined | Don't Care Note: 1. torr is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 EARLY WRITE CYCLE (OE = DON'T CARE) RAS tRSH tCAS-tCL UCAS/LCAS ADDRESS Column tCWL tRWL twCH twP WE k- tos tDH | V0 M Valid Data K Don't Care Integrated Silicon Solution, Inc. 11 PRELIMINARY DR002-1D 08/20/98IS41C16128 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS UCAS/LCAS ADDRESS /O Open tCAH Column tRWD Valid toD tCAS - tCLCH tRSH tbs tDH Open Valid DIN DOUT. tOEH xy Undefined Don't Care 12 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 EDO-PAGE-MODE READ CYCLE a tRASP | | _$_e+ {RP Dao reo RAS N AN |g _ tCSH | tPC(1) 1] }_ tRSH} _| tCRP4<] | tRCD m Lat-tCP-| [at tCAS-tm| baet-tC P| lat-tCAS, at tcP tCLCH tCLCH tCLCH UCASILCAS NY r N PL A at tAR > ~tRAD ~> a! TtRAL Se tASR {<1 tASCtate| beet ECAH tase at} eet tCAH TASC tee] beet tCAH ADDRESS x Row x Column x Column K Column X Row tRAH+<- t+ tRRH tRCS | tRCH <q_}$1 WE <a tAA+] att tAA4 <at tAA| |e TRAC. pe] nat tCPAm| [nt tCPAwm1 tCAC\aa > tCAC tae > tCAC a > tCLZ Lap tCOH 4p tCLZ aa att tOFF V0 Open _Q" Valid Data_ XS Vaid Data SS" Vaid Data J Open tOE -< tOEHC- as | at LOE tOES-}= Se tOD| | -1OES>| e- (OD _ y OE \ Z Z - tOEP m x) Undefined Don't Care Note: 1. tec can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tec specifications. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98 13IS41C16128 EDO-PAGE-MODE EARLY-WRITE CYCLE RAS tc UCAS/LCAS ADDRESS Column @) Valid Data Valid Data Valid Data 14 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) RAS tPc / tPRWC(1) tRSH tCAS, tCLCH tCAS, tCLCH tCAS, tCLCH UCAS/LCAS tRAL tCAH {CAH ADDRESS Column Column Column tRWL tCWL twP tAWD tcwD WE Vo OE RY Undefined Don't Care Note: 1. tec can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tec specifications. Integrated Silicon Solution, Inc. 15 PRELIMINARY DR002-1D 08/20/98EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) IS41C16128 RAS UCAS/LCAS ADDRESS oO -_ Valid Data Valid Data 16 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS UCAS/LCAS tRAD tRAH tASC. ADDRESS Column tRCS WE tWHZ tCLZ (QQ f??:_...00 Valid Data Open toD OE xy Undefined Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) je tRAS eT ..< tRP __ | RAS ON 7 \ tcRPla tRPC | UCAS/LCAS _/} \_/ tASR tl {RAH ADDRESS Row X Row 1/0 Open Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98 17IS41C16128 BR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) <t tRP pe| |og tRAS | |-< tRP -] |og___ tRAS >| f.S*:SSSSS RAS x N y N tRPC ~t| tCHR tCHR tCPj< UCAS/LCAS } /O Open w- [CSR | HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW) $ tRAS ____-] | <a tRP | tRASw- RAS i ye |}- tRSH Lt tCHR sJ tCRPw-| |~a tRCD y UCAS/LCAS - N jt tAR be] wt tRAD we| tRAL a tASR <aetRAH tASC- <te TCAH aie Lg me ADDRESS Row Column tAA ++| <t tRAC sa ~<a tC AC} tOFF(2) mt <0 tCLZ 0 <_= Open Valid Data }- Open= tOE >| el tOD <tm tORD OE \ VA RY Undefined | Don't Care Notes: 1. AHidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. torr is referenced from rising edge of RAS or CAS, whichever occurs last. 18 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 400-MIL PLASTIC SOJ Package Code: K N OoOoOoOoOo ooo oo ) Et : | { cm E ny wg _ Fp ___ | SEATING PLANE fp 4] coo A TORINO ye Al t E2 400-mil Plastic SOJ (K) Inches Millimeters Symbol Min Max Min Max Ref. Std. N 40 A 0.144 3.66 Al 0.025 0.66 A2 0.082 208 B 0.015 0.019 038 0.48 Notes; . - p 0026 0002 0466 08 Se ee ee tes acacia C = 0.007 0.013 0.18 0.33 3. Dimensions D and E1 do not include mold flash protru- D 1.020 1.030 2591 26.16 sions and should be measured from the bottom of the E 0.430 _0.450 10.92 11.43 4. Pern reads shall be planar with respect to one another E1 0.395 0.405 10.03 10.28 within 0.004 inches at the seating plane. E2 0.346 0.386 8.79 9.80 0.050 BSC 1.27 BSC Integrated Silicon Solution, Inc. 19 PRELIMINARY DR002-1D 08/20/98IS41C16128 PLASTIC TSOP Package Code: T (Type 2) N/2+1 N CO E 4H TOO UOUUUUU, N/2 _ A 0 SEATING PLANE A= fC | URAHARA HRAAAPY yy | OS rlele elles to >| leek wf fe A Plastic TSOP (T - Type Il) Inches Millimeters Symbol Min Max Min Max Notes: 1. Controlling dimension: inches, unless otherwise specified. Ref. Std. 2. BSC = Basic lead spacing between centers. N 40/44 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. A 0.039 0.047 1.00 1.20 4. Formed leads shall be planar with respect to one another Al 0.002 0.008 0.05 0.20 within 0.004 inches at the seating plane. B 0.012 0.016 0.30 0.40 C 0.0047 0.0083 0.12 0.21 D 0.721 0.729 18.313 18.517 E 0.462 0.470 11.735 11.938 e 0.0315 BSC 0.800 BSC H 0.396 0.404 10.058 10.262 L 0.017 0.023 0.432 0.584 a 0 5 0 5 20 Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98IS41C16128 ORDERING INFORMATION Commercial Range: 0C to 70C Speed (ns) Order Part No. Package 35 1S41C16128-35K 400-mil SOJ 35 1IS41C016128-35T 400-mil TSOP (Type 2) 40 1S41C16128-40K 400-mil SOJ 40 1S41C16128-40T 400-mil TSOP (Type 2) 45 1S41C16128-45K 400-mil SOJ 45 1S41C16128-45T 400-mil TSOP (Type 2) 50 1S41C016128-50K 400-mil SOJ 50 1S41C16128-50T 400-mil TSOP (Type 2) 60 1S41C16128-60K 400-mil SOJ 60 1S41C16128-60T 400-mil TSOP (Type 2) Industrial Range: 40C to 85C Speed (ns) Order Part No. Package 35 1S41C16128-35K| 400-mil SOJ 35 1S41C016128-35TI 400-mil TSOP (Type 2) 40 1S41C16128-40KI 400-mil SOJ 40 1S41C16128-40TI 400-mil TSOP (Type 2) 45 1S41C16128-45Kl 400-mil SOJ 45 1S41C16128-45TI 400-mil TSOP (Type 2) 50 1S41C16128-50KI 400-mil SOJ 50 1S41C16128-50TI 400-mil TSOP (Type 2) 60 1S41C16128-60KI 400-mil SOJ 60 1S41C16128-60TI 400-mil TSOP (Type 2) . IE Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 email: sales@issi.com http://www.issi.com Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98 21