16-bit FCT with Bus Hold Cypress 16-bit FCT Logic Feature Bus Hold Introduction Bus Hold Eliminates Hold Time problems This application note answers the basic questions about Bus Hold. Namely, what is it, why have it, how is it implemented, how is it specified, how is it measured, and which Cypress FCT products have it? Hold time specifications can be violated when fast devices drive slower devices. The data may disappear before the (slow) device that is supposed to sample it can respond. However, if the fast device has Bus Hold on its inputs, its outputs will not change when the device driving it is "disabled," and the slow device that it is driving cannot have its hold time violated. What is Bus Hold? Bus Hold is the ability of either an input pin or an I/O pin to retain the last valid logic state (voltage level) after the source driving it either enters the high impedance state, or is removed. The Cypress FCT products that have Bus Hold have the letter "H" in their part number. The following functions are some examples of the devices with Bus Hold:; * CY74FCT162H244T 16-bit Buffer/Line Driver * CY74FCT162H245T 16-bit Transceiver (Trans.) * CY74FCT162H501T 18-bit Registered Trans. * CY74FCT162H952T 16-bit Registered Trans How is Bus Hold Implemented? The Bus Hold circuit is implemented, as illustrated in Figure 1 as two inverters and an NMOS transistor connected as a pass gate. The two inverters provide positive feedback and form a bistable element. The pass transistor insures that at power-on, the voltage level at the pad will be LOW. The inverters are "weak," with low W/L ratios, so that they can be easily over-driven by an external source. VCC Why Have Bus Hold? Bus Hold provides a valid logic level on an input pin so that (1) unused inputs do not have to be tied to ground or VCC, (2) pull-up resistors are not required when the bus is idle, and (3) the possibility of having hold time problems are avoided. Bus Hold applies only to data input or I/O pins. Pad Strapping of Unused Inputs If the gate inputs of NMOS transistors are left unconnected (i.e., open, or floating), within a few hundred milliseconds enough charge will accumulate on them to turn them on. They will stay at their threshold, in the linear region of operation, and amplify noise. In TTL compatible CMOS circuits like Cypress FCT, both the N-channel pull-down transistor and the P-channel pull-up transistor in the TTL to CMOS input buffer will be turned on. This will provide a current path from VCC to ground (0.8 mA) that wastes power, will amplify any input noise, and may cause the system to malfunction. For these reasons it is standard practice to tie unused inputs either to ground (preferred) or to VCC. Pull-up Resistors Eliminated "Floating inputs" may occur in a system where several entities time share a common bus, when none of them are driving the bus. It is standard practice to provide a HIGH logic level by connecting these inputs to VCC through 1 K to 10 K pull-up resistors. Using a circuit that has Bus Hold on its inputs eliminates the need for pull-up resistors, which reduces components, saves board space, saves power, improves system reliability, and reduces cost. Cypress Semiconductor Corporation * Figure 1. Bus Hold Implementation How is Bus Hold Specified? There are four minimum current specifications that define Bus Hold. Two are sustaining currents that the node must source or sink without changing state, and two are overdrive currents that will cause the node to change state. IBHL is defined as "Bus Hold LOW sustaining current." The Bus Hold circuit must sink at least this minimum LOW sustaining current at VIL max. IBHL is measured after lowering VIN to ground, and then raising it to VIL max. IBHH is defined as "Bus Hold HIGH sustaining current." The Bus Hold circuit must source at least this minimum HIGH sustaining current at VIH min. IBHH is measured after raising VIN to VCC and then lowering it to VIH min. IBHLO is defined as "Bus Hold LOW overdrive current." An external driver must source at least IBHLO to switch the node from LOW to HIGH. IBHHO is defined as "Bus Hold HIGH overdrive current." An external driver must sink at least IBHHO to switch the node from HIGH to LOW. 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 1996 16-bit FCT with Bus Hold Current into a node is positive and current out of a node is negative. How are the Presence of Bus Hold Circuits Verified and Measured? The following paragraphs describe the procedures and measurements, performed on a production basis, to verify the functionality of Bus Hold, on all 16-bit Cypress FCT Logic products that have it. IBHL Measurement The VCC voltage is set to its minimum value (4.5V). Next, the input is grounded, which sets the bistable Bus Hold element to the logic LOW voltage level. The input voltage is then raised to VIN minimum (0.8V), and IBHL (+50 microamperes) is measured. The test verifies that the Bus hold circuit can sink at least IBHL at VIL (max.) and not change state. IBHH Measurement The VCC voltage is set to its minimum value (4.5V). Next, the input is raised to VCC, which sets the bistable Bus Hold ele- ment to the logic HIGH voltage level. The input voltage is then lowered to VIN maximum (2V), and IBHH (-50 microamperes) is measured. The test verifies that the Bus Hold circuit can source at least IBHH at VIL (max.) and not change state. IBHLO Measurement The VCC voltage is set to its maximum value (5.5V). Next, the input is grounded, which sets the bistable Bus Hold element to the logic LOW voltage level. The input voltage is then raised to VIN maximum (2V), and IBHLO (+500 microamperes) is measured. The test verifies that the external driver must source at least IBHLO to switch the node from LOW to HIGH. IBHHO Measurement The VCC voltage is set to its maximum value (5.5V). Next, the input is raised to VCC, which sets the bistable Bus Hold element to the logic HIGH voltage level. The input voltage is then lowered to VIN minimum (0.8V), and IBHHO (-500 microamperes) is measured. The test verifies that the external driver must sink at least IBHHO to switch the node from HIGH to LOW. (c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.