16-bit FCT with Bus Hold
Cypress Semiconductor Corporation • 3901 North First Street • San Jo se • CA 95134 • 408-943-2600
October 1996
Cypres s 1 6-bit FCT Logic Fe ature Bus Hold
Introduction
This application note answers the basic questions about Bus
Hold. Namely, what is it, why ha ve it, how is it implemented,
how is it specified, how is it measured, and which Cypress
FCT products have it?
What is Bus Hold?
Bus Hold is the ability of either an input pin or an I/O pin to
retain the last valid logic state (voltage level) after the source
driving it either enters the high impedance state, or is re-
moved.
The Cypress FCT products that have Bus Hold have th e lette r
“H” in their part number. The following functions are some
examples of the devices wit h Bus Hold:;
• CY74FCT162H244T 16-bit Bu ffer/Line Driver
• CY74FCT162H245T 16-bit Transceiver (Trans.)
• CY74FCT162H501T 18-bit Registered Trans.
• CY74FCT162H952T 16-bit R egistered Trans
Why Have Bus Hold?
Bus Hold provides a valid logi c level on an input pin so that
(1) unused inputs do not have to be t ied to ground or VCC, (2)
pull-up resistors are not required when the b us is idle, and (3)
the possibility of having hold time problems are avoided. Bus
Hold applies only to data input or I/O pins.
Strappin g of U nused Inputs
If the gate in put s of NMOS transistors are left unconnected
(i.e., open, or floating), within a few hundred milliseconds
enough charge will ac cumulate on them to turn them on. They
will stay at their threshold, in the linear region of operation,
and am plify n oise. In TT L compatible CMOS circ uits like Cy-
press FCT, both the N-channel pull-down transistor and the
P-channel pull- up tr a nsistor i n the TTL to CMOS input buffer
will be turned on. This will provide a current path from VCC to
ground (0.8 mA) that wastes power, will amplify any input
noise, and may cause the system to malfunction. For these
reasons it is standard practice to tie unused inputs eit her to
ground (pref erred) or to VCC.
Pull-up Resistors Elimi nated
“Floating inputs” may occur in a system where several entities
ti me sha re a c ommon bu s , when none of them are driving the
bus. It is standard practice to provide a HIGH logic level by
connecting thes e inputs to VCC through 1 KΩ to 10 KΩ pull-up
resistors.
Using a circuit that has Bus Hold on its inputs eliminate s t he
need for pull-up resistors, which reduces components, saves
board space, saves power, improves system reliability, and
reduces cost.
Bus Hold Eliminates Hold Time problems
Hold time specifications can be violated when fast devices
drive slower devices. The data may disappear before the
(slow) device that is supposed to sample it can respond. How-
ever, if the f a st device has Bus Hold on its inputs, its outputs
will not change when the device driving it is “disabled,” and
the slow device that it is driving cannot have its hold time
violated.
How is Bus Hold Implemented?
The Bus Hold circuit is implemented, as illustrated in
Figure
1
as two inverters and an NMOS transistor connected as a
pass gate. The two inverters provide positive feedback and
form a bistable element. The pass transistor insures that at
power-on, the voltage level at the pad will be LOW. The in-
verters ar e “weak,” wit h low W/L ratios, so th at they can b e
easily over-driven by an external source.
How is Bus Hold Specified?
There are four minimum current specifications that define Bus
Hold. Two are sustaining currents that the node must source
or sink wi thout changing state, and two are overdrive currents
th at will cause the node to change state.
IBHL is defined as “Bus Hold LOW sustaining current.” The
Bus Hold circuit must sink at least this minimum LOW sus-
taining current at VIL max. IBHL is measu red a fter lowering VIN
to ground, and then raising it to VIL max.
IBHH is defined as “Bus Hold HIGH sustaining current.” The
Bus Hold circuit must s ource at least this minimum HIGH sus-
taining current at VIH min. I BHH is measured after raising V IN
to VCC and then lowering it to VIH min.
IBHLO is defined as “Bus Hold LOW overdrive current.” An
external driver must source at least IBHLO to switch the nod e
from LO W t o HIGH.
IBHHO is defined as “Bus Hold HIGH overdrive current.” An
external driver must sink at least IBHHO to switch the node
from HIGH to LOW.
Figur e 1. Bus Hold Implem entati on
VCC
Pad
16-bi t FCT with Bus Hold
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibil ity for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semicondu ctor product. Nor does it convey o r im ply an y licens e under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in signifi cant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Current into a node is positive and current out of a node is
negative.
How are the Presence of Bus Hold
Circuits Verified and Measured?
The fo llowing paragraphs describe the procedures and mea-
surements, performed on a production basis, to verify the
functionality of Bus Hold, on all 16-bit Cypress FCT Logic
product s that have it.
I
BHL
Measurem ent
The VCC voltage is set to its minimum value (4.5V). Next, the
input is grounded, which s ets the bistable Bus Hold element
to the logic LOW voltage level. The input voltage is then
raised to VIN minimum (0.8V), and IBHL (+50 microamperes)
is measured. The test verifies that the Bus hold circuit can
sink at least IBHL at VIL (max.) and not change state.
I
BHH
Measurem ent
The VCC voltage is set to its minimum value (4.5V). Next, the
input is raised to VCC, which sets the bist able Bus Hold ele-
ment to the logic HIGH voltage level. The inp ut v oltage is then
lowere d to V IN maximum (2V), and IBHH (-50 microamperes)
is measured. The test verifies that the Bus Hold circuit can
source at least IBHH at VIL (max.) and not change state.
I
BHLO
Measurement
The VCC voltage is set to its maximum value (5.5V). Next, the
input is grounded, which sets the bista ble Bus Hold element
to the logic LOW voltage level. The input voltage is then
raise d to VIN maximum (2V), and IBHLO (+500 microamperes)
is measured. The test verifies that the external driver must
source at least IBHLO to switch the node fr om LOW to HI GH.
I
BHHO
Measurement
The VCC voltage is set to its maximum value (5.5V). Next, the
input is raised to VCC, which sets the bistable B us Hold ele-
ment to the logic HIGH voltage level. The inp ut v oltage is then
lowered to VIN minimum (0.8V), and IBHHO (-500 microam-
peres) is measured. The te st verifies t hat the extern al driver
must sink at least IBHHO to switch the node from HIGH to
LOW.
