This is information on a product in full production.
October 2016 DocID026900 Rev 4 1/168
STM32F302xD STM32F302xE
ARM® Cortex®-M4 32b MCU+FPU, up to 512KB Flash, 64KB SRAM,
FSMC, 2 ADCs, 1 DAC ch., 4 comp, 2 Op-Amp, 2.0-3.6 V
Datasheet - production data
Features
•Core: ARM® Cortex®-M4 32-bit CPU with
72 MHz FPU, single-cycle multiplication and
HW division, DSP instruction and MPU
(memory protection unit)
•Operating conditions:
–V
DD, VDDA voltage range: 2.0 V to 3.6 V
•Memories
– Up to 512 Kbytes of Flash memory
– 64 Kbytes of SRAM, with HW parity check
implemented on the first 32 Kbytes.
– Flexible memory controller (FSMC) for
static memories, with four Chip Select
•CRC calculation unit
•Reset and supply management
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and
Standby
–V
BAT supply for RTC and backup registers
•Clock management
–4
to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
–Internal 40 kHz oscillator
•Up to 115 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
•Interconnect matrix
•12-channel DMA controller
•Two ADCs 0.20 µs (up to 18 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, separate analog
supply from 2.0 to 3.6 V
•One 12-bit DAC channels with analog supply
from 2.4 to 3.6 V
•Four ultra-fast rail-to-rail analog comparators
with analog supply from 2.0 to 3.6 V
•Two operational amplifiers that can be used in
PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V
•Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
•Up to 11 timers:
– One 32-bit timer and two 16-bit timers with
up to four IC/OC/PWM or pulse counter
and quadrature (incremental) encoder input
– One 16-bit 6-channel advanced-control
timers, with up to six PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with two IC/OCs, one
OCN/PWM, deadtime generation and
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent,
window)
– One SysTick timer: 24-bit downcounter
– One 16-bit basic timers to drive the DAC
•Calendar RTC with Alarm, periodic wakeup
from Stop/Standby
•Communication interfaces
– CAN interface (2.0B Active)
LQFP64 LQFP100 LQFP144
UFBGA100
(10 × 10 mm) (14 × 14 mm) (20 x 20 mm)
(7 x 7 mm)
WLCSP100
(
4.775 x 5.041 mm
)
www.st.com
STM32F302xD STM32F302xE
2/168 DocID026900 Rev 4
– Three I2C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from STOP
– Up to five USART/UARTs (ISO 7816
interface, LIN, IrDA, modem control)
– Up to four SPIs, 4 to 16 programmable bit
frames, two with multiplexed half/full duplex
I2S interface
– USB 2.0 full-speed interface with LPM
support
–Infrared transmitter
•SWD, Cortex®-M4 with FPU ETM, JTAG
•96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F302xD STM32F302RD, STM32F302VD, STM32F302ZD.
STM32F302xE STM32F302RE, STM32F302VE, STM32F302ZE.
DocID026900 Rev 4 3/168
STM32F302xD STM32F302xE Contents
5
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 ARM® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . 15
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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4/168 DocID026900 Rev 4
3.18.1 Advanced timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 25
3.18.3 Basic timers (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 28
3.22 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 29
3.23 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 29
3.24 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.25 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.26 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.28.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 69
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STM32F302xD STM32F302xE Contents
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6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 69
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.11 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.17 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.18 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.19 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.22 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.3 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.5 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 163
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
List of tables STM32F302xD STM32F302xE
6/168 DocID026900 Rev 4
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32F302xD/E family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . 13
Table 3. External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. STM32F302xD/E peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. STM32F302xD/E I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. STM32F302xD/E SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Capacitive sensing GPIOs available on STM32F302xD/E devices . . . . . . . . . . . . . . . . . . 31
Table 11. Number of capacitive sensing channels available on
STM32F302xD/E devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13. STM32F302xD/E pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. STM32F302xD/E alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Memory map, peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 19. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 20. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 21. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 22. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 23. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 24. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 71
Table 26. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 72
Table 27. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 73
Table 28. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 74
Table 29. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 74
Table 30. Typical current consumption in Run mode, code with data processing running
from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 77
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 35. Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 36. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 37. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 38. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 40. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 41. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 42. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 43. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 44. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 91
Table 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . 91
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Table 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 92
Table 48. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . . 93
Table 49. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . . 93
Table 50. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 51. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 52. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . . 96
Table 53. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 55. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 56. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 57. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 58. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 106
Table 59. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 60. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 61. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 62. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 63. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 64. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 65. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 66. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 67. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 68. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 69. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 70. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 71. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 72. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 73. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 74. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 75. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 76. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 77. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 78. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 79. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 80. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 81. ADC accuracy - limited test conditions, 100-/144-pin packages . . . . . . . . . . . . . . . . . . . 132
Table 82. ADC accuracy, 100-pin/144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 83. ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 84. ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 85. ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 86. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 87. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 88. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 89. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 90. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 91. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 92. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 93. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 94. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 152
Table 95. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 96. WLCSP100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 97. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 159
List of tables STM32F302xD STM32F302xE
8/168 DocID026900 Rev 4
Table 98. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 99. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 101. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DocID026900 Rev 4 9/168
STM32F302xD STM32F302xE List of figures
10
List of figures
Figure 1. STM32F302xD/E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. STM32F302xD/E clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. STM32F302xD/E LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5. STM32F302xD/E LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6. STM32F302xD/E LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 7. STM32F302xD/E WLCSP100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. STM32F302xD/E UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. STM32F302xD/E memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 14. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] 00’) . . . . . . . . . . . . . 75
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 88
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 90
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 92
Figure 22. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 23. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 24. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 25. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 27. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 28. PC Card/CompactFlash controller waveforms for common memory
read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 29. PC Card/CompactFlash controller waveforms for common memory
write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 30. PC Card/CompactFlash controller waveforms for attribute memory
read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 31. PC Card/CompactFlash controller waveforms for attribute memory
write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 32. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 107
Figure 33. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 107
Figure 34. NAND controller read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 35. NAND controller write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 36. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 37. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 38. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . 115
Figure 39. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . 115
Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 43. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 44. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
List of figures STM32F302xD STM32F302xE
10/168 DocID026900 Rev 4
Figure 45. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 46. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 47. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 48. ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 49. ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 53. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 54. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 55. Recommended footprint for the LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 56. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 57. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 58. Recommended footprint for the UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 59. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 60. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 61. Recommended footprint for the LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 62. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 63. WLCSP100 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 64. Recommended footprint for the WLCSP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 65. WLCSP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 66. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 67. Recommended footprint for the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 68. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 69. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DocID026900 Rev 4 11/168
STM32F302xD STM32F302xE Introduction
63
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F302xD/E microcontrollers.
This STM32F302xD/E datasheet should be read in conjunction with the reference manual of
STM32F302xB/C/D/E, STM32F302x6/8 devices (RM0365) available on STMicroelectronics
website at www.st.com.
For information on the ARM® Cortex®-M4 core with FPU, refer to the following documents:
•Cortex® -M4 with FPU Technical Reference Manual, available from the www.arm.com
website
•STM32F3 and STM32F4 Series Cortex® -M4 programming manual (PM0214)
available on STMicroelectronics website at www.st.com.
Description STM32F302xD STM32F302xE
12/168 DocID026900 Rev 4
2 Description
The STM32F302xD/E family is based on the high-performance ARM® Cortex®-M4 32-bit
RISC core with FPU operating at a frequency of 72 MHz, and embedding a floating point
unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The
family incorporates high-speed embedded memories (512-Kbyte Flash memory, 64-Kbyte
SRAM), a flexible memory controller (FSMC) for static memories (SRAM, PSRAM, NOR
and NAND), and an extensive range of enhanced I/Os and peripherals connected to an
AHB and two APB buses.
The devices offer two fast 12-bit ADCs (5 Msps), four comparators, two operational
amplifiers, one DAC channel, a low-power RTC, up to two general-purpose 16-bit timers,
one general-purpose 32-bit timer, and one timer dedicated to motor control. They also
feature standard and advanced communication interfaces: up to three I2Cs, up to four SPIs
(two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and
USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external
PLL.
The STM32F302xD/E family operates in the -40 to +85°C and -40 to +105°C temperature
ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows
the design of low-power applications.
The STM32F302xD/E family offers devices in different packages ranging from 64 to
144 pins.
Depending on the device chosen, different sets of peripherals are included.
DocID026900 Rev 4 13/168
STM32F302xD STM32F302xE Description
63
Table 2. STM32F302xD/E family device features and peripheral counts
Peripheral STM32F302Rx STM32F302Vx STM32F302Zx
Flash (Kbytes) 384 512 384 512 384 512
SRAM (Kbytes) on data bus 64
FMC (flexible memory controller) NO YES
Timers
Advanced control 1 (16-bit)
General purpose 5 (16-bit)
1 (32-bit)
Basic 1 (16-bit)
PWM channels (all) (1) 26
PWM channels
(except
complementary)
20
Communication
interfaces
SPI (I2S)(2) 4(2)
I2C3
USART 3
UART 2
CAN 1
USB 1
GPIOs
Normal I/Os
(TC, TTa) 26
37 in WLCSP100,44 in
LQFP100 and
UFBGA100
45
5-volt tolerant
I/Os (FT, FTf) 25
42 in LQFP100
40 in WLCSP100 and
UFBGA100
70
DMA channels 12
Capacitive sensing channels 18 24
12-bit ADCs 2
16 channels
2
17 channels
2
18 channels
12-bit DAC channels 1
Analog comparator 4
Operational amplifiers 2
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
Packages LQFP64
LQFP100
,WLCSP100
UFBGA100
LQFP144
1. This total number considers also the PWMs generated on the complementary output channels.
2. The SPI interfaces works in an exclusive way in either the SPI mode or the I2S audio mode.
Description STM32F302xD STM32F302xE
14/168 DocID026900 Rev 4
Figure 1. STM32F302xD/E block diagram
1. AF: alternate function on I/O pins.
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DocID026900 Rev 4 15/168
STM32F302xD STM32F302xE Functional overview
63
3 Functional overview
3.1 ARM® Cortex®-M4 core with FPU with embedded Flash and
SRAM
The ARM® Cortex®-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 32-bit RISC processor with FPU features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allows efficient signal processing
and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F302xD/E family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32F302xD/E family devices.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU manage up to 8 protection areas that are further divided up into 8
subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of
addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS detects it and takes action. In an RTOS
environment, the kernel dynamically updates the MPU area setting, based on the process to
be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memory
All STM32F302xD/E devices feature 384/512 Kbyte of embedded Flash memory available
for storing programs and data. The Flash memory access time is adjusted to the CPU clock
frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states
above).
Functional overview STM32F302xD STM32F302xE
16/168 DocID026900 Rev 4
3.4 Embedded SRAM
STM32F302xD/E devices feature 64 Kbyte of embedded SRAM with hardware parity check
implemented on the first 32 Kbyte. The memory can be accessed in read/write at CPU clock
speed with 0 wait states.
3.5 Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART1 (PA9/PA10), USART2 (PA2/PA3) or USB (PA11/PA12) through DFU
(device firmware upgrade).
3.6 Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
DocID026900 Rev 4 17/168
STM32F302xD STM32F302xE Functional overview
63
3.7 Power management
3.7.1 Power supply schemes
•VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
•VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators,
operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to
VDDA differs from one analog peripheral to another. Table 3 provides the summary of
the VDDA ranges for analog peripherals. The VDDA voltage level must always be greater
than or equal to the VDD voltage level and must be provided first.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
3.7.2 Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
•The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.7.3 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR), and power-down.
•The MR mode is used in the nominal regulation mode (Run)
•The LPR mode is used in Stop mode.
•The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
Table 3. External analog supply values for analog peripherals
Analog peripheral Minimum VDDA supply Maximum VDDA supply
ADC/COMP 2.0 V 3.6 V
DAC/OPAMP 2.4 V 3.6 V
Functional overview STM32F302xD STM32F302xE
18/168 DocID026900 Rev 4
3.7.4 Low-power modes
The STM32F302xD/E supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and wake
up the CPU when an interrupt/event occurs.
•Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC
alarm, COMPx, I2Cx or U(S)ARTx.
•Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.
Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.8 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F302xD/E peripheral interconnect matrix
Interconnect source Interconnect
destination Interconnect action
TIMx
TIMx Timers synchronization or chaining
ADCx
DAC1 Conversion triggers
DMA Memory to memory transfer trigger
Compx Comparator output blanking
COMPx TIMx Timer input: OCREF_CLR input, input capture
ADCx TIMx Timer triggered by analog watchdog
DocID026900 Rev 4 19/168
STM32F302xD STM32F302xE Functional overview
63
Note: For more details about the interconnect actions, refer to the corresponding sections in the
STM32F302xD/E reference manual (RM0365).
3.9 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
GPIO
RTCCLK
HSE/32
MC0
TIM16 Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
COMPx
GPIO
TIM1
TIM15, 16, 17 Timer break
GPIO
TIMx External trigger, timer break
ADCx
DAC1 Conversion external trigger
DAC1 COMPx Comparator inverting input
Table 4. STM32F302xD/E peripheral interconnect matrix (continued)
Interconnect source Interconnect
destination Interconnect action
Functional overview STM32F302xD STM32F302xE
20/168 DocID026900 Rev 4
Figure 2. STM32F302xD/E clock tree
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DocID026900 Rev 4 21/168
STM32F302xD STM32F302xE Functional overview
63
3.10 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.11 Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA is used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC
and ADC.
3.12 Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
•The NOR/PSRAM memory controller,
•The NAND/PC Card memory controller.
This memory controller is also named Flexible memory controller (FMC).
The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM),
– NOR Flash memory/OneNAND Flash memory,
– PSRAM (four memory banks),
– NAND Flash memory with ECC hardware to check up to 8 Kbyte of data,
– 16-bit PC Card compatible devices.
•8-,16-bit data bus width,
•Independent Chip Select control for each memory bank,
•Independent configuration for each memory bank,
•Write FIFO,
•LCD parallel interface.
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
Functional overview STM32F302xD STM32F302xE
22/168 DocID026900 Rev 4
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.13 Interrupts and events
3.13.1 Nested vectored interrupt controller (NVIC)
The STM32F302xD/E devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 73 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
•Closely coupled NVIC gives low latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Closely coupled NVIC core interface
•Allows early processing of interrupts
•Processing of late arriving higher priority interrupts
•Support for tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14 Fast analog-to-digital converter (ADC)
Two fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6
bit, are embedded in the STM32F302xD/E family devices. The ADCs have up to 18 external
channels. The ADCs can perform conversions in single-shot or scan modes. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 2
ADCs channel 18, VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2
connected to ADC2 channel 17.
Additional logic functions embedded in the ADC interface allow:
•Simultaneous sample and hold
•Interleaved sample and hold
•Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller.
Three analog watchdogs are available per ADC.
The analog watchdog feature allows very precise monitoring of the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timer (TIM1)
can be internally connected to the ADC start trigger and injection trigger, respectively, to
allow the application to synchronize A/D conversion and timers.
DocID026900 Rev 4 23/168
STM32F302xD STM32F302xE Functional overview
63
3.14.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.14.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADCx_IN18, x=1...4 input
channel. The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.
3.14.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.14.4 OPAMP reference voltage (VREFOPAMP)
Every OPAMP reference voltage can be measured using a corresponding ADC internal
channel: VREFO, VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2
connected to ADC2 channel 17.
3.15 Digital-to-analog converter (DAC)
One 12-bit buffered DAC channel can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
•One DAC output channel
•8-bit or 10-bit monotonic output
•Left or right data alignment in 12-bit mode
•Synchronized update capability
•Noise-wave generation
•Triangular-wave generation
•DMA capability (for each channel)
Functional overview STM32F302xD STM32F302xE
24/168 DocID026900 Rev 4
•External triggers for conversion
•Input voltage reference VREF+
3.16 Operational amplifier (OPAMP)
The STM32F302xD/E embed two operational amplifiers (OPAMP1 and OPAMP2) with
external or internal follower routing and PGA capability (or even amplifier and filter capability
with external components). When an operational amplifier is selected, an external ADC
channel is used to enable output measurement.
The operational amplifier features:
•8.2 MHz bandwidth
•0.5 mA output capability
•Rail-to-rail input/output
•In PGA mode, the gain is programmed to be 2, 4, 8 or 16.
3.17 Ultra-fast comparators (COMP)
The STM32F302xD/E devices embed four ultra-fast rail-to-rail comparators (COMP1, 2, 4,
6) with programmable reference voltage (internal or external) and selectable output polarity.
The reference voltage can be one of the following:
•External I/O
•DAC output pin
•Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers.
3.18 Timers and watchdogs
The STM32F302xD/E include one advanced control timer, up to six general-purpose timers,
one basic timer, two watchdog timers and one SysTick timer. The table below compares the
features of the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced TIM1 16-bit Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes 4 Yes
General-
purpose TIM2 32-bit Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes 4 No
DocID026900 Rev 4 25/168
STM32F302xD STM32F302xE Functional overview
63
Note: TIM1/2/3/4/15/16/17 can have PLL as clock source, and therefore can be clocked at
144 MHz.
3.18.1 Advanced timers (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
•Input capture
•Output compare
•PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
•One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timer (described in
Section 3.18.2) using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.18.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)
There are up to six synchronizable general-purpose timers embedded in the
STM32F302xD/E (see Table 5 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
General-
purpose TIM3, TIM4 16-bit Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM15 16-bit Up
Any integer
between 1
and 65536
Yes 2 1
General-
purpose TIM16, TIM17 16-bit Up
Any integer
between 1
and 65536
Yes 1 1
Basic TIM6 16-bit Up
Any integer
between 1
and 65536
Yes 0 No
Table 5. Timer feature comparison (continued)
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Functional overview STM32F302xD STM32F302xE
26/168 DocID026900 Rev 4
•TIM2, 3, and TIM4
These are full-featured general-purpose timers:
– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•TIM15, 16 and 17
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.18.3 Basic timers (TIM6)
This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit
time base.
3.18.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.18.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It is
used as a watchdog to reset the device when a problem occurs. It is clocked from the main
clock. It has an early warning interrupt capability and the counter can be frozen in debug
mode.
DocID026900 Rev 4 27/168
STM32F302xD STM32F302xE Functional overview
63
3.18.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•A 24-bit down counter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0.
•Programmable clock source
3.19 Real-time clock (RTC) and backup registers
The RTC and the 16 backup registers are supplied through a switch that takes power from
either the VDD supply when present or the VBAT pin. The backup registers are sixteen 32-bit
registers used to store 64 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. It supports the following features:
•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
•Two programmable alarms with wake up from Stop and Standby mode capability.
•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
•Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
•Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
•17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
•A 32.768 kHz external crystal
•A resonator or oscillator
•The internal low-power RC oscillator (typical frequency of 40 kHz)
•The high-speed external clock divided by 32.
3.20 Inter-integrated circuit interface (I2C)
Up to three I2C bus interfaces can operate in multimaster and slave modes. They can
support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz)
modes.
Functional overview STM32F302xD STM32F302xE
28/168 DocID026900 Rev 4
All I2C bus interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask). They also include programmable
analog and digital noise filters.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2,3) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the features available in I2C1, I2C2 and I2C3.
3.21 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F302xD/E devices have three embedded universal synchronous/asynchronous
receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbit/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
Table 6. Comparison of I2C analog and digital filters
-Analog filter Digital filter
Pulse width of
suppressed spikes ≥ 50 ns Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Table 7. STM32F302xD/E I2C implementation
I2C features(1) I2C1 I2C2 I2C3
7-bit addressing mode X X X
10-bit addressing mode X X X
Standard mode (up to 100 kbit/s) X X X
Fast mode (up to 400 kbit/s) X X X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Independent clock X X X
SMBus X X X
Wakeup from STOP X X X
1. X = supported.
DocID026900 Rev 4 29/168
STM32F302xD STM32F302xE Functional overview
63
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.
3.22 Universal asynchronous receiver transmitter (UART)
The STM32F302xD/E devices have 2 embedded universal asynchronous receiver
transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC,
multiprocessor communication mode and single-wire half-duplex communication mode. The
UART4 interface can be served by the DMA controller.
Refer to Table 8 for the features available in all U(S)ART interfaces.
3.23 Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to four SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex and full duplex communication
modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode
it can output a clock for an external audio component at 256 times the sampling frequency.
Refer to Table 9 for the features available in SPI1, SPI2, SPI3 and SPI4.
Table 8. USART features
USART modes/features(1) USART1 USART2 USART3 UART4 UART5
Hardware flow control for modem X X X - -
Continuous communication using DMA X X X X -
Multiprocessor communication X X X X X
Synchronous mode X X X - -
Smartcard mode X X X - -
Single-wire half-duplex communication X X X X X
IrDA SIR ENDEC block X X X X X
LIN mode XXXXX
Dual clock domain and wakeup from Stop mode X X X X X
Receiver timeout interrupt XXXXX
Modbus communication X X X X X
Auto baud rate detection X X X - -
Driver Enable X X X - -
1. X = supported.
Functional overview STM32F302xD STM32F302xE
30/168 DocID026900 Rev 4
3.24 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.25 Universal serial bus (USB)
The STM32F302xD/E embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 Kbyte (256 bytes are used for
CAN peripheral if enabled) and suspend/resume support.
The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must
use a HSE crystal oscillator).
3.26 Infrared transmitter
The STM32F302xD/E devices provide an infrared transmitter solution. The solution is based
on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Table 9. STM32F302xD/E SPI/I2S implementation
SPI features(1) SPI1 SPI2 SPI3 SPI4
Hardware CRC calculation XXXX
Rx/Tx FIFO XXXX
NSS pulse mode XXXX
I2S mode - X X -
TI mode XXXX
1. X = supported.
DocID026900 Rev 4 31/168
STM32F302xD STM32F302xE Functional overview
63
Figure 3. Infrared transmitter
3.27 Touch sensing controller (TSC)
The STM32F302xD/E devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, etc.). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
06Y9
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Table 10. Capacitive sensing GPIOs available on STM32F302xD/E devices
Group Capacitive sensing
signal name
Pin
name -Group Capacitive sensing
signal name
Pin
name
1
TSC_G1_IO1 PA0
-
5
TSC_G5_IO1 PB3
TSC_G1_IO2 PA1 TSC_G5_IO2 PB4
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
2
TSC_G2_IO1 PA4
6
TSC_G6_IO1 PB11
TSC_G2_IO2 PA5 TSC_G6_IO2 PB12
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
Functional overview STM32F302xD STM32F302xE
32/168 DocID026900 Rev 4
3.28 Development support
3.28.1 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.28.2 Embedded Trace Macrocell
The ARM embedded trace macrocell (ETM™) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the STM32F302xD/E through a small number of ETM™ pins to an external hardware trace
3
TSC_G3_IO1 PC5 -
7
TSC_G7_IO1 PE2
TSC_G3_IO2 PB0 - TSC_G7_IO2 PE3
TSC_G3_IO3 PB1 - TSC_G7_IO3 PE4
TSC_G3_IO4 PB2 - TSC_G7_IO4 PE5
4
TSC_G4_IO1 PA9 -
8
TSC_G8_IO1 PD12
TSC_G4_IO2 PA10 - TSC_G8_IO2 PD13
TSC_G4_IO3 PA13 - TSC_G8_IO3 PD14
TSC_G4_IO4 PA14 - TSC_G8_IO4 PD15
Table 11. Number of capacitive sensing channels available on
STM32F302xD/E devices
Analog I/O group
Number of capacitive sensing channels
STM32F302VE/ZE STM32F302RE
G1 3 3
G2 3 3
G3 3 3
G4 3 3
G5 3 3
G6 3 3
G7 3 0
G8 3 0
Number of capacitive sensing
channels 24 18
Table 10. Capacitive sensing GPIOs available on STM32F302xD/E devices (continued)
Group Capacitive sensing
signal name
Pin
name -Group Capacitive sensing
signal name
Pin
name
DocID026900 Rev 4 33/168
STM32F302xD STM32F302xE Functional overview
63
port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed
channel. Real-time instruction and data flow activity can be recorded and then formatted for
display on the host computer running debugger software. TPA hardware is commercially
available from common development tool vendors. It operates with third party debugger
software tools.
Pinout and pin description STM32F302xD STM32F302xE
34/168 DocID026900 Rev 4
4 Pinout and pin description
Figure 4. STM32F302xD/E LQFP64 pinout
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DocID026900 Rev 4 35/168
STM32F302xD STM32F302xE Pinout and pin description
63
Figure 5. STM32F302xD/E LQFP100 pinout
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Pinout and pin description STM32F302xD STM32F302xE
36/168 DocID026900 Rev 4
Figure 6. STM32F302xD/E LQFP144 pinout
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DocID026900 Rev 4 37/168
STM32F302xD STM32F302xE Pinout and pin description
63
Figure 7. STM32F302xD/E WLCSP100 ballout
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Pinout and pin description STM32F302xD STM32F302xE
38/168 DocID026900 Rev 4
Figure 8. STM32F302xD/E UFBGA100 ballout
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DocID026900 Rev 4 39/168
STM32F302xD STM32F302xE Pinout and pin description
63
Table 12. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
I/O structure
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, I2C FM+ option
TTa 3.3 V tolerant I/O
TC Standard 3.3V I/O
B Dedicated to BOOT0 pin
RST Bi-directional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Table 13. STM32F302xD/E pin definitions
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
- 1 D6 1 PE2 I/O FT (1)
TRACECK, EVENTOUT,
TIM3_CH1, TSC_G7_IO1,
SPI4_SCK, FMC_A23
-
- 2 D7 2 PE3 I/O FT (1)
TRACED0, EVENTOUT,
TIM3_CH2, TSC_G7_IO2,
SPI4_NSS, FMC_A19
-
- 3 C8 3 PE4 I/O FT (1)
TRACED1, EVENTOUT,
TIM3_CH3, TSC_G7_IO3,
SPI4_NSS, FMC_A20
-
- 4 B9 4 PE5 I/O FT (1)
TRACED2, EVENTOUT,
TIM3_CH4, TSC_G7_IO4,
SPI4_MISO, FMC_A21
-
- 5 E7 5 PE6 I/O FT (1) TRACED3, EVENTOUT,
SPI4_MOSI, FMC_A22 WKUP3, RTC_TAMP3
16D86VBAT S - - - -
Pinout and pin description STM32F302xD STM32F302xE
40/168 DocID026900 Rev 4
27C97PC13
(2) I/O TC - EVENTOUT, TIM1_CH1N WKUP2,RTC_TAMP1,
RTC_TS, RTC_OUT
38C108PC14 -
OSC32_IN (2) I/O TC - EVENTOUT OSC32_IN
49D99
PC15 -
OSC32_OUT
(2)
I/O TC - EVENTOUT OSC32_OUT
- - - 10 PH0 I/O FT (1) EVENTOUT, FMC_A0 -
- - - 11 PH1 I/O FT (1) EVENTOUT, FMC_A1 -
- 19 E8 12 PF2 I/O TTa (1) EVENTOUT, FMC_A2 ADC12_IN10
- - - 13 PF3 I/O FT (1) EVENTOUT, FMC_A3 -
- - - 14 PF4 I/O TTa (1) EVENTOUT, COMP1_OUT,
FMC_A4 ADC1_IN5(3)
- - - 15 PF5 I/O FT (1) EVENTOUT, FMC_A5 -
- - - 16 VSS S - (1) --
--- 17VDD S -
(1) --
- 73 C1 18 PF6 I/O FTf (1)
EVENTOUT, TIM4_CH4,
I2C2_SCL, USART3_RTS,
FMC_NIORD
-
- - - 19 PF7 I/O FT (1) EVENTOUT, FMC_NREG -
- - - 20 PF8 I/O FT (1) EVENTOUT, FMC_NIOWR -
- 10 D10 21 PF9 I/O FT (1) EVENTOUT, TIM15_CH1,
SPI2_SCK, FMC_CD -
- 11 E10 22 PF10 I/O FT (1) EVENTOUT, TIM15_CH2,
SPI2_SCK, FMC_INTR -
5 12 F10 23 PF0-OSC_IN I FTf -
EVENTOUT, I2C2_SDA,
SPI2_NSS/I2S2_WS,
TIM1_CH3N
OSC_IN
613F924
PF1-
OSC_OUT OFTf-
EVENTOUT, I2C2_SCL,
SPI2_SCK/I2S2_CK OSC_OUT
7 14 E9 25 NRST I-O RST - Device reset input/internal reset output (active low)
8 15 G10 26 PC0 I/O TTa - EVENTOUT, TIM1_CH1 ADC12_IN6
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
DocID026900 Rev 4 41/168
STM32F302xD STM32F302xE Pinout and pin description
63
9 16 G9 27 PC1 I/O TTa - EVENTOUT, TIM1_CH2 ADC12_IN7
10 17 G8 28 PC2 I/O TTa - EVENTOUT, TIM1_CH3 ADC12_IN8
11 18 H10 29 PC3 I/O TTa - EVENTOUT, TIM1_CH4,
TIM1_BKIN2 ADC12_IN9
12 20 H8 30 VSSA S - (1) --
- - - 31 VREF- S - (1) --
-21J832VREF+
(4) S-- - -
13 22 J10 33 VDDA S - - - -
14 23 H9 34 PA0 I/O TTa -
TIM2_CH1/TIM2_ETR,
TSC_G1_IO1,
USART2_CTS,
COMP1_OUT, EVENTOUT
ADC1_IN1(3), COMP1_INM,
RTC_TAMP2, WKUP1
15 24 J9 35 PA1 I/O TTa -
RTC_REFIN, TIM2_CH2,
TSC_G1_IO2,
USART2_RTS,
TIM15_CH1N, EVENTOUT
ADC1_IN2(3), COMP1_INP,
OPAMP1_VINP
16 25 F7 36 PA2 I/O TTa (5)
TIM2_CH3, TSC_G1_IO3,
USART2_TX,
COMP2_OUT, TIM15_CH1,
EVENTOUT
ADC1_IN3(3), COMP2_INM,
OPAMP1_VOUT
17 26 G7 37 PA3 I/O TTa -
TIM2_CH4, TSC_G1_IO4,
USART2_RX, TIM15_CH2,
EVENTOUT
ADC1_IN4(3),
OPAMP1_VINM/
OPAMP1_VINP
18 27 K9,
K10 38 VSS S - - - -
19 28 K8 39 VDD S - (1) --
20 29 J7 40 PA4 I/O TTa (5)
TIM3_CH2, TSC_G2_IO1,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK, EVENTOUT
ADC2_IN1(3), DAC1_OUT1,
COMP1_INM,
COMP2_INM,
COMP4_INM,
COMP6_INM,
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
Pinout and pin description STM32F302xD STM32F302xE
42/168 DocID026900 Rev 4
21 30 H7 41 PA5 I/O TTa (5)
TIM2_CH1/TIM2_ETR,
TSC_G2_IO2, SPI1_SCK,
EVENTOUT
ADC2_IN2(3), COMP1_INM,
COMP2_INM,
COMP4_INM,
COMP6_INM,
OPAMP1_VINP,
OPAMP2_VINM,
22 31 H6 42 PA6 I/O TTa (5)
TIM16_CH1, TIM3_CH1,
TSC_G2_IO3, SPI1_MISO,
TIM1_BKIN, COMP1_OUT,
EVENTOUT
ADC2_IN3(3),
OPAMP2_VOUT
23 32 K7 43 PA7 I/O TTa -
TIM17_CH1, TIM3_CH2,
TSC_G2_IO4, SPI1_MOSI,
TIM1_CH1N, EVENTOUT
ADC2_IN4(3), COMP2_INP,
OPAMP1_VINP,
OPAMP2_VINP
24 33 G6 44 PC4 I/O TTa - EVENTOUT, TIM1_ETR,
USART1_TX ADC2_IN5(3)
25 34 F6 45 PC5 I/O TTa - EVENTOUT, TIM15_BKIN,
TSC_G3_IO1, USART1_RX
ADC2_IN11,
OPAMP1_VINM,
OPAMP2_VINM
26 35 J6 46 PB0 I/O TTa - TIM3_CH3, TSC_G3_IO2,
TIM1_CH2N, EVENTOUT
COMP4_INP,
OPAMP2_VINP,
27 36 K6 47 PB1 I/O TTa (5)
TIM3_CH4, TSC_G3_IO3,
TIM1_CH3N, COMP4_OUT,
EVENTOUT
-
28 37 K5 48 PB2 I/O TTa - TSC_G3_IO4, EVENTOUT ADC2_IN12, COMP4_INM
- - - 49 PF11 I/O FT (1) EVENTOUT -
- - - 50 PF12 I/O FT (1) EVENTOUT, FMC_A6 -
- - - 51 VSS S - - - -
--- 52VDD S -
(1) --
- - - 53 PF13 I/O FT (1) EVENTOUT, FMC_A7 -
- - - 54 PF14 I/O FT (1) EVENTOUT, FMC_A8 -
- - - 55 PF15 I/O FT (1) EVENTOUT, FMC_A9 -
- - - 56 PG0 I/O FT (1) EVENTOUT, FMC_A10 -
- - - 57 PG1 I/O FT (1) EVENTOUT, FMC_A11 -
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
DocID026900 Rev 4 43/168
STM32F302xD STM32F302xE Pinout and pin description
63
- 38 F8 58 PE7 I/O TTa (1) EVENTOUT, TIM1_ETR,
FMC_D4 -
- 39 E6 59 PE8 I/O TTa (1) EVENTOUT, TIM1_CH1N,
FMC_D5 COMP4_INM
- 40 - 60 PE9 I/O TTa (1) EVENTOUT, TIM1_CH1,
FMC_D6 -
- - - 61 VSS S - (1) --
--- 62VDD S -
(1) --
- 41 - 63 PE10 I/O TTa (1) EVENTOUT, TIM1_CH2N,
FMC_D7 -
- 42 H5 64 PE11 I/O TTa (1) EVENTOUT, TIM1_CH2,
SPI4_NSS, FMC_D8 -
-43G565PE12 I/OTTa
(1) EVENTOUT, TIM1_CH3N,
SPI4_SCK, FMC_D9 -
- 44 - 66 PE13 I/O TTa (1) EVENTOUT, TIM1_CH3,
SPI4_MISO, FMC_D10 -
- 45 - 67 PE14 I/O TTa (1)
EVENTOUT, TIM1_CH4,
SPI4_MOSI, TIM1_BKIN2,
FMC_D11
-
- 46 - 68 PE15 I/O TTa (1) EVENTOUT, TIM1_BKIN,
USART3_RX, FMC_D12 -
29 47 K4 69 PB10 I/O TTa - TIM2_CH3, TSC_SYNC,
USART3_TX, EVENTOUT -
30 48 K3 70 PB11 I/O TTa - TIM2_CH4, TSC_G6_IO1,
USART3_RX, EVENTOUT ADC12_IN14, COMP6_INP
31 49
K1,
J1,
K2
71 VSS S - - - -
32 50 J5 72 VDD S - - - -
33 51 J4 73 PB12 I/O TTa (5)
TSC_G6_IO2,
I2C2_SMBAL,
SPI2_NSS/I2S2_WS,
TIM1_BKIN, USART3_CK,
EVENTOUT
-
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
Pinout and pin description STM32F302xD STM32F302xE
44/168 DocID026900 Rev 4
34 52 J3 74 PB13 I/O TTa -
TSC_G6_IO3,
SPI2_SCK/I2S2_CK,
TIM1_CH1N,
USART3_CTS, EVENTOUT
-
35 53 J2 75 PB14 I/O TTa -
TIM15_CH1, TSC_G6_IO4,
SPI2_MISO/I2S2ext_SD,
TIM1_CH2N,
USART3_RTS, EVENTOUT
OPAMP2_VINP
36 54 H4 76 PB15 I/O TTa -
RTC_REFIN, TIM15_CH2,
TIM15_CH1N, TIM1_CH3N,
SPI2_MOSI/I2S2_SD,
EVENTOUT
COMP6_INM
- 55 - 77 PD8 I/O TTa (1) EVENTOUT, USART3_TX,
FMC_D13 -
-56G478PD9 I/OTTa
(1) EVENTOUT, USART3_RX,
FMC_D14 -
- 57 H3 79 PD10 I/O TTa (1) EVENTOUT, USART3_CK,
FMC_D15 COMP6_INM
- 58 H2 80 PD11 I/O TTa (1) EVENTOUT,
USART3_CTS, FMC_A16 -
- 59 H1 81 PD12 I/O TTa (1)
EVENTOUT, TIM4_CH1,
TSC_G8_IO1,
USART3_RTS, FMC_A17
-
-60G382PD13 I/OTTa
(1) EVENTOUT, TIM4_CH2,
TSC_G8_IO2, FMC_A18 -
- - - 83 VSS S - (1) --
--- 84VDD S -
(1) --
-61G285PD14 I/OTTa
(1) EVENTOUT, TIM4_CH3,
TSC_G8_IO3, FMC_D0 OPAMP2_VINP
-62G186PD15 I/OTTa
(1)
EVENTOUT, TIM4_CH4,
TSC_G8_IO4, SPI2_NSS,
FMC_D1
-
- - - 87 PG2 I/O FT (1) EVENTOUT, FMC_A12 -
- - - 88 PG3 I/O FT (1) EVENTOUT, FMC_A13 -
- - - 89 PG4 I/O FT (1) EVENTOUT, FMC_A14 -
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
DocID026900 Rev 4 45/168
STM32F302xD STM32F302xE Pinout and pin description
63
- - - 90 PG5 I/O FT (1) EVENTOUT, FMC_A15 -
- - - 91 PG6 I/O FT (1) EVENTOUT, FMC_INT2 -
- - - 92 PG7 I/O FT (1) EVENTOUT, FMC_INT3 -
- - - 93 PG8 I/O FT (1) EVENTOUT -
- - - 94 VSS S - (1) --
--- 95VDD S -
(1) --
37 63 F4 96 PC6 I/O FT - EVENTOUT, TIM3_CH1,
I2S2_MCK, COMP6_OUT -
38 64 F2 97 PC7 I/O FT - EVENTOUT, TIM3_CH2,
I2S3_MCK -
39 65 F1 98 PC8 I/O FT - EVENTOUT, TIM3_CH3 -
40 66 F3 99 PC9 I/O FTf - EVENTOUT, TIM3_CH4,
I2C3_SDA, I2SCKIN -
41 67 F5 100 PA8 I/O FTf -
MCO, I2C3_SCL,
I2C2_SMBAL, I2S2_MCK,
TIM1_CH1, USART1_CK,
TIM4_ETR, EVENTOUT
-
42 68 E5 101 PA9 I/O FTf -
I2C3_SMBAL,
TSC_G4_IO1, I2C2_SCL,
I2S3_MCK, TIM1_CH2,
USART1_TX, TIM15_BKIN,
TIM2_CH3, EVENTOUT
-
43 69 E1 102 PA10 I/O FTf -
TIM17_BKIN,
TSC_G4_IO2, I2C2_SDA,
SPI2_MISO/I2S2ext_SD,
TIM1_CH3, USART1_RX,
COMP6_OUT, TIM2_CH4,
EVENTOUT
-
44 70 E2 103 PA11 I/O FT -
SPI2_MOSI/I2S2_SD,
TIM1_CH1N,
USART1_CTS,
COMP1_OUT, CAN_RX,
TIM4_CH1, TIM1_CH4,
TIM1_BKIN2, EVENTOUT
USB_DM
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
Pinout and pin description STM32F302xD STM32F302xE
46/168 DocID026900 Rev 4
45 71 D1 104 PA12 I/O FT -
TIM16_CH1, I2SCKIN,
TIM1_CH2N,
USART1_RTS,
COMP2_OUT, CAN_TX,
TIM4_CH2, TIM1_ETR,
EVENTOUT
USB_DP
46 72 E3 105 PA13 I/O FT -
SWDIO-JTMS,
TIM16_CH1N,
TSC_G4_IO3, IR-OUT,
USART3_CTS, TIM4_CH3,
EVENTOUT
-
- - - 106 PH2 I/O FT (1) EVENTOUT -
47 74
A1,
A2,
B1
107 VSS S - - - -
48 75 D2 108 VDD S - - - -
49 76 C2 109 PA14 I/O FTf -
SWCLK-JTCK,
TSC_G4_IO4, I2C1_SDA,
TIM1_BKIN, USART2_TX,
EVENTOUT
-
50 77 B2 110 PA15 I/O FTf -
JTDI,
TIM2_CH1/TIM2_ETR,
TSC_SYNC, I2C1_SCL,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_RX, TIM1_BKIN,
EVENTOUT
-
51 78 E4 111 PC10 I/O FT -
EVENTOUT, UART4_TX,
SPI3_SCK/I2S3_CK,
USART3_TX
-
52 79 D3 112 PC11 I/O FT -
EVENTOUT, UART4_RX,
SPI3_MISO/I2S3ext_SD,
USART3_RX
-
53 80 A3 113 PC12 I/O FT -
EVENTOUT, UART5_TX,
SPI3_MOSI/I2S3_SD,
USART3_CK
-
- 81 B3 114 PD0 I/O FT (1) EVENTOUT, CAN_RX,
FMC_D2 -
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
DocID026900 Rev 4 47/168
STM32F302xD STM32F302xE Pinout and pin description
63
- 82 C3 115 PD1 I/O FT (1) EVENTOUT, CAN_TX,
FMC_D3 -
54 83 A4 116 PD2 I/O FT - EVENTOUT, TIM3_ETR,
UART5_RX -
- 84 B4 117 PD3 I/O FT (1)
EVENTOUT,
TIM2_CH1/TIM2_ETR,
USART2_CTS, FMC_CLK
-
- 85 C4 118 PD4 I/O FT (1) EVENTOUT, TIM2_CH2,
USART2_RTS, FMC_NOE -
- 86 - 119 PD5 I/O FT (1) EVENTOUT, USART2_TX,
FMC_NWE -
- - - 120 VSS S - (1) --
--- 121VDD S -
(1) --
- 87 - 122 PD6 I/O FT (1) EVENTOUT, TIM2_CH4,
USART2_RX, FMC_NWAIT -
- 88 D4 123 PD7 I/O FT (1)
EVENTOUT, TIM2_CH3,
USART2_CK,
FMC_NE1/FMC_NCE2
-
- - - 124 PG9 I/O FT (1) EVENTOUT,
FMC_NE2/FMC_NCE3 -
- - - 125 PG10 I/O FT (1) EVENTOUT,
FMC_NCE4_1/FMC_NE3 -
- - - 126 PG11 I/O FT (1) EVENTOUT, FMC_NCE4_2 -
- - - 127 PG12 I/O FT (1) EVENTOUT, FMC_NE4 -
- - - 128 PG13 I/O FT (1) EVENTOUT, FMC_A24 -
- - - 129 PG14 I/O FT (1) EVENTOUT, FMC_A25 -
- - - 130 VSS S - (1) --
--- 131VDD S -
(1) --
- - - 132 PG15 I/O FT (1) EVENTOUT -
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
Pinout and pin description STM32F302xD STM32F302xE
48/168 DocID026900 Rev 4
55 89 A5 133 PB3 I/O FT -
JTDO-TRACESWO,
TIM2_CH2, TIM4_ETR,
TSC_G5_IO1, SPI1_SCK,
SPI3_SCK/I2S3_CK,
USART2_TX, TIM3_ETR,
EVENTOUT
-
56 90 B5 134 PB4 I/O FT -
JTRST, TIM16_CH1,
TIM3_CH1, TSC_G5_IO2,
SPI1_MISO,
SPI3_MISO/I2S3ext_SD,
USART2_RX, TIM17_BKIN,
EVENTOUT
-
57 91 A6 135 PB5 I/O FTf -
TIM16_BKIN, TIM3_CH2,
I2C1_SMBAl, SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
USART2_CK, I2C3_SDA,
TIM17_CH1, EVENTOUT
-
58 92 B6 136 PB6 I/O FTf -
TIM16_CH1N, TIM4_CH1,
TSC_G5_IO3, I2C1_SCL,
USART1_TX, EVENTOUT
-
59 93 C5 137 PB7 I/O FTf -
TIM17_CH1N, TIM4_CH2,
TSC_G5_IO4, I2C1_SDA,
USART1_RX, TIM3_CH4,
FMC_NADV, EVENTOUT
-
60 94 A7 138 BOOT0 I - - - -
61 95 D5 139 PB8 I/O FTf -
TIM16_CH1, TIM4_CH3,
TSC_SYNC, I2C1_SCL,
USART3_RX,
COMP1_OUT, CAN_RX,
TIM1_BKIN, EVENTOUT
-
62 96 C6 140 PB9 I/O FTf -
TIM17_CH1, TIM4_CH4,
I2C1_SDA, IR-OUT,
USART3_TX,
COMP2_OUT, CAN_TX,
EVENTOUT
-
- 97 B7 141 PE0 I/O FT (1)
EVENTOUT, TIM4_ETR,
TIM16_CH1, USART1_TX,
FMC_NBL0
-
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
DocID026900 Rev 4 49/168
STM32F302xD STM32F302xE Pinout and pin description
63
- 98 A8 142 PE1 I/O FT (1) EVENTOUT, TIM17_CH1,
USART1_RX, FMC_NBL1 -
63 99 C7 143 VSS S - - - -
64 100
A9,
A10
,
B10
,
B8
144 VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3
mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED)
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the RM0316 reference manual.
3. Fast ADC channel.
4. The VREF+ functionality is not available on the 64-pin package. In this package, the VREF+ is internally connected to
VDDA.
5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
Table 13. STM32F302xD/E pin definitions (continued)
Pin number
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
LQFP64
LQFP100
WLCSP100
LQFP144
Pinout and pin description STM32F302xD STM32F302xE
50/168 DocID026900 Rev 4
Table 14. STM32F302xD/E alternate function mapping
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Port A
PA0 -
TIM2_
CH1/TIM
2_ETR
-TSC_G1
_IO1 ---
USART2_
CTS
COMP1_
OUT -- - - - - - EVENT
OUT
PA1 RTC_
REFIN
TIM2_
CH2 -TSC_G1
_IO2 ---
USART2_
RTS -TIM15_
CH1N -- ---
EVENT
OUT
PA2 - TIM2_
CH3 -TSC_G1
_IO3 ---
USART2_
TX
COMP2_
OUT
TIM15_
CH1 -- ---
EVENT
OUT
PA3 - TIM2_
CH4 -TSC_G1
_IO4 ---
USART2_
RX -TIM15_
CH2 -- ---
EVENT
OUT
PA4 - TIM3_
CH2
TSC_G2
_IO1 -SPI1_NSS
SPI3_NSS
/I2S3_WS
USART2_
CK -------
EVENT
OUT
PA5 -
TIM2_
CH1/TIM
2_ETR
-TSC_G2
_IO2 -SPI1_SCK---------
EVENT
OUT
PA6 - TIM16_
CH1
TIM3_
CH1
TSC_G2
_IO3 -SPI1_
MISO
TIM1_
BKIN -COMP1_
OUT ------
EVENT
OUT
PA7 - TIM17_
CH1
TIM3_
CH2
TSC_G2
_IO4 -SPI1_
MOSI
TIM1_
CH1N --------
EVENT
OUT
PA8 MCO - - I2C3_
SCL
I2C2_
SMBAL
I2S2_
MCK
TIM1_
CH1
USART1_
CK --
TIM4_
ETR ----
EVENT
OUT
PA9 - - I2C3_
SMBAL
TSC_G4
_IO1 I2C2_SCL I2S3_
MCK
TIM1_
CH2
USART1_
TX -TIM15_
BKIN
TIM2_
CH3 ----
EVENT
OUT
STM32F302xD STM32F302xE Pinout and pin description
DocID026900 Rev 4 51/168
Port A
PA10 - TIM17_
BKIN -TSC_G4
_IO2 I2C2_SDA
SPI2_MIS
O/I2S2ext
_SD
TIM1_
CH3
USART1_
RX
COMP6_
OUT -TIM2_
CH4 ----
EVENT
OUT
PA11 - - - - -
SPI2_MO
SI/I2S2_
SD
TIM1_
CH1N
USART1_
CTS
COMP1_
OUT CAN_RX TIM4_
CH1
TIM1_
CH4
TIM1_
BKIN2 --
EVENT
OUT
PA12 - TIM16_
CH1 ---I2SCKIN
TIM1_
CH2N
USART1_
RTS
COMP2_
OUT CAN_TX TIM4_
CH2
TIM1_
ETR ---
EVENT
OUT
PA13 SWDIO-
JTMS
TIM16_
CH1N -TSC_G4
_IO3 -IR-OUT-
USART3_
CTS --
TIM4_
CH3 ----
EVENT
OUT
PA14 SWCLK-
JTCK --
TSC_G4
_IO4 I2C1_SDA - TIM1_
BKIN
USART2_
TX -------
EVENT
OUT
PA15 JTDI
TIM2_
CH1/TIM
2_ETR
-TSC_
SYNC I2C1_SCL SPI1_NSS SPI3_NSS
/I2S3_WS
USART2_
RX -TIM1_
BKIN -- ---
EVENT
OUT
Port B
PB0 - - TIM3_
CH3
TSC_G3
_IO2 --
TIM1_
CH2N --------
EVENT
OUT
PB1 - - TIM3_
CH4
TSC_G3
_IO3 --
TIM1_
CH3N -COMP4_
OUT ------
EVENT
OUT
PB2 - - - TSC_G3
_IO4 -----------
EVENT
OUT
PB3
JTDO-
TRACES
WO
TIM2_
CH2
TIM4_
ETR
TSC_G5
_IO1 -SPI1_SCK
SPI3_SCK
/I2S3_CK
USART2_
TX --
TIM3_
ETR ----
EVENT
OUT
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Pinout and pin description STM32F302xD STM32F302xE
52/168 DocID026900 Rev 4
Port B
PB4 JTRST TIM16_
CH1
TIM3_
CH1
TSC_G5
_IO2 -SPI1_
MISO
SPI3_MIS
O/I2S3ext
_SD
USART2_
RX --
TIM17_
BKIN ----
EVENT
OUT
PB5 - TIM16_
BKIN
TIM3_
CH2 -I2C1_
SMBAl
SPI1_
MOSI
SPI3_MO
SI/I2S3_
SD
USART2_
CK I2C3_SDA - TIM17_
CH1 ----
EVENT
OUT
PB6 - TIM16_
CH1N
TIM4_
CH1
TSC_G5
_IO3 I2C1_SCL - - USART1_
TX -------
EVENT
OUT
PB7 - TIM17_
CH1N
TIM4_
CH2
TSC_G5
_IO4 I2C1_SDA - - USART1_
RX --
TIM3_
CH4 -FMC_
NADV --
EVENT
OUT
PB8 - TIM16_
CH1
TIM4_
CH3
TSC_
SYNC I2C1_SCL - - USART3_
RX
COMP1_
OUT CAN_RX - - TIM1_
BKIN --
EVENT
OUT
PB9 - TIM17_
CH1
TIM4_
CH4 - I2C1_SDA - IR-OUT USART3_
TX
COMP2_
OUT CAN_TX - - - - - EVENT
OUT
PB10 - TIM2_
CH3 -TSC_
SYNC ---
USART3_
TX -------
EVENT
OUT
PB11 - TIM2_
CH4 -TSC_G6
_IO1 ---
USART3_
RX -------
EVENT
OUT
PB12 - - - TSC_G6
_IO2
I2C2_
SMBAL
SPI2_NSS
/I2S2_WS
TIM1_
BKIN
USART3_
CK -------
EVENT
OUT
PB13 - - - TSC_G6
_IO3 -SPI2_SCK
/I2S2_CK
TIM1_
CH1N
USART3_
CTS -------
EVENT
OUT
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
STM32F302xD STM32F302xE Pinout and pin description
DocID026900 Rev 4 53/168
Port B
PB14 - TIM15_
CH1 -TSC_G6
_IO4 -
SPI2_MIS
O/I2S2ext
_SD
TIM1_
CH2N
USART3_
RTS -------
EVENT
OUT
PB15 RTC_
REFIN
TIM15_
CH2
TIM15_
CH1N -TIM1_
CH3N
SPI2_MO
SI/I2S2_S
D
---------
EVENT
OUT
Port C
PC0 - EVENT
OUT
TIM1_
CH1 -------------
PC1 - EVENT
OUT
TIM1_
CH2 -------------
PC2 - EVENT
OUT
TIM1_
CH3 -------------
PC3 - EVENT
OUT
TIM1_
CH4 -- -
TIM1_
BKIN2 ---------
PC4 - EVENT
OUT
TIM1_
ETR -- - -
USART1_
TX --------
PC5 - EVENT
OUT
TIM15_
BKIN
TSC_G3
_IO1 ---
USART1_
RX --------
PC6 - EVENT
OUT
TIM3_
CH1 -- -
I2S2_
MCK
COMP6_O
UT --------
PC7 - EVENT
OUT
TIM3_
CH2 -- -
I2S3_
MCK ---------
PC8 - EVENT
OUT
TIM3_
CH3 -------------
PC9 - EVENT
OUT
TIM3_
CH4
I2C3_
SDA -I2SCKIN----------
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Pinout and pin description STM32F302xD STM32F302xE
54/168 DocID026900 Rev 4
Port C
PC10 - EVENT
OUT ---
UART4_
TX
SPI3_SCK
/I2S3_CK
USART3_
TX --------
PC11 - EVENT
OUT ---
UART4_
RX
SPI3_MIS
O/I2S3ext
_SD
USART3_
RX --------
PC12 - EVENT
OUT ---
UART5_
TX
SPI3_MO
SI/I2S3_
SD
USART3_
CK --------
PC13 - EVENT
OUT --
TIM1_
CH1N -----------
PC14 - EVENT
OUT --------------
PC15 - EVENT
OUT --------------
Port D
PD0 - EVENT
OUT - - - - - CAN_RX - - - - FMC_D2 - - -
PD1 - EVENT
OUT - - - - CAN_TX - - - - FMC_D3 - - -
PD2 - EVENT
OUT
TIM3_
ETR --
UART5_
RX ----------
PD3 - EVENT
OUT
TIM2_CH
1/TIM2_
ETR
-- - -
USART2_
CTS ----
FMC_
CLK -- -
PD4 - EVENT
OUT
TIM2_
CH2 -- - -
USART2_
RTS ----
FMC_
NOE -- -
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
STM32F302xD STM32F302xE Pinout and pin description
DocID026900 Rev 4 55/168
Port D
PD5 - EVENT
OUT --- - -
USART2_
TX ----
FMC_
NWE -- -
PD6 - EVENT
OUT
TIM2_
CH4 -- - -
USART2_
RX ----
FMC_
NWAIT -- -
PD7 - EVENT
OUT
TIM2_
CH3 -- - -
USART2_
CK ----
FMC_NE
1/FMC_
NCE2
-- -
PD8 - EVENT
OUT --- - -
USART3_
TX ----
FMC_
D13 -- -
PD9 - EVENT
OUT --- - -
USART3_
RX ----
FMC_
D14 -- -
PD10 - EVENT
OUT --- - -
USART3_
CK ----
FMC_
D15 -- -
PD11 - EVENT
OUT --- - -
USART3_
CTS ----
FMC_
A16 -- -
PD12 - EVENT
OUT
TIM4_
CH1
TSC_G8
_IO1 ---
USART3_
RTS ----
FMC_
A17 -- -
PD13 - EVENT
OUT
TIM4_
CH2
TSC_G8
_IO2 --------
FMC_
A18 -- -
PD14 - EVENT
OUT
TIM4_
CH3
TSC_G8
_IO3 --------FMC_D0---
PD15 - EVENT
OUT
TIM4_
CH4
TSC_G8
_IO4 - - SPI2_NSS - - - - - FMC_D1 - - -
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Pinout and pin description STM32F302xD STM32F302xE
56/168 DocID026900 Rev 4
Port E
PE0 - EVENT
OUT
TIM4_
ETR -TIM16_
CH1 --
USART1_
TX ----
FMC_
NBL0 -- -
PE1 - EVENT
OUT --
TIM17_
CH1 --
USART1_
RX ----
FMC_
NBL1 -- -
PE2 TRACECK EVENT
OUT
TIM3_
CH1
TSC_G7
_IO1 -SPI4_SCK------
FMC_
A23 -- -
PE3 TRACED0 EVENT
OUT
TIM3_
CH2
TSC_G7
_IO2 -SPI4_NSS------
FMC_
A19 -- -
PE4 TRACED1 EVENT
OUT
TIM3_
CH3
TSC_G7
_IO3 -SPI4_NSS------
FMC_
A20 -- -
PE5 TRACED2 EVENT
OUT
TIM3_
CH4
TSC_G7
_IO4 -SPI4_
MISO ------
FMC_
A21 -- -
PE6 TRACED3 EVENT
OUT ---
SPI4_
MOSI ------
FMC_
A22 -- -
PE7 - EVENT
OUT
TIM1_
ETR ---------FMC_D4---
PE8 - EVENT
OUT
TIM1_
CH1N ---------FMC_D5---
PE9 - EVENT
OUT
TIM1_
CH1 ---------FMC_D6---
PE10 - EVENT
OUT
TIM1_
CH2N ---------FMC_D7---
PE11 - EVENT
OUT
TIM1_
CH2 - - SPI4_NSS - - - - - - FMC_D8 - - -
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
STM32F302xD STM32F302xE Pinout and pin description
DocID026900 Rev 4 57/168
Port E
PE12 - EVENT
OUT
TIM1_
CH3N - - SPI4_SCK - - - - - - FMC_D9 - - -
PE13 - EVENT
OUT
TIM1_
CH3 --
SPI4_
MISO ------
FMC_
D10 -- -
PE14 - EVENT
OUT
TIM1_
CH4 --
SPI4_
MOSI
TIM1_
BKIN2 -----
FMC_
D11 -- -
PE15 - EVENT
OUT
TIM1_
BKIN -- - -
USART3_
RX ----
FMC_
D12 -- -
Port F
PF0 - EVENT
OUT - - I2C2_SDA SPI2_NSS
/I2S2_WS
TIM1_
CH3N ---------
PF1 - EVENT
OUT - - I2C2_SCL SPI2_SCK
/I2S2_CK ----------
PF2 - EVENT
OUT ----------FMC_A2---
PF3 - EVENT
OUT ----------FMC_A3---
PF4 - EVENT
OUT
COMP1_
OUT ---------FMC_A4---
PF5 - EVENT
OUT ----------FMC_A5---
PF6 - EVENT
OUT
TIM4_
CH4 - I2C2_SCL - - USART3_
RTS ----
FMC_
NIORD -- -
PF7 - EVENT
OUT ----------
FMC_
NREG -- -
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Pinout and pin description STM32F302xD STM32F302xE
58/168 DocID026900 Rev 4
Port F
PF8 - EVENT
OUT ----------
FMC_
NIOWR -- -
PF9 - EVENT
OUT -TIM15_
CH1 -SPI2_SCK------FMC_CD---
PF10 - EVENT
OUT -TIM15_
CH2 -SPI2_SCK------
FMC_
INTR -- -
PF11 - EVENT
OUT --------------
PF12 - EVENT
OUT ----------FMC_A6---
PF13 - EVENT
OUT ----------FMC_A7---
PF14 - EVENT
OUT ----------FMC_A8---
PF15 - EVENT
OUT ----------FMC_A9---
Port G
PG0 - EVENT
OUT ----------
FMC_
A10 -- -
PG1 - EVENT
OUT ----------
FMC_
A11 -- -
PG2 - EVENT
OUT ----------
FMC_
A12 -- -
PG3 - EVENT
OUT ----------
FMC_
A13 -- -
PG4 - EVENT
OUT ----------
FMC_
A14 -- -
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
STM32F302xD STM32F302xE Pinout and pin description
DocID026900 Rev 4 59/168
Port G
PG5 - EVENT
OUT ----------
FMC_
A15 -- -
PG6 - EVENT
OUT ----------
FMC_
INT2 -- -
PG7 - EVENT
OUT ----------
FMC_
INT3 -- -
PG8 - EVENT
OUT --------------
PG9 - EVENT
OUT ----------
FMC_NE
2/FMC_
NCE3
-- -
PG10 - EVENT
OUT ----------
FMC_
NCE4_1/
FMC_
NE3
-- -
PG11 - EVENT
OUT ----------
FMC_
NCE4_2 -- -
PG12 - EVENT
OUT ----------
FMC_
NE4 -- -
PG13 - EVENT
OUT ----------
FMC_
A24 -- -
PG14 - EVENT
OUT ----------
FMC_
A25 -- -
PG15 - EVENT
OUT --------------
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
Pinout and pin description STM32F302xD STM32F302xE
60/168 DocID026900 Rev 4
Port H
PH0 - EVENT
OUT ----------FMC_A0---
PH1 - EVENT
OUT ----------FMC_A1---
PH2 - EVENT
OUT --------------
Table 14. STM32F302xD/E alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF
TIM2/15/
16/17/E
VENT
I2C3/TIM1
/2/3/4/8/20
/15/GPCO
MP1
I2C3//15/
TSC
I2C1/2/TI
M1/8/16/
17
SPI1/SPI2
/I2S2/SPI3
/I2S3/SPI4
/UART4/5/
Infrared
SPI2/I2S2/
SPI3/I2S3/
TIM1/8/20/
Infrared
USART1/2
/3/CAN/GP
COMP6
I2C3/GPC
OMP1/2/3/
4/5/6
CAN/TIM1
/8/15
TIM2/3/
4/8/17 TIM1/8 FSMC
/TIM1 - - EVENT
DocID026900 Rev 4 61/168
STM32F302xD STM32F302xE Memory mapping
63
5 Memory mapping
Figure 9. STM32F302xD/E memory map
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62/168 DocID026900 Rev 4
Table 15. Memory map, peripheral register boundary addresses
Bus Boundary address Size
(bytes) Peripheral
AHB4
0xA000 0000 - 0xA000 0FFF 4 K FSMC control registers
0x8000 0000 - 0x9FFF FFFF 512 M FSMC Banks 3 and 4
0x6000 0000 - 0x7FFF FFFF 512 M FSMC Banks 1 and 2
-0x5000 0400 - 0x5FFF FFFF ~384 M Reserved
AHB3 0x5000 0000 - 0x5000 03FF 1 K ADC1 - ADC2
-0x4800 2000 - 0x4FFF FFFF ~132 M Reserved
AHB2
0x4800 1C00 - 0x4800 1FFF 1 K GPIOH
0x4800 1800 - 0x4800 1BFF 1 K GPIOG
0x4800 1400 - 0x4800 17FF 1 K GPIOF
0x4800 1000 - 0x4800 13FF 1 K GPIOE
0x4800 0C00 - 0x4800 0FFF 1 K GPIOD
0x4800 0800 - 0x4800 0BFF 1 K GPIOC
0x4800 0400 - 0x4800 07FF 1 K GPIOB
0x4800 0000 - 0x4800 03FF 1 K GPIOA
-0x4002 4400 - 0x47FF FFFF ~128 M Reserved
AHB1
0x4002 4000 - 0x4002 43FF 1 K TSC
0x4002 3400 - 0x4002 3FFF 3 K Reserved
0x4002 3000 - 0x4002 33FF 1 K CRC
0x4002 2400 - 0x4002 2FFF 3 K Reserved
0x4002 2000 - 0x4002 23FF 1 K Flash interface
0x4002 1400 - 0x4002 1FFF 3 K Reserved
0x4002 1000 - 0x4002 13FF 1 K RCC
0x4002 0800 - 0x4002 0FFF 2 K Reserved
0x4002 0400 - 0x4002 07FF 1 K DMA2
0x4002 0000 - 0x4002 03FF 1 K DMA1
-0x4001 8000 - 0x4001 FFFF 32 K Reserved
APB2
0x4001 4C00 - 0x4001 7FFF 13 K Reserved
0x4001 4800 - 0x4001 4BFF 1 K TIM17
0x4001 4400 - 0x4001 47FF 1 K TIM16
0x4001 4000 - 0x4001 43FF 1 K TIM15
0x4001 3C00 - 0x4001 3FFF 1 K SPI4
0x4001 3800 - 0x4001 3BFF 1 K USART1
0x4001 3400 - 0x4001 37FF 1 K Reserved
0x4001 3000 - 0x4001 33FF 1 K SPI1
DocID026900 Rev 4 63/168
STM32F302xD STM32F302xE Memory mapping
63
APB2
0x4001 2C00 - 0x4001 2FFF 1 K TIM1
0x4001 0800 - 0x4001 2BFF 9 K Reserved
0x4001 0400 - 0x4001 07FF 1 K EXTI
0x4001 0000 - 0x4001 03FF 1 K SYSCFG + COMP + OPAMP
-0x4000 7C00 - 0x4000 FFFF 32 K Reserved
APB1
0x4000 7800 - 0x4000 7BFF 1 K I2C3
0x4000 7400 - 0x4000 77FF 1 K DAC
0x4000 7000 - 0x4000 73FF 1 K PWR
0x4000 6800 - 0x4000 6FFF 2 K Reserved
0x4000 6400 - 0x4000 67FF 1 K bxCAN
0x4000 6000 - 0x4000 63FF 1 K USB/CAN SRAM
0x4000 5C00 - 0x4000 5FFF 1 K USB device FS
0x4000 5800 - 0x4000 5BFF 1 K I2C2
0x4000 5400 - 0x4000 57FF 1 K I2C1
0x4000 5000 - 0x4000 53FF 1 K UART5
0x4000 4C00 - 0x4000 4FFF 1 K UART4
0x4000 4800 - 0x4000 4BFF 1 K USART3
0x4000 4400 - 0x4000 47FF 1 K USART2
0x4000 4000 - 0x4000 43FF 1 K I2S3ext
0x4000 3C00 - 0x4000 3FFF 1 K SPI3/I2S3
0x4000 3800 - 0x4000 3BFF 1 K SPI2/I2S2
0x4000 3400 - 0x4000 37FF 1 K I2S2ext
0x4000 3000 - 0x4000 33FF 1 K IWDG
0x4000 2C00 - 0x4000 2FFF 1 K WWDG
0x4000 2800 - 0x4000 2BFF 1 K RTC
0x4000 1800 - 0x4000 27FF 4 K Reserved
0x4000 1000 - 0x4000 13FF 1 K TIM6
0x4000 0C00 - 0x4000 0FFF 1 K Reserved
0x4000 0800 - 0x4000 0BFF 1 K TIM4
0x4000 0400 - 0x4000 07FF 1 K TIM3
0x4000 0000 - 0x4000 03FF 1 K TIM2
Table 15. Memory map, peripheral register boundary addresses (continued)
Bus Boundary address Size
(bytes) Peripheral
Electrical characteristics STM32F302xD STM32F302xE
64/168 DocID026900 Rev 4
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 2.0 to 3.6 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
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DocID026900 Rev 4 65/168
STM32F302xD STM32F302xE Electrical characteristics
146
6.1.6 Power supply scheme
Figure 12. Power supply scheme
1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply
pins.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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66/168 DocID026900 Rev 4
6.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics,
Table 17: Current characteristics, and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
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Table 16. Voltage characteristics(1)
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage (including VDDA, VBAT
and VDD)-0.3 4.0
V
VDD–VDDA Allowed voltage difference for VDD > VDDA -0.4
VREF+–VDDA(2) Allowed voltage difference for VREF+ > VDDA -0.4
VIN(3)
Input voltage on FT and FTf pins VSS − 0.3 VDD + 4.0
V
Input voltage on TTa pins VSS − 0.3 4.0
Input voltage on any other pin VSS − 0.3 4.0
Input voltage on Boot0 pin 0 9
|ΔVDDx| Variations between different VDD power pins - 50 mV
|VSSX − VSS| Variations between all the different ground pins - 50
VESD(HBM)
Electrostatic discharge voltage (human body
model)
see Section 6.3.13: Electrical
sensitivity characteristics -
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD:
VDDA must power on before or at the same time as VDD in the power up sequence.
VDDA must be greater than or equal to VDD.
2. VREF+ must be always lower or equal than VDDA (VREF+ ≤ VDDA). If unused then it must be connected to VDDA.
3. VIN maximum must always be respected. Refer to Table 17: Current characteristics for the maximum allowed injected
current values.
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STM32F302xD STM32F302xE Electrical characteristics
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Table 17. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source) 160
mA
ΣIVSS Total current out of sum of all VSS_x ground lines (sink) -160
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVSS Maximum current out of each VSS _x ground line (sink)(1) 100
IIO(PIN)
Output current sunk by any I/O and control pin 25
Output current source by any I/O and control pin -25
ΣIIO(PIN)
Total output current sunk by sum of all IOs and control pins(2) 80
Total output current sourced by sum of all IOs and control pins(2) -80
IINJ(PIN)
Injected current on FT, FTf, and B pins(3) -5/+0
Injected current on TC and RST pin(4) ±5
Injected current on TTa pins(5) ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ±25
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer to Table 16: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 16: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 81.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 18. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJMaximum junction temperature 150 °C
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6.3 Operating conditions
6.3.1 General operating conditions
Table 19. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 72
MHzfPCLK1 Internal APB1 clock frequency - 0 36
fPCLK2 Internal APB2 clock frequency - 0 72
VDD Standard operating voltage - 2 3.6 V
VDDA
Analog operating voltage
(OPAMP and DAC not used) Must have a potential
equal to or higher than
VDD
23.6
V
Analog operating voltage
(OPAMP and DAC used) 2.4 3.6
VBAT Backup operating voltage - 1.65 3.6 V
VIN I/O input voltage
TC I/O -0.3 VDD+0.3
V
TTa I/O -0.3 VDDA+0.3
FT and FTf I/O(1)
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
-0.3 5.5
BOOT0 0 5.5
PD
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(2)
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal
characteristics).
LQFP144 - 606
mW
WLCSP100 - 454
LQFP100 - 476
UFBGA100 - 339
LQFP64 - 435
TA
Ambient temperature for 6
suffix version
Maximum power
dissipation -40 85 °C
Low power dissipation(3)
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.7: Thermal characteristics).
-40 105
Ambient temperature for 7
suffix version
Maximum power
dissipation -40 105 °C
Low power dissipation(3) -40 125
TJ Junction temperature range 6 suffix version -40 105 °C
7 suffix version -40 125
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6.3.2 Operating conditions at power-up / power-down
The parameters given in Table 20 are derived from tests performed under the ambient
temperature condition summarized in Table 19.
6.3.3 Embedded reset and power control block characteristics
The parameters given in Table 21 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 19.
Table 20. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate
-
0∞
µs/V
VDD fall time rate 20 ∞
tVDDA
VDDA rise time rate
-
0∞
VDDA fall time rate 20 ∞
Table 21. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VPOR/PDR(1)
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
Power on/power down
reset threshold
Falling edge 1.8(2)
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst(1) PDR hysteresis - - 40 - mV
Table 22. Programmable voltage detector characteristics
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
VPVD0 PVD threshold 0 Rising edge 2.1 2.18 2.26
V
Falling edge 2 2.08 2.16
VPVD1 PVD threshold 1 Rising edge 2.19 2.28 2.37
Falling edge 2.09 2.18 2.27
VPVD2 PVD threshold 2 Rising edge 2.28 2.38 2.48
Falling edge 2.18 2.28 2.38
VPVD3 PVD threshold 3 Rising edge 2.38 2.48 2.58
Falling edge 2.28 2.38 2.48
VPVD4 PVD threshold 4 Rising edge 2.47 2.58 2.69
Falling edge 2.37 2.48 2.59
VPVD5 PVD threshold 5 Rising edge 2.57 2.68 2.79
Falling edge 2.47 2.58 2.69
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6.3.4 Embedded reference voltage
The parameters given in Table 23 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 19.
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
VPVD6 PVD threshold 6 Rising edge 2.66 2.78 2.9
V
Falling edge 2.56 2.68 2.8
VPVD7 PVD threshold 7 Rising edge 2.76 2.88 3
Falling edge 2.66 2.78 2.9
VPVDhyst(2) PVD hysteresis - - 100 - mV
IDD(PVD) PVD current
consumption - - 0.15 0.26 µA
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
Table 22. Programmable voltage detector characteristics (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Table 23. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.16 1.2 1.25 V
–40 °C < TA < +85 °C 1.16 1.2 1.24(1)
1. Data based on characterization results, not tested in production.
V
TS_vrefint
ADC sampling time when
reading the internal
reference voltage
-2.2--µs
VRERINT
Internal reference voltage
spread over the
temperature range
VDD = 3 V ±10 mV - - 10(2)
2. Guaranteed by design, not tested in production.
mV
TCoeff Temperature coefficient - - - 100(2) ppm/°C
Table 24. Internal reference voltage calibration values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
0x1FFF F7BA - 0x1FFF F7BB
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All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Note: The total current consumption is the sum of IDD and IDDA.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in input mode with a static value at VDD or VSS (no load)
•All peripherals are disabled except when explicitly mentioned
•The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
•Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
•When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2
•When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
The parameters given in Table 25 to Table 29 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 19.
Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V
Symbol Parameter Conditions fHCLK
All peripherals enabled All peripherals disabled
Unit
Typ
Max @ TA(1)
Typ
Max @ TA(1)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDD
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
72 MHz 66.4 76.5 76.9 77.4 33.0 37.2 38.1 38.9
mA
64 MHz 59.8 66.4 67.7 68.6 29.7 33.5 34.3 35.0
48 MHz 47.3 53.7 53.8 55.1 23.2 26.2 27.1 28.0
32 MHz 33.3 36.8 37.4 38.5 16.8 19.8 20.6 21.4
24 MHz 26.0 29.4 30.0 31.2 13.5 16.6 17.4 18.6
8 MHz 10.7 13.8 14.4 15.3 6.63 10.2 10.5 11.2
1 MHz 4.27 7.47 8.13 8.90 3.78 7.40 7.70 8.50
Internal
clock (HSI)
64 MHz 55.6 59.6 62.8 63.2 29.4 33.1 34.5 35.0
48 MHz 43.6 47.0 49.2 50.1 23.1 26.2 27.1 28.0
32 MHz 30.8 33.6 35.3 35.8 16.7 19.8 20.6 21.5
24 MHz 24.0 28.0 28.2 29.7 13.5 16.5 17.5 18.4
8 MHz 10.5 13.6 14.7 15.2 6.63 9.74 10.6 11.2
IDD
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
72 MHz 66.2 76.2(2) 76.7 77.2(2) 32.8 36.9(2) 37.7 38.5(2)
64 MHz 59.6 66.2 67.6 68.4 29.3 33.1 33.9 34.4
48 MHz 47.0 53.4 53.6 54.9 22.4 25.6 26.2 27.2
32 MHz 33.0 36.6 37.2 38.1 16.0 19.0 19.5 20.4
24 MHz 25.6 29.0 29.5 30.6 12.8 15.7 16.3 17.6
8 MHz 10.3 13.4 13.8 14.7 6.40 9.48 9.93 10.90
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IDD
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
1 MHz 3.92 7.06 7.54 8.60 3.42 6.53 7.05 8.10
mA
Internal
clock (HSI)
64 MHz 55.4 59.2 62.5 62.9 29.1 32.7 34.0 34.6
48 MHz 43.1 46.7 49.0 49.9 22.8 26.1 26.8 27.8
32 MHz 30.5 33.2 35.0 35.5 15.8 18.8 19.5 20.9
24 MHz 23.8 27.8 27.9 29.2 12.6 15.6 16.3 17.5
8 MHz 9.85 13.1 14.1 14.6 6.20 9.37 10.3 10.7
IDD
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
72 MHz 48.8 53.5(2) 53.6 54.0(2) 7.60 8.20(2) 8.50 9.00(2)
64 MHz 43.5 48.6 49.1 49.3 6.90 7.50 7.80 8.00
48 MHz 33.6 38.1 40.0 41.3 5.30 5.80 6.00 6.40
32 MHz 24.3 27.5 28.1 29.3 3.80 4.10 4.40 4.70
24 MHz 18.6 21.9 22.4 22.6 2.90 3.30 3.40 3.90
8 MHz 8.24 11.27 11.79 12.70 1.36 1.74 1.85 2.00
1 MHz 3.64 6.72 7.36 8.30 0.79 1.17 1.26 1.35
Internal
clock (HSI)
64 MHz 39.7 43.9 45.5 45.8 6.70 7.30 7.40 7.70
48 MHz 30.4 33.9 35.3 36.5 5.10 5.60 5.70 6.10
32 MHz 21.9 25.8 26.2 26.7 3.60 4.10 4.20 4.50
24 MHz 17.0 20.2 21.5 21.7 2.98 3.41 3.46 3.57
8 MHz 7.81 11.0 11.7 12.4 1.41 1.74 1.81 1.87
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued)
Symbol Parameter Conditions fHCLK
All peripherals enabled All peripherals disabled
Unit
Typ
Max @ TA(1)
Typ
Max @ TA(1)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
Table 26. Typical and maximum current consumption from the VDDA supply
Symbol Parameter Conditions
(1) fHCLK
VDDA = 2.4 V VDDA = 3.6 V
Unit
Typ
Max @ TA(2)
Typ
Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDDA
Supply
current in
Run mode,
code
executing
from Flash
or RAM
HSE
bypass
72 MHz 220 243 255 260 241 264 281 287
µA
64 MHz 194 215 226 231 212 233 248 254
48 MHz 145 164 172 176 158 176 187 192
32 MHz 100 116 121 124 108 123 130 134
24 MHz 78 92 96 98 85 97 102 105
8 MHz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5
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STM32F302xD STM32F302xE Electrical characteristics
146
IDDA
Supply
current in
Run mode,
code
executing
from Flash
or RAM
HSE
bypass 1 MHz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5
µA
HSI clock
64 MHz 266 290 301 306 295 320 335 341
48 MHz 216 237 247 251 240 262 274 279
32 MHz 170 188 196 199 190 208 217 221
24 MHz 148 164 170 172 166 182 189 192
8 MHz 70 78 81 82 84 92 95 97
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
Table 26. Typical and maximum current consumption from the VDDA supply (continued)
Symbol Parameter Conditions
(1) fHCLK
VDDA = 2.4 V VDDA = 3.6 V
Unit
Typ
Max @ TA(2)
Typ
Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
Table 27. Typical and maximum VDD consumption in Stop and Standby modes
Symbol Parameter Conditions
Typ @VDD (VDD=VDDA)Max
Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply
current in
Stop mode
Regulator in run mode,
all oscillators OFF 18.4 18.7 18.8 18.9 19.0 19.1 47 435 940
µA
Regulator in low-power
mode, all oscillators OFF 6.80 6.94 7.11 7.18 7.26 7.39 33 408 898
Supply
current in
Standby
mode
LSI ON and IWDG ON 0.72 0.87 0.99 1.10 1.23 1.37 - - -
LSI OFF and IWDG OFF 0.57 0.68 0.76 0.85 0.94 1.03 6.2 8.6 13.5
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Table 28. Typical and maximum VDDA consumption in Stop and Standby modes
Symbol Parameter Conditions
Typ @VDD (VDD = VDDA)Max
(1)
Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA =
25 °C
TA =
85 °C
TA =
105 °C
IDDA
Supply
current in
Stop mode
VDDA supervisor ON
Regulator in run/low-
power mode, all
oscillators OFF
1.72 1.85 1.97 2.10 2.25 2.41 10.7 11 12
µA
Supply
current in
Standby
mode
LSI ON and IWDG ON 2.08 2.26 2.43 2.61 2.82 3.05 - - -
LSI OFF and IWDG
OFF 1.60 1.73 1.85 1.98 2.13 2.29 3.6 4 6
Supply
current in
Stop mode
VDDA supervisor OFF
Regulator in run/low-
power mode, all
oscillators OFF
1.00 1.02 1.05 1.10 1.16 1.24 - - -
Supply
current in
Standby
mode
LSI ON and IWDG ON 1.36 1.43 1.51 1.61 1.74 1.88 - - -
LSI OFF and IWDG
OFF 0.88 0.90 0.93 0.98 1.05 1.12 - - -
1. Data based on characterization results, not tested in production.
Table 29. Typical and maximum current consumption from VBAT supply
Symbol Para
meter
Conditions
(1)
Typ @VBAT
Max
@VBAT = 3.6 V(2)
Unit
1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V TA =
25°C
TA =
85°C
TA =
105°C
IDD_VBAT
Backup
domain
supply
current
LSE & RTC
ON; “Xtal
mode” lower
driving
capability;
LSEDRV[1:
0] = '00'
0.48 0.50 0.52 0.58 0.65 0.72 0.80 0.90 1.1 1.5 2.0
µA
LSE & RTC
ON; “Xtal
mode”
higher
driving
capability;
LSEDRV[1:
0] = '11'
0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5 2.2 2.9
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
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STM32F302xD STM32F302xE Electrical characteristics
146
Figure 14. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] 00’)
Typical current consumption
The MCU is placed under the following conditions:
•VDD = VDDA = 3.3 V
•All I/O pins available on each package are in analog input configuration
•The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
•When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
•PLL is used for frequencies greater than 8 MHz
•AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
# # # #
6
6
6
6
6
6
6
6
4
!#
!
)6"!4
-36
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Table 30. Typical current consumption in Run mode, code with data processing running
from Flash
Symbol Parameter Conditions fHCLK
Typ
Unit
Peripherals
enabled
Peripherals
disabled
IDD
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash
72 MHz 60.7 27.3
mA
64 MHz 54.3 24.1
48 MHz 42.1 19.4
32 MHz 28.7 13.9
24 MHz 22.2 11.0
16 MHz 15.4 7.9
8 MHz 8.3 4.51
4 MHz 5.14 3.02
2 MHz 3.37 2.21
1 MHz 2.49 1.80
500 kHz 2.04 1.57
125 kHz 1.71 0.84
IDDA(1) (2)
Supply current in
Run mode from
VDDA supply
72 MHz 239.7
µA
64 MHz 210.5
48 MHz 155.6
32 MHz 105.5
24 MHz 81.9
16 MHz 58.6
8 MHz 1.16
4 MHz 1.16
2 MHz 1.16
1 MHz 1.16
500 kHz 1.16
125 kHz 1.16
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp is not included. Refer to the tables of characteristics in the subsequent sections.
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Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM
Symbol Parameter Conditions fHCLK
Typ
Unit
Peripherals
enabled
Peripherals
disabled
IDD
Supply current in
Sleep mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
72 MHz 43.0 7.4
mA
64 MHz 38.3 6.8
48 MHz 29.0 5.29
32 MHz 19.7 3.91
24 MHz 15.2 3.19
16 MHz 10.8 2.46
8 MHz 5.85 1.55
4 MHz 3.80 1.45
2 MHz 2.67 1.32
1 MHz 2.12 1.22
500 kHz 1.83 1.19
125 kHz 1.60 0.83
IDDA(1) (2)
Supply current in
Sleep mode from
VDDA supply
72 MHz 239.7
µA
64 MHz 210.5
48 MHz 155.6
32 MHz 105.5
24 MHz 81.9
16 MHz 58.6
8 MHz 1.16
4 MHz 1.16
2 MHz 1.16
1 MHz 1.16
500 kHz 1.16
125 kHz 1.16
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp is not included. Refer to the tables of characteristics in the subsequent sections.
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I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Ta ble 66: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (seeTable 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
where:
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDD fSW C××=
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Table 32. Switching output I/O current consumption
Symbol Parameter Conditions(1)
1. CS = 5 pF (estimated value).
I/O toggling
frequency (fSW)Typ Unit
ISW
I/O current
consumption
VDD = 3.3 V
Cext = 0 pF
C = CINT + CEXT+ CS
2 MHz 0.90
mA
4 MHz 0.93
8 MHz 1.16
18 MHz 1.60
36 MHz 2.51
48 MHz 2.97
VDD = 3.3 V
Cext = 10 pF
C = CINT + CEXT +CS
2 MHz 0.93
4 MHz 1.06
8 MHz 1.47
18 MHz 2.26
36 MHz 3.39
48 MHz 5.99
VDD = 3.3 V
Cext = 22 pF
C = CINT + CEXT +CS
2 MHz 1.03
4 MHz 1.30
8 MHz 1.79
18 MHz 3.01
36 MHz 5.99
VDD = 3.3 V
Cext = 33 pF
C = CINT + CEXT+ CS
2 MHz 1.10
4 MHz 1.31
8 MHz 2.06
18 MHz 3.47
36 MHz 8.35
VDD = 3.3 V
Cext = 47 pF
C = CINT + CEXT+ CS
2 MHz 1.20
4 MHz 1.54
8 MHz 2.46
18 MHz 4.51
36 MHz 9.98
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
•all I/O pins are in analog input configuration
•all peripherals are disabled unless otherwise mentioned
•the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
•ambient operating temperature at 25°C and VDD = VDDA = 3.3 V.
Table 33. Peripheral current consumption
Peripheral
Typical consumption(1)
Unit
IDD
BusMatrix (2) 8.3
µA/MHz
DMA1 7.0
DMA2 5.4
FSMC 35.0
CRC 1.5
GPIOH 1.3
GPIOA 5.4
GPIOB 5.3
GPIOC 5.4
GPIOD 5.0
GPIOE 5.4
GPIOF 5.2
GPIOG 5.0
TSC 5.2
ADC1&2 15.4
APB2-Bridge (3) 3.1
SYSCFG 4.0
TIM1 26.0
USART1 17.7
SPI4 6.2
TIM15 11.9
TIM16 8.0
TIM17 8.5
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STM32F302xD STM32F302xE Electrical characteristics
146
APB1-Bridge (3) 6.7
µA/MHz
TIM2 39.2
TIM3 30.8
TIM4 31.3
TIM6 4.3
WWDG 1.3
SPI2 33.6
SPI3 33.9
USART2 39.3
USART3 39.3
UART4 29.8
UART5 27.0
I2C1 6.7
I2C2 6.4
USB 14.7
CAN 25.6
PWR 3.7
DAC 22.1
I2C3 6.8
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
Table 33. Peripheral current consumption (continued)
Peripheral
Typical consumption(1)
Unit
IDD
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6.3.6 Wakeup time from low-power mode
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•For Stop or Sleep mode: the wakeup event is WFE.
•WKUP1 (PA0) pin is used to wake up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 19.
Table 34. Low-power mode wakeup timings
Symbol Parameter Conditions
Typ @VDD, VDD = VDDA
Max Unit
2.0 V 2.4 V 2.7 V 3 V 3.3 V 3.6 V
tWUSTOP
Wakeup from
Stop mode
Regulator in
run mode 5.4 5.2 5.2 5.1 5.0 4.9 5.6
µs
Regulator in
low power
mode
12.0 10.1 9.2 8.6 8.1 7.8 12.9
tWUSTANDBY(1)
Wakeup from
Standby
mode
LSI and
IWDG OFF 91.0 77.1 71.7 68.0 65.1 63.1 139
tWUSLEEP
Wakeup from
Sleep mode -6-
CPU
clock
cycles
1. Data based on characterization results, not tested in production.
Table 35. Wakeup time using USART
Symbol Parameter Conditions Typ Max Unit
tWUUSART
Wakeup time needed to
calculate the maximum
USART baudrate allowing
to wakeup up from stop
mode when USART clock
source is HSI
Stop mode with
main regulator in
low power mode
-13.125
µs
Stop mode with
main regulator in
run mode
- 3.125
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6.3.7 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.15. However, the
recommended clock input waveform is shown in Figure 15.
Figure 15. High-speed external clock source AC timing diagram
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.15. However, the
recommended clock input waveform is shown in Figure 16.
Table 36. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
User external clock source
frequency(1)
1. Guaranteed by design, not tested in production.
-
1832MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSEH)
tw(HSEL)
OSC_IN high or low time(1) 15 - -
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --20
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Electrical characteristics STM32F302xD STM32F302xE
84/168 DocID026900 Rev 4
Figure 16. Low-speed external clock source AC timing diagram
Table 37. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency(1)
1. Guaranteed by design, not tested in production.
-
- 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD
V
VLSEL
OSC32_IN input pin low level
voltage VSS -0.3V
DD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
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DocID026900 Rev 4 85/168
STM32F302xD STM32F302xE Electrical characteristics
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 38. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Table 38. HSE oscillator characteristics
Symbol Parameter Conditions(1)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min(2)
2. Guaranteed by design, not tested in production.
Typ Max(2) Unit
fOSC_IN Oscillator frequency - 4 8 32 MHz
RFFeedback resistor - - 200 - kΩ
IDD HSE current consumption
During startup(3)
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
--8.5
mA
VDD= 3.3 V, Rm= 30Ω,
CL=10 pF@8 MHz -0.4-
VDD= 3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz -0.5-
VDD= 3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz -0.8-
VDD= 3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz -1-
VDD= 3.3 V, Rm= 30Ω,
CL=20 pF@32 MHz -1.5-
gmOscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
Startup time VDD is stabilized - 2 - ms
Electrical characteristics STM32F302xD STM32F302xE
86/168 DocID026900 Rev 4
Figure 17. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
IDD LSE current consumption
LSEDRV[1:0]=00
lower driving capability -0.50.9
µA
LSEDRV[1:0]=01
medium low driving capability --1
LSEDRV[1:0]=10
medium high driving capability --1.3
LSEDRV[1:0]=11
higher driving capability --1.6
gm
Oscillator
transconductance
LSEDRV[1:0]=00
lower driving capability 5- -
µA/V
LSEDRV[1:0]=01
medium low driving capability 8--
LSEDRV[1:0]=10
medium high driving capability 15 - -
LSEDRV[1:0]=11
higher driving capability 25 - -
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
DocID026900 Rev 4 87/168
STM32F302xD STM32F302xE Electrical characteristics
146
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8 Internal clock source characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
High-speed internal (HSI) RC oscillator
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Table 40. HSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 8 - MHz
TRIM HSI user trimming step - - - 1(2)
2. Guaranteed by design, not tested in production.
%
DuCy(HSI) Duty cycle - 45(2) -55
(2) %
ACCHSI
Accuracy of the HSI
oscillator
TA = -40 to 105°C -2.8(3)
3. Data based on characterization results, not tested in production.
-3.8
(3)
%
TA = -10 to 85°C -1.9(3) -2.3
(3)
TA = 0 to 85°C -1.9(3) -2
(3)
TA = 0 to 70°C -1.3(3) -2
(3)
TA = 0 to 55°C -1(3) -2
(3)
TA = 25°C(4)
4. Factory calibrated, parts not soldered.
-1 - 1
tSU(HSI) HSI oscillator startup time - 1(2) -2
(2) μs
IDDA(HSI)
HSI oscillator power
consumption - - 80 100(2) μA
Electrical characteristics STM32F302xD STM32F302xE
88/168 DocID026900 Rev 4
Figure 19. HSI oscillator accuracy characterization results for soldered parts
Low-speed internal (LSI) RC oscillator
6.3.9 PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
Table 41. LSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz
tsu(LSI)(2)
2. Guaranteed by design, not tested in production.
LSI oscillator startup time - - 85 µs
IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
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Table 42. PLL characteristics
Symbol Parameter
Value
Unit
Min Typ Max
fPLL_IN
PLL input clock(1)
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
1(2) -24
(2) MHz
PLL input clock duty cycle 40(2) -60
(2) %
fPLL_OUT PLL multiplier output clock 16(2) -72MHz
tLOCK PLL lock time - - 200(2) µs
Jitter Cycle-to-cycle jitter - - 300(2)
2. Guaranteed by design, not tested in production.
ps
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6.3.10 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
6.3.11 FSMC characteristics
Unless otherwise specified, the parameters given in Table 45 to Table 60 for the FSMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 19 with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics: for more details on the input/output
characteristics.
Table 43. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by design, not tested in production.
Unit
tprog 16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs
tERASE Page (2 KB) erase time TA = –40 to +105 °C 20 - 40 ms
tME Mass erase time TA = –40 to +105 °C 20 - 40 ms
IDD Supply current Write mode - - 10 mA
Erase mode - - 12 mA
Table 44. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Data based on characterization results, not tested in production.
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years1 kcycle(2) at TA = 105 °C 10
10 kcycle(2) at TA = 55 °C 20
Electrical characteristics STM32F302xD STM32F302xE
90/168 DocID026900 Rev 4
Asynchronous waveforms and timings
Figure 20 to Figure 23 represent asynchronous waveforms and Table 45 to Table 52
provide the corresponding timings. The results shown in these tables are obtained with the
following FSMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
•NOR NWAIT pulse width= 1THCLK
In all the timing tables, the THCLK is the HCLK clock period.
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
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STM32F302xD STM32F302xE Electrical characteristics
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Table 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
1. Based on characterization, not tested in production
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 2THCLK– 1 2THCLK+1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2THCLK 2THCLK+ 1.5
th(NE_NOE)
FMC_NOE high to FMC_NE high hold
time 0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 (NA)
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 6 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK +7 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2
tw(NADV) FMC_NADV low time - THCLK +1.5
Table 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7THCLK +0.5 7THCLK+ 1
ns
tw(NOE) FMC_NWE low time 6THCLK -1.5 6THCLK +2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4THCLK +5 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4THCLK-3 -
Electrical characteristics STM32F302xD STM32F302xE
92/168 DocID026900 Rev 4
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK-1 3THCLK+2
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK+0.5 THCLK+1
tw(NWE) FMC_NWE low time THCLK-2 THCLK+1
th(NE_NWE)
FMC_NWE high to FMC_NE high hold
time THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK-1.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK-0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+ 3
th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2.5
tw(NADV) FMC_NADV low time - THCLK+2
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DocID026900 Rev 4 93/168
STM32F302xD STM32F302xE Electrical characteristics
146
Table 48. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+1 8THCLK+2
ns
tw(NWE) FMC_NWE low time 6THCLK-1 6THCLK+2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK-0.5 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4THCLK+2 -
Table 49. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+2 8THCLK+2
ns
tw(NOE) FMC_NWE low time 6THCLK-1 6THCLK+1.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4THCLK+6 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4THCLK-4 -
Electrical characteristics STM32F302xD STM32F302xE
94/168 DocID026900 Rev 4
Figure 22. Asynchronous multiplexed PSRAM/NOR read timings
Table 50. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK-0.5 3THCLK+1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK 2THCLK+1
tw(NOE) FMC_NOE low time THCLK-2 THCLK+2
th(NE_NOE)
FMC_NOE high to FMC_NE high hold
time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 1.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 2
tw(NADV) FMC_NADV low time THCLK-2 THCLK+2
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high 0 -
th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
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STM32F302xD STM32F302xE Electrical characteristics
146
Figure 23. Asynchronous multiplexed PSRAM/NOR write timings
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
ns
tsu(Data_NE) Data to FMC_NEx high setup time THCLK -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Based on characterization, not tested in production.
Table 50. Asynchronous multiplexed PSRAM/NOR read timings(1) (continued)
Symbol Parameter Min Max Unit
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96/168 DocID026900 Rev 4
Synchronous waveforms and timings
Figure 24 and Figure 27 present the synchronous waveforms and Table 53 to Table 56
provide the corresponding timings. The results shown in these tables are obtained with the
following FSMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable;
•MemoryType = FMC_MemoryType_CRAM;
•WriteBurst = FMC_WriteBurst_Enable;
•CLKDivision = 1;
•DataLatency = 2 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK =
36 MHz).
Table 51. Asynchronous multiplexed PSRAM/NOR write timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4THCLK-1 4THCLK+1
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK THCLK+0.5
tw(NWE) FMC_NWE low time 2THCLK-0.5 2THCLK+1
th(NE_NWE)
FMC_NWE high to FMC_NE high hold
time THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 1 2.5
tw(NADV) FMC_NADV low time THCLK-2 THCLK+2
th(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high) THCLK-2 -
th(A_NWE) Address hold time after FMC_NWE high THCLK-1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK-0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1
tv(Data_NADV) FMC_NADV high to Data valid - THCLK +3.5
th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 -
Table 52. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9THCLK 9THCLK+0.5
ns
tw(NWE) FMC_NWE low time 6THCLK 6THCLK+2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+6 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 5THCLK-5 -
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Figure 24. Synchronous multiplexed NOR/PSRAM read timings
Table 53. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 5
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x=
0…2) THCLK+1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) -3
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) 0 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 6
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
&-#?#,+
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7!)40/,B
TW#,+ TW#,+
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TD#,+,.%X, TD#,+(.%X(
TD#,+,.!$6,
TD#,+,!6
TD#,+,.!$6(
TD#,+(!)6
TD#,+,./%, TD#,+(./%(
TD#,+,!$6
TD#,+,!$)6
TSU!$6#,+(
TH#,+(!$6
TSU!$6#,+( TH#,+(!$6
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
-36
Electrical characteristics STM32F302xD STM32F302xE
98/168 DocID026900 Rev 4
Figure 25. Synchronous multiplexed PSRAM write timings
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
ns
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before
FMC_CLK high 4 -
th(CLKH-ADV)
FMC_A/D[15:0] valid data after
FMC_CLK high 6 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Based on characterization, not tested in production.
Table 53. Synchronous multiplexed NOR/PSRAM read timings(1) (continued)
Symbol Parameter Min Max Unit
&-#?#,+
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7!)4#&'B
7!)40/,B
TW#,+ TW#,+
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TD#,+,.%X, TD#,+(.%X(
TD#,+,.!$6,
TD#,+,!6
TD#,+,.!$6(
TD#,+(!)6
TD#,+(.7%(
TD#,+,.7%,
TD#,+(.",(
TD#,+,!$6
TD#,+,!$)6 TD#,+,$ATA
TSU.7!)46#,+( TH#,+(.7!)46
-36
TD#,+,$ATA
&-#?.",
DocID026900 Rev 4 99/168
STM32F302xD STM32F302xE Electrical characteristics
146
Table 54. Synchronous multiplexed PSRAM write timings(1) (2)
1. Based on characterization, not tested in production.
2. CL = 30 pF.
Symbol Parameter Min Max Unit
tw(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6
V2THCLK-1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 5.5
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x=
0…2) THCLK+1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) -0
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) 0 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 5.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 7.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA)
FMC_A/D[15:0] valid data after
FMC_CLK low -8
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 6
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 5 -
Electrical characteristics STM32F302xD STM32F302xE
100/168 DocID026900 Rev 4
Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings
Table 55. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK-1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 5
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2) THCLK+1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) - 7
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) THCLK -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 6
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK+1 -
tsu(DV-CLKH)
FMC_D[15:0] valid data before
FMC_CLK high 3.5 -
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TD#,+,!6 TD#,+(!)6
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TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
-36
&-#?.!$6
TD#,+,.!$6, TD#,+,.!$6(
DocID026900 Rev 4 101/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 27. Synchronous non-multiplexed PSRAM write timings
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK
high 5 -
ns
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. Based on characterization, not tested in production.
Table 55. Synchronous non-multiplexed NOR/PSRAM read timings(1) (continued)
Symbol Parameter Min Max Unit
-36
&-#?#,+
&-#?.%X
&-#?!;=
&-#?.7%
&-#?$;= $ $
&-#?.7!)4
7!)4#&'B7!)40/,B
TW#,+ TW#,+
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TD#,+,.%X, TD#,+(.%X(
TD#,+,!6 TD#,+(!)6
TD#,+(.7%(
TD#,+,.7%,
TD#,+,$ATA
TSU.7!)46#,+(
TH#,+(.7!)46
&-#?.!$6
TD#,+,.!$6, TD#,+,.!$6(
TD#,+,$ATA
&-#?.",
TD#,+(.",(
Electrical characteristics STM32F302xD STM32F302xE
102/168 DocID026900 Rev 4
PC Card/CompactFlash controller waveforms and timings
Figure 28 to Figure 33 present the PC Card/Compact Flash controller waveforms, and
Table 57 to Table 58 provide the corresponding timings. The results shown in this table are
obtained with the following FSMC configuration:
•COM.FMC_SetupTime = 0x04;
•COM.FMC_WaitSetupTime = 0x07;
•COM.FMC_HoldSetupTime = 0x04;
•COM.FMC_HiZSetupTime = 0x05;
•ATT.FMC_SetupTime = 0x04;
•ATT.FMC_WaitSetupTime = 0x07;
•ATT.FMC_HoldSetupTime = 0x04;
•ATT.FMC_HiZSetupTime = 0x05;
•IO.FMC_SetupTime = 0x04;
•IO.FMC_WaitSetupTime = 0x07;
•IO.FMC_HoldSetupTime = 0x04;
•IO.FMC_HiZSetupTime = 0x05;
•TCLRSetupTime = 0;
•TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
Table 56. Synchronous non-multiplexed PSRAM write timings(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK-1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 6
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2) THCLK+1.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) - 6.5
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) 0 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+2 -
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK
low - 7.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 7
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
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STM32F302xD STM32F302xE Electrical characteristics
146
Table 57. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tv(NCEx-A) FMC_Ncex low to FMC_Ay valid - 0
ns
th(NCEx_AI) FMC_NCEx high to FMC_Ax invalid 2.5 -
td(NREG-NCEx) FMC_NCEx low to FMC_NREG valid - 2
th(NCEx-NREG) FMC_NCEx high to FMC_NREG invalid 0 -
td(NCEx-NWE) FMC_NCEx low to FMC_NWE low - 5THCLK+2
tw(NWE) FMC_NWE low width 8THCLK 8THCLK+0.5
td(NWE_NCEx) FMC_NWE high to FMC_NCEx high 5THCLK-1 -
tv (NWE-D) FMC_NWE low to FMC_D[15:0] valid - 5
th (NWE-D) FMC_NWE high to FMC_D[15:0] invalid 4THCLK-1 -
td (D-NWE)
FMC_D[15:0] valid before FMC_NWE
high 13THCLK-3 -
td(NCEx-NOE) FMC_NCEx low to FMC_NOE low - 5THCLK+2
tw(NOE) FMC_NOE low width 8THCLK-1 8THCLK+2
td(NOE_NCEx) FMC_NOE high to FMC_NCEx high 5THCLK-1 -
tsu (D-NOE)
FMC_D[15:0] valid data before
FMC_NOE high THCLK+2 -
th(NOE-D) FMC_N0E high to FMC_D[15:0] invalid 0 -
Electrical characteristics STM32F302xD STM32F302xE
104/168 DocID026900 Rev 4
Figure 28. PC Card/CompactFlash controller waveforms for common memory
read access
1. FMC_NCE4_2 remains high (inactive during 8-bit access.
Figure 29. PC Card/CompactFlash controller waveforms for common memory
write access
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&-#?.)/2$
TD.7%.#%?
TD$.7%
&-#?.#%? (IGH
DocID026900 Rev 4 105/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 30. PC Card/CompactFlash controller waveforms for attribute memory
read access
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
-36
TD.#%?./% TW./%
TSU$./% TH./%$
TV.#%?! TH.#%?!)
TD.2%'.#%? TH.#%?.2%'
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TD./%.#%?
(IGH
Electrical characteristics STM32F302xD STM32F302xE
106/168 DocID026900 Rev 4
Figure 31. PC Card/CompactFlash controller waveforms for attribute memory
write access
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Table 58. Switching characteristics for PC Card/CF read and write cycles in I/O
space(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NIOWR) FMC_NIOWR low width 8THCLK-0.5 -
ns
tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid - 5.5
th(NIOWR-D)
FMC_NIOWR high to FMC_D[15:0]
invalid 4THCLK-0.5 -
td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid - 5THCLK+1
th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid 4THCLK+0.5 -
td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid - 5THCLK
th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid 6THCLK+2 -
tw(NIORD) FMC_NIORD low width 8THCLK-1 8THCLK+1
tsu(D-NIORD)
FMC_D[15:0] valid before FMC_NIORD
high THCLK+2 -
td(NIORD-D)
FMC_D[15:0] valid after FMC_NIORD
high 0-
-36
TW.7%
TV.#%?!
TD.2%'.#%?
TH.#%?!)
TH.#%?.2%'
TV.7%$
&-#?.7%
&-#?./%
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&-#?!;=
&-#?.#%?
&-#?.#%?
&-#?.2%'
&-#?.)/72
&-#?.)/2$
TD.7%.#%?
(IGH
TD.#%?.7%
DocID026900 Rev 4 107/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 32. PC Card/CompactFlash controller waveforms for I/O space read access
Figure 33. PC Card/CompactFlash controller waveforms for I/O space write access
-36
TD.)/2$.#%? TW.)/2$
TSU$.)/2$ TD.)/2$$
TV.#%X! TH.#%?!)
&-#?.7%
&-#?./%
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TD.#%?.)/72 TW.)/72
TV.#%X! TH.#%?!)
TH.)/72$
!44X():
TV.)/72$
-36
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&-#?./%
&-#?$;=
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&-#?.#%?
&-#?.#%?
&-#?.2%'
&-#?.)/72
&-#?.)/2$
Electrical characteristics STM32F302xD STM32F302xE
108/168 DocID026900 Rev 4
NAND controller waveforms and timings
Figure 34 and Figure 35 present the NAND controller synchronous waveforms, and
Table 59 and Table 60 provide the corresponding timings. The results shown in this table
are obtained with the following FSMC configuration:
•COM.FMC_SetupTime = 0x01;
•COM.FMC_WaitSetupTime = 0x03;
•COM.FMC_HoldSetupTime = 0x02;
•COM.FMC_HiZSetupTime = 0x03;
•ATT.FMC_SetupTime = 0x01;
•ATT.FMC_WaitSetupTime = 0x03;
•ATT.FMC_HoldSetupTime = 0x02;
•ATT.FMC_HiZSetupTime = 0x03;
•Bank = FMC_Bank_NAND;
•MemoryDataWidth = FMC_MemoryDataWidth_16b;
•ECC = FMC_ECC_Enable;
•ECCPageSize = FMC_ECCPageSize_512Bytes;
•TCLRSetupTime = 0;
•TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
Figure 34. NAND controller read timings
&-#?.7%
&-#?./%.2%
&-#?$;=
TSU$./% TH./%$
-36
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#,%&-#?!
&-#?.#%X
TD!,%./% TH./%!,%
DocID026900 Rev 4 109/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 35. NAND controller write timings
Table 59. Switching characteristics for NAND Flash read cycles(1) (2)
1. Based on characterization, not tested in production.
2. CL = 30 pF
Symbol Parameter Min Max Unit
tw(NOE) FMC_NOE low width 6THCLK 6THCLK + 2
ns
tsu(D-NOE)
FMC_D[15-0] valid data before
FMC_NOE high THCLK+5 -
th(NOE-D)
FMC_D[15-0] valid data after FMC_NOE
high 0-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 6THCLK -0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 6THCLK-1 -
Table 60. Switching characteristics for NAND Flash write cycles(1)
1. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
tw(NWE) FMC_NWE low width 4THCLK-0.5 4THCLK + 1.5
ns
tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid - 3.5
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK -1.5 -
td(D-NWE)
FMC_D[15-0] valid before FMC_NWE
high 5THCLK – 3 -
td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 4THCLK+2
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2THCLK-1 -
-36
TH.7%$
TV.7%$
&-#?.7%
&-#?./%.2%
&-#?$;=
!,%&-#?!
#,%&-#?!
&-#?.#%X
TD!,%.7% TH.7%!,%
Electrical characteristics STM32F302xD STM32F302xE
110/168 DocID026900 Rev 4
6.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling two LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 61. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Table 61. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
DocID026900 Rev 4 111/168
STM32F302xD STM32F302xE Electrical characteristics
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Pre qualification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
6.3.13 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 62. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/72 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP144 package
compliant with IEC
61967-2
0.1 to 30 MHz 7
dBµV30 to 130 MHz 15
130 MHz to 1GHz 31
SAE EMI Level 4 -
Table 63. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1)
1. Data based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C, conforming
to ANSI/JEDEC JS-001 22000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1 C3 250
Electrical characteristics STM32F302xD STM32F302xE
112/168 DocID026900 Rev 4
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.14 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The test results are given in Table 65.
Table 64. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II Level A
Table 65. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on BOOT0 -0 NA
mA
Injected current on PF3, PC1, PC2, PA1, PA2, PA3,
PA4, PA5, PA6, PA7, PB0, PB1, PE8, PE9, PE10, PE11,
PE12, PE13, PE14, PE15, PB13, PB14, PB15, PD8,
PD9, PD10, PD11, PD12, PD13, PD14 pins with
induced leakage current on adjacent pins less than -
50 µA or more than +400 µA
-5 +5
Injected current on PF2, PF4, PC0, PC1, PC2, PC3,
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PC4, PC5,
PB2, PB11 with induced leakage current on other pins
from this group less than -50 µA or more than +400 µA
-5 +5
DocID026900 Rev 4 113/168
STM32F302xD STM32F302xE Electrical characteristics
146
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.15 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 66 are derived from tests
performed under the conditions summarized in Table 19. All I/Os are CMOS and TTL
compliant.
IINJ
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
P15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with
induced leakage current on other pins from this group
less than -50 µA or more than +400 µA
-5 +5
mA
Injected current on any other FT and FTf pins -5 NA
Injected current on any other pins -5 +5
Table 65. I/O current injection susceptibility (continued)
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
Table 66. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
Low level input
voltage
TC and TTa I/O - - 0.3 VDD+0.07 (1)
V
FT and FTf I/O - - 0.475 VDD-0.2 (1)
BOOT0 - - 0.3 VDD–0.3 (1)
All I/Os except BOOT0 - - 0.3 VDD (2)
VIH
High level input
voltage
TC and TTa I/O 0.445 VDD+0.398 (1) --
V
FT and FTf I/O 0.5 VDD+0.2 (1) --
BOOT0 0.2 VDD+0.95 (1) --
All I/Os except BOOT0 0.7 VDD (2) --
Vhys Schmitt trigger
hysteresis
TC and TTa I/O - 200 (1) -
mVFT and FTf I/O - 100 (1) -
BOOT0 - 300 (1) -
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 36 and Figure 37 for standard I/Os.
Figure 36. TC and TTa I/O input characteristics - CMOS port
Ilkg
Input leakage
current (3)
TC, FT and FTf I/O
TTa I/O in digital mode
VSS ≤ VIN ≤ VDD
--±0.1
µA
TTa I/O in digital mode
VDD ≤ VIN ≤ VDDA
--1
TTa I/O in analog mode
VSS ≤ VIN ≤ VDDA
--±0.2
FT and FTf I/O(4)
VDD ≤ VIN ≤ 5 V --10
RPU
Weak pull-up
equivalent resistor(5) VIN = VSS 25 40 55 kΩ
RPD
Weak pull-down
equivalent resistor(5) VIN = VDD 25 40 55 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 65: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
Table 66. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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STM32F302xD STM32F302xE Electrical characteristics
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Figure 37. TC and TTa I/O input characteristics - TTL port
Figure 38. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
Figure 39. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 17).
•The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 17).
Output voltage levels
Unless otherwise specified, the parameters given in Table 67 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 19. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL
compliant.
Table 67. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1) Output low level voltage for an I/O pin CMOS port(2)
IIO = +48 mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH(3) Output high level voltage for an I/O pin VDD–0.4 -
VOL (1) Output low level voltage for an I/O pin TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-0.4
VOH (3) Output high level voltage for an I/O pin 2.4 -
VOL(1)(4) Output low level voltage for an I/O pin IIO = +20 mA
2.7 V < VDD < 3.6 V
-1.3
VOH(3)(4) Output high level voltage for an I/O pin VDD–1.3 -
VOL(1)(4) Output low level voltage for an I/O pin IIO = +6 mA
2 V < VDD < 2.7 V
-0.4
VOH(3)(4) Output high level voltage for an I/O pin VDD–0.4 -
VOLFM+(4)(4) Output low level voltage for an FTf I/O pin in
FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V -0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 17 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 17 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
4. Data based on design simulation.
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STM32F302xD STM32F302xE Electrical characteristics
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 40 and
Table 68, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 19.
Table 68. I/O AC characteristics(1)
OSPEEDRy [1:0]
value(1) Symbol Parameter Conditions Min Max Unit
x0
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 2(3) MHz
tf(IO)out
Output high to low level
fall time CL = 50 pF, VDD = 2 V to 3.6 V
- 125(3)
ns
tr(IO)out
Output low to high level
rise time - 125(3)
01
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 10(3) MHz
tf(IO)out
Output high to low level
fall time CL = 50 pF, VDD = 2 V to 3.6 V
-25
(3)
ns
tr(IO)out
Output low to high level
rise time -25
(3)
11
fmax(IO)out Maximum frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50(3)
MHzCL = 50 pF, VDD = 2.7 V to 3.6 V - 30(3)
CL = 50 pF, VDD = 2 V to 2.7 V - 20(3)
tf(IO)out
Output high to low level
fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
tr(IO)out
Output low to high level
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
FM+
configuration(4)
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 to 3.6 V
-2
(4) MHz
tf(IO)out
Output high to low level
fall time -12
(4)
ns
tr(IO)out
Output low to high level
rise time -34
(4)
-t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
-10
(3) -ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0365 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 40.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the reference manual RM0365 for a description of FM+
I/O mode configuration.
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Figure 40. I/O AC characteristics definition
1. See Table 68: I/O AC characteristics.
6.3.16 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 66).
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 19.
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Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1) NRST Input low level voltage - - - 0.3VDD+
0.07(1)
V
VIH(NRST)(1) NRST Input high level voltage - 0.445VDD+
0.398(1) --
Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV
RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ
VF(NRST)(1) NRST Input filtered pulse - - - 100(1) ns
VNF(NRST)(1) NRST Input not filtered pulse - 500(1) --ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
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STM32F302xD STM32F302xE Electrical characteristics
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Figure 41. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 69. Otherwise the reset is not taken into account by the device.
3. Place the external capacitor 0.1u F on NRST as close as possible to the chip.
6.3.17 Timer characteristics
The parameters given in Table 70 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
-1-
tTIMxCLK
fTIMxCLK = 72 MHz 13.9 - ns
fTIMxCLK = 144 MHz 6.95 - ns
fEXT Timer external clock
frequency on CH1 to CH4
-0
fTIMxCLK/2 MHz
fTIMxCLK = 72 MHz 0 36 MHz
ResTIM Timer resolution TIMx (except TIM2) - 16 bit
TIM2 - 32
tCOUNTER 16-bit counter clock period
- 1 65536 tTIMxCLK
fTIMxCLK = 72 MHz 0.0139 910 µs
fTIMxCLK = 144 MHz 0.0069 455 µs
tMAX_COUNT Maximum possible count
with 32-bit counter
- - 65536 × 65536 tTIMxCLK
fTIMxCLK = 72 MHz - 59.65 s
fTIMxCLK = 144 MHz - 29.825 s
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6.3.18 Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev.03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s
•Fast-mode Plus (Fm+): with a bit rate up to 1Mbits/s
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support
Fm+ low level output current maximum requirement. Refer to Section 6.3.15: I/O port
characteristics.
All I2C I/Os embed an analog filter, refer to the Table 73: I2C analog filter characteristics.
Table 71. IWDG min/max timeout period at 40 kHz (LSI) (1)
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 7 6.4 26214.4
Table 72. WWDG min-max timeout value @72 MHz (PCLK)(1)
1. Guaranteed by design, not tested in production.
Prescaler WDGTB Min timeout value Max timeout value
1 0 0.05687 3.6409
2 1 0.1137 7.2817
4 2 0.2275 14.564
8 3 0.4551 29.127
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STM32F302xD STM32F302xE Electrical characteristics
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SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 74 for SPI or in Table 75 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 19.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 73. I2C analog filter characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Min Max Unit
tAF
Pulse width of spikes that are
suppressed by the analog filter 50 260 ns
Table 74. SPI characteristics(1)
Symbol Parameter Conditions Min Typ. Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode 2.7 V<VDD<3.6 V,
SPI1/4 --24
MHz
Master mode 2 V<VDD<3.6 V,
SPI1/2/3/4 18
Slave mode 2 V<VDD<3.6 V,
SPI1/4 24
Slave mode 2 V<VDD<3.6 V,
SPI1/2/3/4 18
Slave mode transmitter/full duplex
2 V<VDD<3.6 V, SPI1/2/3/4 16.5(2)
Slave mode transmitter/full duplex
2.7 V<VDD<3.6 V, SPI1/4 22.5(2)) -
Duty(SCK)
Duty cycle of SPI clock
frequency Slave mode 30 50 70 %
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tsu(MI) Data input setup time Master mode 3 - -
tsu(SI) Slave mode 3 - -
th(MI) Data input hold time Master mode 6.5 - -
th(SI) Slave mode 4.5 - -
ta(SO) Data output access time Slave mode 10 - 30
tdis(SO) Data output disable time Slave mode 8 - 7
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Figure 42. SPI timing diagram - slave mode and CPHA = 0
tv(SO) Data output valid time
Slave mode 2.7 V<VDD<3.6 V - 15 22
Slave mode 2 V<VDD<3.6 V - 15 30
tv(MO) Master mode - 2 4.5
th(SO) Data output hold time Slave mode 9 - -
th(MO) Master mode 0 - -
1. Data based on characterization results, not tested in production.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Table 74. SPI characteristics(1) (continued)
Symbol Parameter Conditions Min Typ. Max Unit
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STM32F302xD STM32F302xE Electrical characteristics
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Figure 43. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 44. SPI timing diagram - master mode(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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124/168 DocID026900 Rev 4
Note: Refer to the I2S section in RM0365 Reference Manual for more details about the sampling
frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source
clock precision might slightly change the values DCK depends mainly on ODD bit value.
Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.
Table 75. I2S characteristics(1)
1. Data based on characterization results, not tested in production.
Symbol Parameter Conditions Min Max Unit
fMCK I2S Main clock output - 256 x 8K 256xFs (2)
2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)
MHz
fCK I2S clock frequency Master data: 32 bits - 64xFs MHz
Slave data: 32 bits - 64xFs -
DCK
I2S clock frequency duty
cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode - 20
ns
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 0 -
th(WS) WS hold time Slave mode 4 -
tsu(SD_MR) Data input setup time Master receiver 1 -
tsu(SD_SR) Slave receiver 1 -
th(SD_MR) Data input hold time Master receiver 8 -
th(SD_SR) Slave receiver 2.5 -
tv(SD_ST)
Data output valid time
Slave transmitter
(after enable edge) -50
tv(SD_MT)
Master transmitter
(after enable edge) -22
th(SD_ST)
Data output hold time
Slave transmitter (after
enable edge) 8-
th(SD_MT)
Master transmitter
(after enable edge) 1-
DocID026900 Rev 4 125/168
STM32F302xD STM32F302xE Electrical characteristics
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Figure 45. I2S slave timing diagram (Philips protocol)(1)
1. Measurement points are done at 0.5VDD and with external CL=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 46. I2S master timing diagram (Philips protocol)(1)
1. Measurement points are done at 0.5VDD and with external CL=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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USB characteristics
Figure 47. USB timings: definition of data signal rise and fall time
Table 76. USB startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design, not tested in production.
USB transceiver startup time 1 µs
Table 77. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
-3.0
(3)
3. The STM32F302xD/E USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3.6 V
VDI(4)
4. Guaranteed by design, not tested in production.
Differential input sensitivity I(USB_DP, USB_DM) 0.2 -
VVCM(4) Differential common mode range Includes VDI range 0.8 2.5
VSE(4) Single ended receiver threshold - 1.3 2.0
Output levels
VOL Static output level low RL of 1.5 kΩ to 3.6 V(5)
5. RL is the load connected on the USB drivers.
-0.3
V
VOH Static output level high RL of 15 kΩ to VSS(5) 2.8 3.6
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Symbol Parameter Conditions Min Typ Max Unit
Driver characteristics
trRise time(2) CL = 50 pF 4 - 20 ns
tfFall time(2) CL = 50 pF 4 - 20 ns
DocID026900 Rev 4 127/168
STM32F302xD STM32F302xE Electrical characteristics
146
CAN (controller area network) interface
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.19 ADC characteristics
Unless otherwise specified, the parameters given in Table 79 to Table 82 are guaranteed by
design, with conditions summarized in Table 19.
trfm Rise/ fall time matching tr/tf90 - 110 %
VCRS Output signal crossover voltage - 1.3 - 2.0 V
Output driver
Impedance(3) ZDRV driving high and low 28 40 44 Ω
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB Specification - Chapter 7
(version 2.0).
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is
already included in the embedded driver.
Table 78. USB: full-speed electrical characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 79. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply voltage for
ADC -2.0-3.6V
IDDA
Current on VDDA pin
(see Figure 48)
Single-ended mode,
5 MSPS - 907 1033
µA
Single-ended mode,
1 MSPS - 194 285.5
Single-ended mode,
200 KSPS -51.570
Differential mode,
5 MSPS - 887.5 1009
Differential mode,
1 MSPS - 212 285
Differential mode,
200 KSPS -5169.5
Electrical characteristics STM32F302xD STM32F302xE
128/168 DocID026900 Rev 4
IREF
Current on VREF+ pin
(see Figure 49)
Single-ended mode,
5 MSPS - 104 139
µA
Single-ended mode,
1 MSPS -20.437
Single-ended mode,
200 KSPS - 3.3 11.3
Differential mode,
5 MSPS - 174 235
Differential mode,
1 MSPS -34.652.6
Differential mode,
200 KSPS -613.6
VREF+ Positive reference voltage - 2 - VDDA V
fADC ADC clock frequency - 0.14 - 72 MHz
fS(1) Sampling rate
Resolution = 12 bits,
Fast Channel 0.01 - 5.14
MSPS
Resolution = 10 bits,
Fast Channel 0.012 - 6
Resolution = 8 bits,
Fast Channel 0.014 - 7.2
Resolution = 6 bits,
Fast Channel 0.0175 - 9
fTRIG(1) External trigger frequency
fADC = 72 MHz
Resolution = 12 bits --5.14MHz
Resolution = 12 bits - - 14 1/fADC
VAIN Conversion voltage range(2) -0-V
REF+ V
RAIN(1) External input impedance - - - 100 kΩ
CADC(1) Internal sample and hold
capacitor --5-pF
tSTAB(1) Power-up time - 0 0 1 µs
tCAL(1) Calibration time fADC = 72 MHz 1.56 µs
- 112 1/fADC
tlatr(1)
Trigger conversion latency
Regular and injected
channels without conversion
abort
CKMODE = 00 1.5 2 2.5 1/fADC
CKMODE = 01 - - 2 1/fADC
CKMODE = 10 - - 2.25 1/fADC
CKMODE = 11 - - 2.125 1/fADC
tlatrinj(1)
Trigger conversion latency
Injected channels aborting a
regular conversion
CKMODE = 00 2.5 3 3.5 1/fADC
CKMODE = 01 - - 3 1/fADC
CKMODE = 10 - - 3.25 1/fADC
CKMODE = 11 - - 3.125 1/fADC
Table 79. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID026900 Rev 4 129/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 48. ADC typical current consumption on VDDA pin
tS(1) Sampling time fADC = 72 MHz 0.021 - 8.35 µs
- 1.5 - 601.5 1/fADC
TADCVREG
_STUP(1)
ADC Voltage Regulator
Start-up time ---10µs
tCONV(1) Total conversion time
(including sampling time)
fADC = 72 MHz
Resolution = 12 bits 0.19 - 8.52 µs
Resolution = 12 bits
14 to 614 (tS for sampling + 12.5
for
successive approximation)
1/fADC
CMIR Common Mode Input signal
range ADC differential mode
(VSSA +
VREF+)/2
– 0.18
(VSSA +
VREF+)/2
(VSSA +
VREF+)/2
+ 0.18
V
1. Data guaranteed by design, not tested in Production.
2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinout and pin description for further details.
Table 79. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Electrical characteristics STM32F302xD STM32F302xE
130/168 DocID026900 Rev 4
Figure 49. ADC typical current consumption on VREF+ pin
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Table 80. Maximum ADC RAIN (1)
Resolution
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
RAIN max (kΩ)
Fast channels(2) Slow
channels
Other
channels(3)
12 bits
1.5 20.83 0.018 NA NA
2.5 34.72 0.150 NA 0.022
4.5 62.50 0.470 0.220 0.180
7.5 104.17 0.820 0.560 0.470
19.5 270.83 2.70 1.80 1.50
61.5 854.17 8.20 6.80 4.70
181.5 2520.83 22.0 18.0 15.0
601.5 8354.17 82.0 68.0 47.0
10 bits
1.5 20.83 0.082 NA NA
2.5 34.72 0.270 0.082 0.100
4.5 62.50 0.560 0.390 0.330
7.5 104.17 1.20 0.82 0.68
19.5 270.83 3.30 2.70 2.20
61.5 854.17 10.0 8.2 6.8
181.5 2520.83 33.0 27.0 22.0
601.5 8354.17 100.0 82.0 68.0
DocID026900 Rev 4 131/168
STM32F302xD STM32F302xE Electrical characteristics
146
8 bits
1.5 20.83 0.150 NA 0.039
2.5 34.72 0.390 0.180 0.180
4.5 62.50 0.820 0.560 0.470
7.5 104.17 1.50 1.20 1.00
19.5 270.83 3.90 3.30 2.70
61.5 854.17 12.00 12.00 8.20
181.5 2520.83 39.00 33.00 27.00
601.5 8354.17 100.00 100.00 82.00
6 bits
1.5 20.83 0.270 0.100 0.150
2.5 34.72 0.560 0.390 0.330
4.5 62.50 1.200 0.820 0.820
7.5 104.17 2.20 1.80 1.50
19.5 270.83 5.60 4.70 3.90
61.5 854.17 18.0 15.0 12.0
181.5 2520.83 56.0 47.0 39.0
601.5 8354.17 100.00 100.0 100.0
1. Data based on characterization results, not tested in production.
2. All fast channels, expect channels on PA2, PA6.
3. Fast channels available on PA2, PA6.
Table 80. Maximum ADC RAIN (1) (continued)
Resolution
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
RAIN max (kΩ)
Fast channels(2) Slow
channels
Other
channels(3)
Electrical characteristics STM32F302xD STM32F302xE
132/168 DocID026900 Rev 4
Table 81. ADC accuracy - limited test conditions, 100-/144-pin packages (1)(2)
Symbol Parameter Conditions Min
(3) Typ Max
(3) Unit
ET
To ta l
unadjusted
error
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
100-pin/144-pin package
Single ended Fast channel 5.1 Ms - ±3.5 ±4.5
LSB
Slow channel 4.8 Ms - ±4±4.5
Differential Fast channel 5.1 Ms - ±3±3
Slow channel 4.8 Ms - ±3±3
EO Offset error
Single ended Fast channel 5.1 Ms - ±1±1.5
Slow channel 4.8 Ms - ±1±2.5
Differential Fast channel 5.1 Ms - ±1±1.5
Slow channel 4.8 Ms - ±1±1.5
EG Gain error
Single ended Fast channel 5.1 Ms - ±3±4
Slow channel 4.8 Ms - ±3.5 ±4
Differential Fast channel 5.1 Ms - ±1.5 ±2.5
Slow channel 4.8 Ms - ±2±2.5
ED
Differential
linearity
error
Single ended Fast channel 5.1 Ms - ±1±1.5
Slow channel 4.8 Ms - ±1±1.5
Differential Fast channel 5.1 Ms - ±1±1
Slow channel 4.8 Ms - ±1±1
EL
Integral
linearity
error
Single ended Fast channel 5.1 Ms - ±1.5 ±2
Slow channel 4.8 Ms - ±1.5 ±3
Differential Fast channel 5.1 Ms - ±1±1.5
Slow channel 4.8 Ms - ±1±1.5
ENOB(4)
Effective
number of
bits
Single ended Fast channel 5.1 Ms 10.7 10.8 -
bits
Slow channel 4.8 Ms 10.7 10.8 -
Differential Fast channel 5.1 Ms 11.2 11.3 -
Slow channel 4.8 Ms 11.1 11.3 -
SINAD(4)
Signal-to-
noise and
distortion
ratio
Single ended Fast channel 5.1 Ms 66 67 -
dB
Slow channel 4.8 Ms 66 67 -
Differential Fast channel 5.1 Ms 69 70 -
Slow channel 4.8 Ms 69 70 -
DocID026900 Rev 4 133/168
STM32F302xD STM32F302xE Electrical characteristics
146
SNR(4) Signal-to-
noise ratio ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
100-pin/144-pin package
Single ended Fast channel 5.1 Ms 66 67 -
dB
Slow channel 4.8 Ms 66 67 -
Differential Fast channel 5.1 Ms 69 70 -
Slow channel 4.8 Ms 69 70 -
THD(4)
To ta l
harmonic
distortion
Single ended Fast channel 5.1 Ms - -76 -76
Slow channel 4.8 Ms - -76 -76
Differential Fast channel 5.1 Ms - -80 -80
Slow channel 4.8 Ms - -80 -80
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 81. ADC accuracy - limited test conditions, 100-/144-pin packages (1)(2) (continued)
Symbol Parameter Conditions Min
(3) Typ Max
(3) Unit
Table 82. ADC accuracy, 100-pin/144-pin packages(1)(2)(3)
Symbol Parameter Conditions Min (4) Max(4) Unit
ET
Total
unadjusted
error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA, VREF+ ≤ 3.6 V
100-pin/144-pin package
Single
Ended
Fast channel 5.1 Ms - ±6.5
LSB
Slow channel 4.8 Ms - ±6.5
Differential Fast channel 5.1 Ms - ±4
Slow channel 4.8 Ms - ±4
EO Offset error
Single
Ended
Fast channel 5.1 Ms - ±3
Slow channel 4.8 Ms - ±3
Differential Fast channel 5.1 Ms - ±2
Slow channel 4.8 Ms - ±2
EG Gain error
Single
Ended
Fast channel 5.1 Ms - ±6
Slow channel 4.8 Ms - ±6
Differential Fast channel 5.1 Ms - ±3
Slow channel 4.8 Ms - ±3
ED
Differential
linearity
error
Single
Ended
Fast channel 5.1 Ms - ±1.5
Slow channel 4.8 Ms - ±1.5
Differential Fast channel 5.1 Ms - ±1.5
Slow channel 4.8 Ms - ±1.5
Electrical characteristics STM32F302xD STM32F302xE
134/168 DocID026900 Rev 4
EL
Integral
linearity
error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps,
2.0 V≤ VDDA, VREF+ ≤ 3.6 V
100-pin/144-pin package
Single
Ended
Fast channel 5.1 Ms - ±2
LSB
Slow channel 4.8 Ms - ±3
Differential Fast channel 5.1 Ms - ±2
Slow channel 4.8 Ms - ±2
ENOB
(5)
Effective
number of
bits
Single
Ended
Fast channel 5.1 Ms 10.4 -
bits
Slow channel 4.8 Ms 10.2 -
Differential Fast channel 5.1 Ms 10.8 -
Slow channel 4.8 Ms 10.8 -
SINAD
(5)
Signal-to-
noise and
distortion
ratio
Single
Ended
Fast channel 5.1 Ms 64 -
dB
Slow channel 4.8 Ms 63 -
Differential Fast channel 5.1 Ms 67 -
Slow channel 4.8 Ms 67 -
SNR(5) Signal-to-
noise ratio
Single
Ended
Fast channel 5.1 Ms 64 -
Slow channel 4.8 Ms 64 -
Differential Fast channel 5.1 Ms 67 -
Slow channel 4.8 Ms 67 -
THD(5)
Total
harmonic
distortion
Single
Ended
Fast channel 5.1 Ms - 74
Slow channel 4.8 Ms - -74
Differential Fast channel 5.1 Ms - -78
Slow channel 4.8 Ms - -76
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 82. ADC accuracy, 100-pin/144-pin packages(1)(2)(3) (continued)
Symbol Parameter Conditions Min (4) Max(4) Unit
DocID026900 Rev 4 135/168
STM32F302xD STM32F302xE Electrical characteristics
146
Table 83. ADC accuracy - limited test conditions, 64-pin packages(1)(2)
Symbol Parameter Conditions Min
(3) Typ Max
(3) Unit
ET
To ta l
unadjusted
error
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
VDDA = 3.3 V
25°C
64-pin package
Single ended Fast channel 5.1 Ms - ±4 ±4.5
LSB
Slow channel 4.8 Ms - ±5.5 ±6
Differential Fast channel 5.1 Ms - ±3.5 ±4
Slow channel 4.8 Ms - ±3.5 ±4
EO Offset error
Single ended Fast channel 5.1 Ms - ±2 ±2
Slow channel 4.8 Ms - ±1.5 ±2
Differential Fast channel 5.1 Ms - ±1.5 ±2
Slow channel 4.8 Ms - ±1.5 ±2
EG Gain error
Single ended Fast channel 5.1 Ms - ±3 ±4
Slow channel 4.8 Ms - ±5 ±5.5
Differential Fast channel 5.1 Ms - ±3 ±3
Slow channel 4.8 Ms - ±3 ±3.5
ED
Differential
linearity
error
Single ended Fast channel 5.1 Ms - ±1 ±1
Slow channel 4.8 Ms - ±1 ±1
Differential Fast channel 5.1 Ms - ±1 ±1
Slow channel 4.8 Ms - ±1 ±1
EL
Integral
linearity
error
Single ended Fast channel 5.1 Ms - ±1.5 ±2
Slow channel 4.8 Ms - ±2 ±3
Differential Fast channel 5.1 Ms - ±1.5 ±1.5
Slow channel 4.8 Ms - ±1.5 ±2
ENOB
(4)
Effective
number of
bits
Single ended Fast channel 5.1 Ms 10.8 10.8 -
bit
Slow channel 4.8 Ms 10.8 10.8 -
Differential Fast channel 5.1 Ms 11.2 11.3 -
Slow channel 4.8 Ms 11.2 11.3 -
SINAD
(4)
Signal-to-
noise and
distortion
ratio
Single ended Fast channel 5.1 Ms 66 67 -
dB
Slow channel 4.8 Ms 66 67 -
Differential Fast channel 5.1 Ms 69 70 -
Slow channel 4.8 Ms 69 70 -
Electrical characteristics STM32F302xD STM32F302xE
136/168 DocID026900 Rev 4
SNR(4) Signal-to-
noise ratio ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
VDDA = 3.3 V
25°C
64-pin package
Single ended Fast channel 5.1 Ms 66 67 -
dB
Slow channel 4.8 Ms 66 67 -
Differential Fast channel 5.1 Ms 69 70 -
Slow channel 4.8 Ms 69 70 -
THD(4)
To ta l
harmonic
distortion
Single ended Fast channel 5.1 Ms - -80 -80
Slow channel 4.8 Ms - -78 -77
Differential Fast channel 5.1 Ms - -83 -82
Slow channel 4.8 Ms - -81 -80
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 83. ADC accuracy - limited test conditions, 64-pin packages(1)(2) (continued)
Symbol Parameter Conditions Min
(3) Typ Max
(3) Unit
Table 84. ADC accuracy, 64-pin packages(1)(2)(3)
Symbol Parameter Conditions Min(4) Max
(4) Unit
ET
Total
unadjusted
error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA ≤ 3.6 V
64-pin package
Single ended Fast channel 5.1 Ms - ±6.5
LSB
Slow channel 4.8 Ms - ±6.5
Differential Fast channel 5.1 Ms - ±4
Slow channel 4.8 Ms - ±4.5
EO Offset error
Single ended Fast channel 5.1 Ms - ±3
Slow channel 4.8 Ms - ±3
Differential Fast channel 5.1 Ms - ±2.5
Slow channel 4.8 Ms - ±2.5
EG Gain error
Single ended Fast channel 5.1 Ms - ±6
Slow channel 4.8 Ms - ±6
Differential Fast channel 5.1 Ms - ±3.5
Slow channel 4.8 Ms - ±4
ED
Differential
linearity
error
Single ended Fast channel 5.1 Ms - ±1.5
Slow channel 4.8 Ms - ±1.5
Differential Fast channel 5.1 Ms - ±1.5
Slow channel 4.8 Ms - ±1.5
DocID026900 Rev 4 137/168
STM32F302xD STM32F302xE Electrical characteristics
146
EL
Integral
linearity
error
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
2.0 V ≤ VDDA ≤ 3.6 V
64-pin package
Single ended Fast channel 5.1 Ms - ±3
LSB
Slow channel 4.8 Ms - ±3.5
Differential Fast channel 5.1 Ms - ±2
Slow channel 4.8 Ms - ±2.5
ENOB
(5)
Effective
number of
bits
Single ended Fast channel 5.1 Ms 10.4 -
bits
Slow channel 4.8 Ms 10.4 -
Differential Fast channel 5.1 Ms 10.8 -
Slow channel 4.8 Ms 10.8 -
SINAD
(5)
Signal-to-
noise and
distortion
ratio
Single ended Fast channel 5.1 Ms 64 -
dB
Slow channel 4.8 Ms 63 -
Differential Fast channel 5.1 Ms 67 -
Slow channel 4.8 Ms 67 -
SNR(5) Signal-to-
noise ratio
Single ended Fast channel 5.1 Ms 64 -
dB
Slow channel 4.8 Ms 64 -
Differential Fast channel 5.1 Ms 67 -
Slow channel 4.8 Ms 67 -
THD(5)
Total
harmonic
distortion
Single ended Fast channel 5.1 Ms - -75
Slow channel 4.8 Ms - -75
Differential Fast channel 5.1 Ms - -79
Slow channel 4.8 Ms - -78
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 84. ADC accuracy, 64-pin packages(1)(2)(3) (continued)
Symbol Parameter Conditions Min(4) Max
(4) Unit
Electrical characteristics STM32F302xD STM32F302xE
138/168 DocID026900 Rev 4
Figure 50. ADC accuracy characteristics
Table 85. ADC accuracy at 1MSPS(1)(2)
Symbol Parameter Test conditions Typ Max(3) Unit
ET Total unadjusted error
ADC Freq ≤ 72 MHz
Sampling Freq ≤ 1MSPS
2.4 V ≤ VDDA = VREF+ ≤ 3.6 V
Single-ended mode
Fast channel ±2.5 ±5
LSB
Slow channel ±3.5 ±5
EO Offset error Fast channel ±1 ±2.5
Slow channel ±1.5 ±2.5
EG Gain error Fast channel ±2 ±3
Slow channel ±3 ±4
ED Differential linearity error Fast channel ±0.7 ±2
Slow channel ±0.7 ±2
EL Integral linearity error Fast channel ±1 ±3
Slow channel ±1.2 ±3
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current
within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.15: I/O port characteristics does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
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DocID026900 Rev 4 139/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 51. Typical connection diagram using the ADC
1. Refer to Table 79 for the values of RAIN.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 12. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
6.3.20 DAC electrical specifications
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Table 86. DAC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 2.4 - 3.6 V
RLOAD(1) Resistive load DAC output buffer ON 5 - - kΩ
RLResistive load
Dac output buffer ON:
connected to VSSA
5- - kΩ
Dac output buffer ON:
connected to VDDA
25 - - kΩ
RO(1) Output impedance DAC output buffer OFF - - 15 kΩ
CLOAD(1) Capacitive load DAC output buffer ON - - 50 pF
VDAC_OUT (1) Voltage on DAC_OUT
output
Corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VDDA = 3.6 V
and (0x155) and (0xEAB) at
VDDA = 2.4 V DAC output
buffer ON.
0.2 - VDDA – 0.2 V
DAC output buffer OFF - 0.5 VDDA - 1LSB mV
Electrical characteristics STM32F302xD STM32F302xE
140/168 DocID026900 Rev 4
IREF
DAC DC current
consumption in quiescent
mode (Standby mode)
With no load, worst code
(0xF1C) on the input - - 220 µA
IDDA(3)
DAC DC current
consumption in quiescent
mode (Standby mode)(2)
With no load, middle code
(0x800) on the input. - - 380 µA
With no load, worst code
(0xF1C) on the input. - - 480 µA
DNL(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
Given for a 10-bit input code - - ±0.5 LSB
Given for a 12-bit input code - - ±2 LSB
INL(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 4095)
Given for a 10-bit input code - - ±1 LSB
Given for a 12-bit input code - - ±4 LSB
Offset(3)
Offset error (difference
between measured value at
Code (0x800) and the ideal
value = VDDA/2)
---±10mV
Given for a 10-bit input code
at VDDA = 3.6 V -- ±3 LSB
Given for a 12-bit input code
at VDDA = 3.6 V -- ±12LSB
Gain error(3) Gain error Given for a 12-bit input code - - ±0.5 %
tSETTLING(3)
Settling time (full scale: for a
12-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ-3 4 µs
tSTAB Power-up time - 1
conver
sion
cycle
Update rate(3)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ-- 1 MS/s
tWAKEUP(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ-6.5 10 µs
PSRR+ (1)
Power supply rejection ratio
(to VDDA) (static DC
measurement
CLOAD = 50 pF,
No RLOAD ≥ 5 kΩ, - –67 –40 dB
Iskink(1) Output sink current
DAC buffer ON
Output level higher
than 0.2 V
100 - - µA
1. Guaranteed by design, not tested in production.
Table 86. DAC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID026900 Rev 4 141/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 52. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.21 Comparator characteristics
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
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Table 87. Comparator characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDA Analog supply voltage - 2 - 3.6
VVIN
Comparator input voltage
range -0-V
DDA
VBG Scaler input voltage - - VREFINIT -
VSC Scaler offset voltage - - ±5 ±10 mV
tS_SC
Scaler startup time from
power down ---0.2ms
tSTART Comparator startup time VDDA ≥ 2.7 V - - 4 µs
VDDA < 2.7 V - - 10
tD
Propagation delay for
200 mV step with 100 mV
overdrive
VDDA ≥ 2.7 V - 25 28
ns
VDDA < 2.7 V - 28 30
Propagation delay for full
range step with 100 mV
overdrive
VDDA ≥ 2.7 V - 32 35
VDDA < 2.7 V - 35 40
VOFFSET Comparator offset error VDDA ≥ 2.7 V - ±5±10 mV
VDDA < 2.7 V - - ±25
Electrical characteristics STM32F302xD STM32F302xE
142/168 DocID026900 Rev 4
TVOFFSET Total offset variation Full temperature range - - 3 mV
IDDA
COMP current
consumption - - 400 600 µA
1. Guaranteed by design, not tested in production.
Table 87. Comparator characteristics(1) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
DocID026900 Rev 4 143/168
STM32F302xD STM32F302xE Electrical characteristics
146
6.3.22 Operational amplifier characteristics
Table 88. Operational amplifier characteristics(1)
Symbol Parameter Condition Min Typ Max Unit
VDDA Analog supply voltage - 2.4 - 3.6 V
CMIR Common mode input range - 0 - VDDA V
VIOFFSET
Input offset
voltage
Maximum
calibration
range
25°C, No Load
on output. --4
mV
All
voltage/Temp. --6
After offset
calibration
25°C, No Load
on output. --1.6
All
voltage/Temp. --3
ΔVIOFFSET Input offset voltage drift - - 5 - µV/°C
ILOAD Drive current - - - 500 µA
IDDA OPAMP consumption No load,
quiescent mode - 690 1450 µA
TS_OPAMP_VOUT ADC sampling time when reading
the OPAMP output. -400--ns
CMRR Common mode rejection ratio - - 90 - dB
PSRR Power supply rejection ratio DC 73 117 - dB
GBW Bandwidth - - 8.2 - MHz
SR Slew rate - - 4.7 - V/µs
RLOAD Resistive load - 4 - - kΩ
CLOAD Capacitive load - - - 50 pF
VOHSAT High saturation voltage(2)
Rload = min,
Input at VDDA.VDDA-100 --
mV
Rload = 20K,
Input at VDDA.VDDA-20 --
VOLSAT Low saturation voltage(2)
Rload = min,
input at 0V --100
Rload = 20K,
input at 0V. --20
ϕm Phase margin - - 62 - °
tOFFTRIM
Offset trim time: during calibration,
minimum time needed between
two steps to have 1 mV accuracy
---2ms
tWAKEUP Wake up time from OFF state.
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ,
Follower
configuration
-2.85µs
Electrical characteristics STM32F302xD STM32F302xE
144/168 DocID026900 Rev 4
PGA gain Non inverting gain value -
-2--
-4--
-8--
-16--
Rnetwork
R2/R1 internal resistance values in
PGA mode (3)
Gain=2 - 5.4/5.4 -
kΩ
Gain=4 - 16.2/5.4 -
Gain=8 - 37.8/5.4 -
Gain=16 - 40.5/2.7 -
PGA gain error PGA gain error - -1% - 1% -
Ibias OPAMP input bias current - - - ±0.2(4) µA
PGA BW PGA bandwidth for different non
inverting gain
PGA Gain = 2,
Cload = 50pF,
Rload = 4 KΩ
-4-
MHz
PGA Gain = 4,
Cload = 50pF,
Rload = 4 KΩ
-2-
PGA Gain = 8,
Cload = 50pF,
Rload = 4 KΩ
-1-
PGA Gain = 16,
Cload = 50pF,
Rload = 4 KΩ
-0.5-
en Voltage noise density
@ 1KHz, Output
loaded with
4 KΩ
- 109 -
@ 10KHz,
Output loaded
with 4 KΩ
-43-
1. Guaranteed by design, not tested in production.
2. The saturation voltage can be also limited by the Iload (drive current).
3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
4. Mostly TTa I/O leakage, when used in analog mode.
Table 88. Operational amplifier characteristics(1) (continued)
Symbol Parameter Condition Min Typ Max Unit
nV
Hz
-----------
DocID026900 Rev 4 145/168
STM32F302xD STM32F302xE Electrical characteristics
146
Figure 53. OPAMP voltage noise versus frequency
6.3.23 Temperature sensor characteristics
Table 89. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by design, not tested in production.
VSENSE linearity with temperature - ±1±2°C
Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C
V25 Voltage at 25 °C 1.34 1.43 1.52 V
tSTART(1) Startup time 4 - 10 µs
TS_temp(1)(2)
2. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature 2.2 - - µs
Table 90. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
Electrical characteristics STM32F302xD STM32F302xE
146/168 DocID026900 Rev 4
6.3.24 VBAT monitoring characteristics
Table 91. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -50-KΩ
QRatio on VBAT measurement - 2 - -
Er(1)
1. Guaranteed by design, not tested in production.
Error on Q -1 - +1 %
TS_vbat(1)(2)
2. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the VBAT
1mV accuracy 2.2 - - µs
DocID026900 Rev 4 147/168
STM32F302xD STM32F302xE Package information
166
7 Package information
7.1 Package mechanical data
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.2 LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 54. LQFP144 package outline
1. Drawing is not to scale.
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Table 92. LQFP144 mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
DocID026900 Rev 4 149/168
STM32F302xD STM32F302xE Package information
166
Figure 55. Recommended footprint for the LQFP144 package
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
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Package information STM32F302xD STM32F302xE
150/168 DocID026900 Rev 4
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 56. LQFP144 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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STM32F302xD STM32F302xE Package information
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7.3 UFBGA100 package information
UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 57. UFBGA100 package outline
1. Drawing is not to scale.
Table 93. UFBGA100 package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.450 5.500 5.550 0.2146 0.2165 0.2185
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.450 5.500 5.550 0.2146 0.2165 0.2185
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
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Figure 58. Recommended footprint for the UFBGA100 package
Note: Non-solder mask defined (NSMD) pads are recommended.
Note: 4 to 6 mils solder paste screen printing process.
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 94. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch 0.5
Dpad 0.27 mm
Dsm 0.35 mm typ. (depends on the soldermask
registration tolerance)
Solder paste 0.27 mm aperture diameter.
Table 93. UFBGA100 package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
069
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DocID026900 Rev 4 153/168
STM32F302xD STM32F302xE Package information
166
Device marking for UFBGA100
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 59. UFBGA100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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154/168 DocID026900 Rev 4
7.4 LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 60. LQFP100 package outline
1. Drawing is not to scale.
Table 95. LQPF100 package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
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STM32F302xD STM32F302xE Package information
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Figure 61. Recommended footprint for the LQFP100 package
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 95. LQPF100 package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
AIC
Package information STM32F302xD STM32F302xE
156/168 DocID026900 Rev 4
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 62. LQFP100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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STM32F302xD STM32F302xE Package information
166
7.5 WLCSP100 package information
WLCSP100 is a 100-ball, 4.775 x 5.041 mm, 0.4 mm pitch wafer level chip scale package.
Figure 63.WLCSP100 package outline
1. Drawing is not to scale.
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158/168 DocID026900 Rev 4
Figure 64. Recommended footprint for the WLCSP100 package
Table 96. WLCSP100 package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Typ Min Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.38 - - 0.0150 -
A3(2)
2. Back side coating.
- 0.025 - - 0.0010 -
Ø b(3)
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
0.22 0.25 0.28 - 0.0098 0.0110
D 4.74 4.775 4.81 - 0.1880 0.1894
E 5.006 5.041 5.076 - 0.1985 0.1998
e - 0.4 - - 0.0157 -
e1 - 3.6 - - 0.1417 -
e2 - 3.6 - - 0.1417 -
F - 0.5875 - - 0.0231 -
G - 0.7205 - - 0.0284 -
N - 100 - - 3.9370 -
aaa - 0.1 - - 0.0039 -
bbb - 0.1 - - 0.0039 -
ccc - 0.1 - - 0.0039 -
ddd - 0.05 - - 0.0020 -
eee - 0.05 - - 0.0020 -
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DocID026900 Rev 4 159/168
STM32F302xD STM32F302xE Package information
166
Device marking for WLCSP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 65. WLCSP100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
Table 97. WLCSP100 recommended PCB design rules (0.4 mm pitch)
Dimension Recommended values
Pitch 0.4 mm
Dpad 0.225 mm
Dsm 0.290 mm
Stencil thickness 0.1 mm
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7.6 LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 66. LQFP64 package outline
1. Drawing is not to scale.
Table 98. LQFP64 package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
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STM32F302xD STM32F302xE Package information
166
Figure 67. Recommended footprint for the LQFP64 package
1. Dimensions are expressed in millimeters.
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
θ0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 98. LQFP64 package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
AIC
Package information STM32F302xD STM32F302xE
162/168 DocID026900 Rev 4
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 68. LQFP64 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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STM32F302xD STM32F302xE Package information
166
7.7 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 19: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x Θ
JA)
Where:
•TA max is the maximum temperature in °C,
•Θ
JA is the package junction-to- thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
7.7.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.7.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use the STM32F302xD/E at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range is best suited to the application.
Table 99. Package thermal characteristics
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-
LQFP144 - 20 × 20 mm 33
°C/W
Thermal resistance junction-
UFBGA100 - 7 × 7 mm 59
Thermal resistance junction-
LQFP100 - 14 × 14 mm 42
Thermal resistance junction-
WLCSP100 - 0.4 mm pitch 44
Thermal resistance junction-
LQFP64 - 10 × 10 mm / 0.5 mm pitch 46
Package information STM32F302xD STM32F302xE
164/168 DocID026900 Rev 4
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 99 TJmax is calculated as follows:
– For LQFP100, 42 °C/W
TJmax = 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (42°C/W × 447 mW) = 105-18.774 = 86.226 °C
Suffix 7: TAmax = TJmax - (42°C/W × 447 mW) = 125-18.774 = 106.226 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high temperature with
a low dissipation, as long as junction temperature TJ remains within the specified range.
Assuming the following application conditions:
Maximum temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 99 TJmax is calculated as follows:
– For LQFP100, 42 °C/W
TJmax = 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation to be able to use suffix 6
parts.
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STM32F302xD STM32F302xE Package information
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Refer to Figure 69 to select the required temperature range (suffix 6 or 7) according to your
temperature or power requirements.
Figure 69. LQFP100 PD max vs. TA
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6XIIL[
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Part numbering STM32F302xD STM32F302xE
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8 Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact the nearest ST sales office.
Table 100. Ordering information scheme
Example: STM32 F 302 V E T 6 x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
302 = STM32F302xx
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Code size
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
H = UFBGA
T = LQFP
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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STM32F302xD STM32F302xE Revision history
167
9 Revision history
Table 101. Document revision history
Date Revision Changes
20-Jan-2015 1 Initial release.
09-Apr-2015 2
Added USB_DM and USB_DP as additional function to
PA11 and PA12 description, respectively in Table 13:
STM32F302xD/E pin definitions.
Updated:
– Figure 56: LQFP144 marking example (package top
view),
–Figure 59: UFBGA100 marking example (package top
view),
–Figure 62: LQFP100 marking example (package top
view).
08-Mar-2016 3
Renamed:
– FMC as FSMC,
– CCM RAM as CCM SRAM.
Removed:
–table: I2C timings specification and Figure: I2C bus
AC waveforms and measurement circuit in Section :
I2C interface characteristics.
Added:
– Package information for WLCSP100 in Section 7:
Package information.
18-Oct-2016 4
Updated:
Table 2: STM32F302xD/E family device features and
peripheral counts, Section 3.17: Ultra-fast comparators
(COMP), Table 66: DAC characteristics, Table 61: ADC
characteristics, Table 13: STM32F302xD/E pin
definitions, Table 14: STM32F302xD/E alternate
function mapping, Figure 41: Recommended NRST pin
protection
Added:
Table 37: Wakeup time using USART.
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