CD4070BCNX - Fairchild Semiconductor

October 1987

Revised April 2002

CD4070BC Quad 2-Input EXCLUSIVE-OR Gate

CD4070BC

Quad 2-Input EXCLUSIVE-OR Gate

General Description

The CD4070BC employs complementary MOS (CMOS)

transistors to achieve wide power supply operating range,

low power consumption, and high noise margin, the

CD4070BC provide basic functio ns used in the impleme n-

tation of digital integrated circuit systems. The N- and P-

channel enhancement mode transistors provide a symmet-

rical circuit with output swing essentially equal to the supply

voltage. No DC power other than that caused by leakage

current is consumed during static condition. All inputs are

protected from damage due to static discharge by diode

clamps to VDD and VSS.

Features

■Wide supply voltage rang e: 3.0V to 15V

■High noise immunity: 0.45 VDD typ.

■Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS

■Pin compatible to CD4030A

Equivalent to MM74C86 and MC14070B

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the orderin g c ode.

Connection Diagram

Top View

Truth Table

Order Number Package Number Package Description

CD4070BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4070BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Inputs Outputs

ABY

LLL

LHH

HLH

HHL

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CD4070BC

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the devic es should be opera ted at these limits. The table of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provides

conditions for act ual devi c e operation.

Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

Note 3: “Absolute Maximum Ratings” are th ose value s beyo nd which t he safet y of the d evice ca nnot be guarant eed. The y are not meant to imply that the

devices should be opera t ed at these lim its. T he t able of “Recommended Operating Conditions” an d “Electrical Characteristics” provides conditions for actual

devi c e operation .

DC Supply Voltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5toV

DD +0.5 VDC

Storage Temperature Range (T S)−65°C to +150°C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Out lin e 500 mW

Lead Temperature (TL)

(Solder ing, 10 seco nds) 260°C

DC Supply Voltage (VDD) 3V to 15 VDC

Input Voltage (VIN)0 to V

DD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V, 0.25 0.25 7.5

µA

Current VIN = VDD or VSS

VDD = 10V, 0.5 0.5 15

VIN = VDD or VSS

VDD = 15V, 1.0 1.0 30

VIN = VDD or VSS

VOL LOW Level |IO| < 1 µA

Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level |IO| < 1 µA

Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level |IO| < 1 µA

Input Voltage VDD = 5V, VO = 4.5V or 0.5V 1.5 1.5 1.5 VVDD = 10V, VO = 9V or 1.0V 3.0 3.0 3.0

VDD = 15V, VO = 13.5V or 1.5V 4.0 4.0 4.0

VIH HIGH Level |IO| < 1 µA

Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VVDD = 10V, VO = 1V or 9.0V 7.0 7.0 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIG H Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15 V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4070BC

AC Electrical Characteristics (Note 4)

TA = 25°C, CL = 50 pF, RL = 200k, tr and tf ≤ 20 ns, unless otherwise specified

Note 4: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics Application

Note—AN-90.

Typical Performance Characteristics

Propagation Delay Time vs. Load Capacitance

AC Test Circuit and Switching Time Waveforms

Note: Delays measured with input tr, tf = 20 ns.

tr = tf = 20 ns

Symbol Parameter Conditions Min Typ Max Units

tPHL or Propagation Delay Time VDD = 5V 110 185 nstPLH from Input to Output VDD = 10V 50 90

VDD = 15V 40 75

tTHL or Transition Time VDD = 5V 100 200 nstTLH VDD = 10V 50 100

VDD = 15V 40 80

CIN Average Input Capacitance Any Input 5 7.5 pF

CPD Power Dissipation Capacitance Any Input (Note 5) 20 pF

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CD4070BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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CD4070BC Quad 2-Input EXCLUSIVE-OR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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