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April 1st, 2010
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R8A66160DD/SP
16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 1 of 7
REJ03F0261-0100
Rev. 1.00
Jan.10. 2008
DESCRIPTION
R8A66160 is a LED array driver having a 16-bit serial input and parallel output shift register function with
direct coupled reset input and output latch function.
This product guarantees the output current of 24mA (Vcc =5V case) which is sufficient for cathode common
LED drive, capable of following 16-bits continuously at the same time. Parallel output is ope n drain output.
In addition, as this product has been designed in complete CMOS, power consumption can be greatly
reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures
the realization of an easy printed circuit. R8A66160 is the succession product of M66310.
FEATURES
● Cathode common LED drive
● VCC 5V or 3.3V single power supply
● High output current: all parallel outputs QA~QP IOH=-24mA (at VCC =5.0V) IOH=-12mA (at VCC =3.3V)
simultaneous lighting available
● Low power dissip ation: 100uW/package (max) (Vcc=5.0V, Ta=25oC, quiescent state)
● High noise margin: Schmitt input circuit provides respon siveness to a long line length
● Equipped with direct-coupled re set
● Open drain output: (except serial data output SQP)
● Wide operating temperature range: Ta=-40oC~+85oC
● Pin layout facilitates printed circuit wi ring. (This layout facilitates cascade connection and LED connection)
APPLICATION
● LED array drive, The various LED display modules
● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipment
BLOCK DIAGRAM
A
SERIAL
DATA
INPUT
CKS
SHIFT
CLOCK
INPUT
CKL
LATCH
CLOCK
INPUT
R
DIRECT
RESET
INPUT
SERIAL
DATA
OUTPUT
PARALLEL DATA OUTPUTS
LOGI C DI A GRAM
SERIAL
DATA
OUTPUT
SQP
OUTPUT FORMAT
PARALLEL
DATA
OUTPUTS
QA〜QP
22
QE
OE
ENABLE
INPUT
5
S
4
S
8 7 6
GND
9
S
S
S
10
SQP
2
QB12
QP
11
QO
13
QN
14
QM
15
QL
16
QK
17
QJ
18
QI
19
QH
20
QG
21
QF
23
QD
24
QC
1
QAVcc
3
DATA signal
OE signal
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
A
SERIAL
DATA
INPUT
CKS
SHIFT
CLOCK
INPUT
CKL
LATCH
CLOCK
INPUT
R
DIRECT
RESET
INPUT
R
DIRECT
RESET
INPUT
SERIAL
DATA
OUTPUT
PARALLEL DATA OUTPUTS
LOGI C DI A GRAM
SERIAL
DATA
OUTPUT
SQP
OUTPUT FORMAT
PARALLEL
DATA
OUTPUTS
QA〜QP
22
QE
OE
ENABLE
INPUT
55
SS
44
SS
88 77 66
GND
9
GND
99
SS
SSS
SSS
10
SQP
2
QB12
QP
11
QO
13
QN
14
QM
15
QL
16
QK
17
QJ
18
QI
19
QH
20
QG
21
QF
23
QD
24
QC
1
QAVcc
3
Vcc
33
DATA signal
OE signal
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
QCK
DR
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 2 of 7
PIN CONFIGURATION ( TOP VIEW )
FUNCTIONAL DESCRIPTION
As R8A66160 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for
LED drive while maintaini ng low power consumption and allowance for high noises.
Each bit of a shift register con sists of two flip-flop having independent clocks for shifting and latching.
As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and
latch operations being mad e when “L” changes to “H”.
Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers
one by one when a pulse is impressed to CKS. Whe n A is “L”, the signal of “L” shifts.
When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching
register, and they appear in the parallel data outputs from QA ~ QP.
Outputs QA ~ QP are open drain output s.
To extend the number of bits, use the serial data output SQP which shows the output of the shifting register
of the 16th bit.
When reset input R is changed to “L”, QA ~ QP and SQP are reset. In this case, shifting and latching register
are reset.
If “H” is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not
reach the high impedance st ate. Furthermore, change in OE does not affect shift operation.
FUNCTION TABLE (Note: 1)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QA
QB
A
OE
CKL
R
CKS
SQP
QO
QP
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
A
CKL
CKS
SQP
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
PARALLEL DATA
OUTPUTS
SERIAL DATA INPUT
ENABLE INPUT
LATCH CLOCK INPUT
DIRECT RESET INPUT
SHIFT CLOCK INPUT
SERIAL DATA OUTPUT
PARALLEL DATA
OUTPUTS
PARALLEL DATA
OUTPUTS
VCC
GND
QA
QB
OE
R
QO
QP
：Change from low-level to high-level
：Output state Q bef ore CKLchanged
：Irrelevant
：Contents of s hift register before CK Schanged
：Contents of s hift register
：t2is set after t1is set
：High Impedance
Operatio n mode
Shift
Latch
operation
Input Parallel dat a output
CKSCKLAR OE QAQBQCQDQEQFQGQHQIQJQKQLQMQNQOQP
Serial
data
output
SQP
Remarks
Shift t1H↑XHLQA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
Latch t2HX
↑XL H
qA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Shift t1H↑XLL
QA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
Latch t2HX
↑XL ZqA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Reset LXXXX ZZZZZZ ZZZZZZZ ZZ ZL
Output
lighting
“H”
Output
lights-out
“L”
Output disa ble XXXXHZZZZZZZZZZZZZ ZZ Z
qP
Note1:↑
Q
X
q
q
t1, t2
Z
0
0：Change from low-level to high-level
：Output state Q bef ore CKLchanged
：Irrelevant
：Contents of s hift register before CK Schanged
：Contents of s hift register
：t2is set after t1is set
：High Impedance
Operatio n mode
Shift
Latch
operation
Input Parallel dat a output
CKSCKLAR OE QAQBQCQDQEQFQGQHQIQJQKQLQMQNQOQP
Serial
data
output
SQP
Remarks
Shift t1H↑XHLQA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
Latch t2HX
↑XL H
qA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Shift t1H↑XLL
QA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
Latch t2HX
↑XL ZqA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Reset LXXXX ZZZZZZ ZZZZZZZ ZZ ZL
Output
lighting
“H”
Output
lights-out
“L”
Output disa ble XXXXHZZZZZZZZZZZZZ ZZ Z
qP
Operatio n mode
Shift
Latch
operation
Input Parallel dat a output
CKSCKLARR OEOE QAQBQCQDQEQFQGQHQIQJQKQLQMQNQOQPQAQBQCQDQEQFQGQHQIQJQKQLQMQNQOQP
Serial
data
output
SQP
Remarks
Shift t1H↑XHLQA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
qO0
Latch t2HX
↑XL H
qA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Latch t2HX
↑XL H
qA0
qA0qB0
qB0qC0
qC0qD0
qD0qE0
qE0qF0
qF0qG0
qG0qH0
qH0qI0
qI0qJ0
qJ0qK0
qK0qL0
qL0qM0
qM0qN0
qN0qO0
qO0qO0
qO0
Shift t1H↑XLL
QA
0QB
0QC
0QD
0QE
0QF
0QG
0QH
0QI0QJ0QK
0QL
0QM
0QN
0QO
0QP
0qO0
Latch t2HX
↑XL ZqA0qB0qC0qD0qE0qF0qG0qH0qI0qJ0qK0qL0qM0qN0qO0qO0
Latch t2HX
↑XL ZqA0
qA0qB0
qB0qC0
qC0qD0
qD0qE0
qE0qF0
qF0qG0
qG0qH0
qH0qI0
qI0qJ0
qJ0qK0
qK0qL0
qL0qM0
qM0qN0
qN0qO0
qO0qO0
qO0
Reset LXXXX ZZZZZZ ZZZZZZZ ZZ ZL
Output
lighting
“H”
Output
lights-out
“L”
Output disa ble XXXXHZZZZZZZZZZZZZ ZZ Z
qPqP
Note1:↑
Q
X
q
q
t1, t2
Z
0
0
Note1:↑
Q
X
q
q
t1, t2
Z
0
0
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 3 of 7
ABSOLUTE MA XIMUM RATING S (Ta=-40~+85oC, unless otherwise noted)
Symbol Parameter Conditions Ratings Unit
VCC Supply voltage -0.5 ~ +7.0 V
VI Input voltage -0.5 ~ VCC+0.5 V
VO Output voltage -0.5 ~ VCC+0.5 V
QA ~ QP -50
IO Output current per
output pin SQP ±25 mA
ICC Supply / GND current VCC, GND -410, +20 mA
Pd Power dissipation (Note 2) 500 mW
Tstg Storage temperature range -65 ~+150 oC
Note 2: R8A66160SP; Ta=-40~+70oC, Ta=+70~+85oC are derated at -6mW/oC.
RECOMMENDED OPERATING CONDITIONS (Ta=-40~+85oC, unle ss otherwise noted)
Limits
Symbol Parameter Min. Typ. Max.
Unit
5.0V support 4.5 5.0 5.5 V
VCC Supply voltage 3.3V support 3.0 3.3 3.6 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
Topr Operating temperature range -40 +85 oC
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 4 of 7
ELECTRICAL CHARACTERISTICS
■5.0V version support specifications (Ta=-40~+85oC,Vcc=4.5V~5.5V, unless otherwise noted)
Limits
Symbol Parameter Test conditions
Min. Typ. Max.
Unit
VT+ Positive-going threshold
voltage VO=0.1V, VCC-0.1V
|IO|=20uA 0.35xVCC 0.70xVCC V
VT- Negative-going threshold
voltage VO=0.1V, VCC-0.1V
|IO|=20uA 0.20xVCC 0.55xVCC V
IOH= -20uA VCC-0.1
VI=VT+,VT-
VCC=4.5V IOH= -24mA 3.66
VOH High-level output
voltage QA ~ QP (Note3) IOH= -40mA 3.25 V
IOH= -20uA VCC-0.1
VOH High-level output
voltage SQP VI=VT+,VT-
VCC=4.5V IOH= -4mA 3.66 V
IOL= 20uA 0.10
VOL Low-level output
voltage SQP VI=VT+,VT-
VCC=4.5V IOL= 4mA 0.53 V
IIH High-level input current VI=VCC, VCC=5.5V 5 uA
IIL Low-level input current VI=GND, VCC=5.5V -5 uA
VO=VCC 10
IO Maximum output
leakage current QA ~ QP VI=VT+,VT-
VCC=5.5V VO=GND -10
uA
ICC Quiescent supply current VI=VCC,GND, VCC=5.5V 200 uA
Note 3: R8A66160 is used under the condition of an output current IOH=-40mA, the number of simultaneous drive outputs is
restricted as shown in the Duty Cycle – IOH of TYPICAL CHARACTERISTICS.
■3.3V version support specifications (Ta=-40~+85oC,Vcc=3.0V~3.6V, unless otherwise noted)
Limits
Symbol Parameter Test conditions
Min. Typ. Max.
Unit
VT+ Positive-going threshold
voltage VO=0.1V, VCC-0.1V
|IO|=20uA 0.35xVCC 0.70xVCC V
VT- Negative-going threshold
voltage VO=0.1V, VCC-0.1V
|IO|=20uA 0.20xVCC 0.55xVCC V
IOH= -20uA VCC-0.1
IOH= -12mA 2.34
VOH High-level output
voltage QA ~ QP VI=VT+,VT-
VCC=3.0V IOH= -20mA 2.08 V
IOH= -20uA VCC-0.1
VOH High-level output
voltage SQP VI=VT+,VT-
VCC=3.0V IOH= -2mA 2.60 V
IOL= 20uA 0.10
VOL Low-level output
voltage SQP VI=VT+,VT-
VCC=3.0V IOL= 2mA 0.40 V
IIH High-level input current VI=VCC, VCC=3.6V 5 uA
IIL Low-level input current VI=GND, VCC=3.6V -5 uA
VO=VCC 10
IO Maximum output
leakage current QA ~ QP VI=VT+,VT-
VCC=3.6V VO=GND -10
uA
ICC Quiescent supply current VI=VCC,GND, VCC=3.6V 200 uA
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 5 of 7
SWITCHING CHARACTERISTICS (Ta=-40~+85oC,Vcc=5.0V or 3.3V)
5.0V specification 3.3V specification
Symbol Parameter Test
conditions Min. Typ. Max. Min. Typ. Max. Unit
fmax Maximum clock frequency 4 3.3 MHz
tPLH 125 150 ns
tPHL Output “L”-“H” and “H”-“L”
propagation time CKS - SQP 125 150 ns
tPHL Output “H”-“L”
propagation time R - SQP 125 150 ns
tPHZ Output “H”-“Z”
propagation time R - QA ~ QP
(turned off) 200 220 ns
tPZH Output “Z”-“H”
propagation time CKL - QA ~ QP
(turned on) 125 150 ns
tPHZ Output “H”-“Z”
propagation time CKL - QA ~ QP
(turned off) 200 220 ns
tPZH Output “Z”-“H”
propagation time OE - QA ~ QP
(turned on) 125 150 ns
tPHZ Output “H”-“Z”
propagation time OE - QA ~ QP
(turned off)
CL=50pF
RL=1KΩ
(Note 4)
200 220 ns
CI Input capacitance 10 10 pF
TIMING REQUIREMENTS (Ta=-40~+85oC,Vcc=5.0V or 3.3V)
5.0V specification 3.3V specification
Symbol Parameter
Test
conditions Min. Typ. Max. Min. Typ. Max. Unit
tw CKS, CKL, R pulse width 125 150 ns
tsu A setup time with respect to CKS 125 150 ns
tsu CKS setup time with respect to CKL 125 150 ns
th A hold time with respect to CKS 15 20 ns
trec R recovery time with respect to CKS, CKL
(Note 4)
70 80 ns
Note4 : Test Circuit
PG
GND
50Ω
INPUT VCC
CL
SQP
(1) The pulse generator (PG) has the following characteristics (10%~90%) : tr=6ns,tf=6ns
(2) The capacitance CLincludes stray wiring capacitance and the probe input capacitance.
RLCL
QA〜QP
DUT
Note4 : Test Circuit
PG
GND
50Ω
INPUT VCC
CL
SQP
CL
SQP
(1) The pulse generator (PG) has the following characteristics (10%~90%) : tr=6ns,tf=6ns
(2) The capacitance CLincludes stray wiring capacitance and the probe input capacitance.
RLCL
QA〜QP
DUT
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 6 of 7
TYPICAL CHARACTERISTICS
TIMING DIAGRAM
50%
CKL
CKS
50%
50%
tsu tw
VCC
GND
VCC
GND
CKS
SQP
QA〜QP
50% 50%
50%
50%
VCC
GND
VOH
VOL
VCC
GND
90% VOH
R
tw
trec
tPHL
tPHZ
CKL50%
tPZH
tPHZ
VCC
GND
50% VOH
90% VOH
QA〜QP
QA〜QP
50% 50%
tsu th
50%
CKS
AVCC
GND
VCC
GND
CKS
SQP
tw
50% 50% 50%
tPLH tPHL
50% 50%
VCC
GND
VOH
VOL
50% 50%
OE tPZH tPHZ
50% 90% VOH
VCC
GND
QA〜QP50%
CKL
CKS
50%
50%
tsu tw
VCC
GND
VCC
GND
50%
CKL
CKS
50%
50%
tsu tw
VCC
GND
VCC
GND
CKS
SQP
QA〜QP
50% 50%
50%
50%
VCC
GND
VOH
VOL
VCC
GND
90% VOH
R
tw
trec
tPHL
tPHZ
CKS
SQP
QA〜QP
50% 50%
50%
50%
VCC
GND
VOH
VOL
VCC
GND
90% VOH
RR
tw
trec
tPHL
tPHZ
CKL50%
tPZH
tPHZ
VCC
GND
50% VOH
90% VOH
QA〜QP
QA〜QP
CKL50%
tPZH
tPHZ
VCC
GND
50% VOH
90% VOH
QA〜QP
QA〜QP
50% 50%
tsu th
50%
CKS
AVCC
GND
VCC
GND
50% 50%
tsu th
50%
CKS
AVCC
GND
VCC
GND
CKS
SQP
tw
50% 50% 50%
tPLH tPHL
50% 50%
VCC
GND
VOH
VOL
CKS
SQP
tw
50% 50% 50%
tPLH tPHL
50% 50%
VCC
GND
VOH
VOL
50% 50%
OE tPZH tPHZ
50% 90% VOH
VCC
GND
QA〜QP
50% 50%
OEOE tPZH tPHZ
50% 90% VOH
VCC
GND
QA〜QP
・Repetition frequency＞10Hz
・Numbers in ○indicate the number of output circuits that operate simultaneously.
・Current values are per circuit.
・
・
・
①〜⑯ ①〜⑥
⑦
⑧
⑨
⑩
⑪
⑫
⑬
⑭
⑮
⑯
(上から順に)
Duty Cycle-IOH 特性
Duty Cycle (%) Duty Cycle (%)
IOH(mA)
Vcc=4.5V, Ta＝85℃Vcc=4.5V, Ta＝25℃
020406080100 0 20 40 60 80 100
IOH(mA)
Duty Cycle-IOH 特性
Characteristics Characteristics
From top
to bottom
R8A66160DD/SP
REJ03F0261-0100 Rev.1.00 Jan.10.2008 .
page 7 of 7
PACKAGE OUTLINE
Product name Package RENESAS Code Previous Code
R8A66160DD 24pin DIP PRDP0024AF-A 24P4X-A
R8A66160SP 24pin SOP PRSP0024DF-A 24P2X-B
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