Product Specification PE43701 50 RF Digital Attenuator 7-bit, 31.75 dB, 9 kHz - 4.0 GHz Product Description * HaRPTM-enhanced UltraCMOSTM device ig n * Attenuation: 0.25 dB steps to 31.75 dB * High Linearity: Typical +59 dBm IIP3 * Excellent low-frequency performance * 3.3 V or 5.0 V Power Supply Voltage * Fast switch settling time * Programming Modes: * Direct Parallel Latched Parallel * Serial-Addressable: Program up to eight addresses 000 - 111 * High-attenuation state @ power-up (PUP) * ew D The PE43701 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Features es The PE43701 is a HaRPTM-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 31.75 dB attenuation range in 0.25 dB steps. The Peregrine 50 RF DSA provides a parallel or serialaddressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with Vdd due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. Figure 1. Package Type * No DC blocking capacitors required * Packaged in a 32-lead 5x5x0.85 mm QFN fo rN 32-lead 5x5x0.85 mm QFN Package * CMOS Compatible Figure 2. Functional Schematic Diagram ot Switched Attenuator Array RF Output N RF Input Parallel Control 7 Serial In Control Logic Interface CLK LE A0 A1 Document No. 70-0243-06 www.psemi.com A2 P/S (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Table 1. Electrical Specifications @ +25C, VDD = 3.3 V or 5.0 V Parameter Test Conditions Frequency Min Frequency Range Typical Max Units 4.0 GHz 2.4 dB (0.2+1.5%) (0.15+4%) (0.25+4.5%) dB dB dB 9 kHz Attenuation Range 0.25 dB Step 0 - 31.75 9 kHz 4 GHz 0 dB - 7.75 dB Attenuation settings 8 dB - 31.75 dB Attenuation settings 0 dB - 31.75 dB Attenuation settings Attenuation Error Return Loss 9 kHz < 3 GHz 9 kHz < 3 GHz 3 GHz 4 GHz 9 kHz - 4 GHz 18 Relative Phase All States 9 kHz - 4 GHz P1dB (note 1) Input 20 MHz - 4 GHz IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 30 1MHz Switching Time 50% DC CTRL to 10% / 90% RF RF Trise/Tfall 10% / 90% RF Settling Time RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. 44 deg dBm 59 dBm -110 dBm 10 mVpp 650 ns 400 ns 4 D Video Feed Through dB 32 es Typical Spurious Value dB 1.9 ig n Insertion Loss 25 s Note 1. Please note Maximum Operating Pin (50) of +23dBm as shown in Table 3. ew Performance Plots Figure 3. 0.25 dB Step Error vs. Frequency* 200 MHz 2200 MHz 900 MHz 3000 MHz 1800 MHz 0.50 Figure 4. 0.25dB Attenuation vs. Attenuation State 0.25-dB PE43701 Attenuation 35 900 MHz 1800 MHz 2200 MHz 3800 MHz 0.00 -0.25 0 4 8 12 16 20 Attenuation Setting (dB) 24 Attenuation dB rN 0.25 fo Step Error (dB) 30 25 20 15 10 5 0 28 32 0 5 10 ot N 1.5 1dB State 8dB State 200 MHz 2200 MHZ 1.5 1.0 30 35 900 MHz 3000 MHz 1800 MHz 4000 MHz 1.0 Attenuation Error (dB) Attenuation Error (dB) 25 Figure 6. 0.25 dB Attenuation Error vs. Frequency Figure 5. 0.25 dB Major State Bit Error 0.5dB State 4dB State 31.75dB State 20 Attenuation State *Monotonicity is held so long as Step-Error does not cross below -0.25 0.25dB State 2dB State 16dB State 15 0.5 0.0 -0.5 0.5 0.0 -0.5 -1.0 -1.0 -1.5 -1.5 0 1000 2000 Frequency (MHz) 3000 4000 (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 2 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Figure 7. Insertion Loss vs. Temperature -40C 0 +25C Figure 8. Input Return Loss vs. Attenuation: T = +25C +85C 0 -0.5 0.25dB 8dB -2 -2.5 -3 -3.5 2dB -20 -30 -40 -50 -4 -5 -70 1.0 2.0 3.0 4.0 5.0 Frequency (GHz) 6.0 7.0 8.0 9.0 0 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 1 2 3 4 5 Frequency (GHz) 6 7 8 9 Figure 10. Input Return Loss vs. Temperature: 16dB State Figure 9. Output Return Loss vs. Attenuation: T = +25C 0dB 4dB 0 D 0.0 es -60 -4.5 2dB -40C 25C 85C ew 0 -20 rN -30 -40 -50 -60 1 2 3 4 5 Frequency (GHz) 6 fo 0 7 8 Return Loss (dB) -5 -10 Return Loss (dB) 1dB 31.75dB ig n Return Loss (dB) -1.5 0 -5 -20 -25 -40 0 9 1 2 0dB 4dB 120 -15 -20 -25 -30 -35 -40 3 4 5 Frequency (GHz) 6 7 8 9 Figure 12. Relative Phase vs. Frequency 85C N -10 25C -15 -35 Relative Phase Error (Deg) ot -40C -10 -30 Figure 11. Output Return Loss vs. Temperature: 16dB State Return Loss (dB) 0.5dB 16dB -10 -1 Insertion Loss (dBm) 0dB 4dB 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB 100 80 60 40 20 -45 0 -50 0 1 2 3 4 5 Frequency (GHz) Document No. 70-0243-06 www.psemi.com 6 7 8 9 0 1 2 3 4 5 6 7 Frequency (GHz) (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com 8 PE43701 Product Specification Figure 13. Relative Phase vs. Temperature: 31.75dB State 1800 MHz +25 C 3000 MHz 1.5 30 1.0 Attenuation Error (dB) 35 Phase (deg) 25 20 15 10 0.0 -0.5 -1.0 -1.5 0 0 20 40 60 0.0 80 D +85 C 1.5 16.0 20.0 24.0 28.0 32.0 +25 C -40 C +85 C ew 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 4.0 8.0 12.0 16.0 20.0 Attenuation Setting (dB) fo 0.0 24.0 28.0 Attenuation Error (dB) 1.0 rN Attenuation Error (dB) 12.0 Figure 16. Attenuation Error vs. Attenuation Setting: 3000 MHz Figure 15. Attenuation Error vs. Attenuation Setting: 1800 MHz -40 C 8.0 Attenuation Setting (dB) Temperature (Deg. C) +25 C 4.0 es -20 +85 C 0.5 5 -40 -40 C ig n 900 MHz Figure 14. Attenuation Error vs. Attenuation 0.5 0.0 -0.5 -1.0 -1.5 32.0 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) Figure 17. Input IP3 vs. Frequency 0dB 0.25dB 0.5dB 1dB 4dB 8dB 16dB 31.75dB ot 70 N 65 2dB Input IP3 (dBm) 60 55 50 45 40 35 30 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 4 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification C0.5 C1 C2 C4 C8 C16 SI 32 31 30 29 28 27 26 25 NC 1 24 CLK VDD 2 23 LE P/S 3 22 A1 A0 4 21 A2 GND 5 20 GND GND 6 19 GND RF1 7 18 RF2 GND 8 17 GND Latch-Up Avoidance 10 11 12 13 14 15 16 GND GND GND GND GND GND Switching Frequency 1 N/C No Connect 2 VDD Power supply pin 3 P/S Serial/Parallel mode select 4 A0 Address Bit A0 (LSB) 5, 6, 8-17, 19, 20 GND Ground 7 RF1 RF1 port 18 RF2 RF2 port 21 A2 22 A1 23 LE 24 CLK Exposed Solder Pad Connection ew Description D The PE43701 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Pin Name rN The exposed solder pad on the bottom of the package must be grounded for proper device operation. fo Address Bit A2 Address Bit A1 Latch Enable input ot Serial interface clock input SI Serial Interface input C16 Attenuation control bit, 16 dB C8 Attenuation control bit, 8 dB 28 C4 Attenuation control bit, 4 dB 29 C2 Attenuation control bit, 2 dB 30 C1 Attenuation control bit, 1 dB 31 C0.5 Attenuation control bit, 0.5 dB 32 C0.25 Attenuation control bit, 0.25 dB Paddle GND Ground for proper operation N 27 es 9 GND Moisture Sensitivity Level Pin No. 26 Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. The Moisture Sensitivity Level rating for the PE43701 in the 5x5 QFN package is MSL1. Table 2. Pin Descriptions 25 When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. GND Exposed Solder pad Electrostatic Discharge (ESD) Precautions ig n C0.25 Figure 18. Pin Configuration (Top View) Document No. 70-0243-06 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Table 3. Operating Ranges VDD Power Supply Voltage Min Typ 3.0 3.3 Max Units Symbol V VDD VDD Power Supply Voltage 5.0 5.5 V IDD Power Supply Current 70 350 A Digital Input High 2.6 PIN Input power (50): 1 Hz 20 MHz 20 MHz 4 GHz TOP Operating temperature range -40 25 5.5 V See fig. 19 +23 dBm dBm 85 C 1 V 15 A Parameter/Conditions Min Max Units Power supply voltage -0.3 6.0 V VI Voltage on any Digital input -0.3 5.8 V PIN Input power (50) 1 Hz 20 MHz 20 MHz 4 GHz See fig. 19 +23 dBm dBm TST Storage temperature range VESD ESD voltage (HBM)1 ESD voltage (Machine Model) ig n Parameter Table 4. Absolute Maximum Ratings -65 150 C 500 100 V V 0 Digital Input Leakage1 es Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Digital Input Low Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. D Note 1. Input leakage current per Control pin ew Figure 19. Maximum Power Handling Capability: Z0 = 50 30.0 rN 25.0 15.0 10.0 fo Pin dBm 20.0 ot 5.0 1.0E+04 N 0.0 1.0E+03 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 Hz (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 6 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Table 5. Control Voltage Table 8. Address Word Truth Table State Bias Condition Low 0 to +1.0 Vdc at 2 A (typ) High +2.6 to +5 Vdc at 10 A (typ) Address Word A7 (MSB) A6 A5 A4 A3 A2 X X X X X L X X X X X L Shift Clock Function 0 Shift Register Clocked Contents of shift register transferred to attenuator core X Table 7. Parallel Truth Table D4 D3 D2 D1 D0 L L L L L L L Reference I.L. L L L L L L H 0.25 dB L L L L L H L L L L L H L L L L L H L L L L H L L L H L L L L H H H H H X X X L H L X X X L H H 011 X X X X X H L L 100 X X X X X H L H 101 X X X X X H H L 110 X X X X X H H H 111 L Attenuation Word L Attenuation Setting RF1-RF2 D6 D5 D4 D3 D2 D1 D0 (LSB) L L L L L L L L Reference I.L. L L L L L L L H 0.25 dB D7 0.5 dB L L L L L L H L 0.5 dB 1 dB L L L L L H L L 1 dB 2 dB L L L L H L L L 2 dB 4 dB L L L H L L L L 4 dB rN L 010 X L L 8 dB L L H L L L L L 8 dB L L 16 dB L H L L L L L L 16 dB H H 31.75 dB L H H H H H H H 31.75 dB fo L 001 X D D5 H 000 X ew D6 Attenuation Setting RF1-RF2 L L H Table 9. Attenuation Word Truth Table Parallel Control Setting L L L ig n Latch Enable Address Setting X es Table 6. Latch and Clock Specifications A0 A1 Table 10. Serial-Addressable Register Map ot Bits can either be set to logic high or logic low MSB (last in) Q14 Q13 N Q15 A7 A6 A5 LSB (first in) *D7 must be set to logic low Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A4 A3 A2 A1 A0 *D7 D6 D5 D4 D3 D2 D1 D0 Address Word Attenuation Word Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state at address 3: Address word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary 4 * 18.25 dB 73 01001001 Serial Input: XXXXX01101001001 Document No. 70-0243-06 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification The parallel interface timing requirements are defined by Fig. 21 (Parallel Interface Timing Diagram), Table 12 (Parallel Interface AC Characteristics), and switching speed (Table 1). Power-up Control Settings The PE43701 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In directparallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-s delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). ew For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 21) to latch new attenuation state into device. ig n Parallel Mode Interface The parallel interface consists of seven CMOScompatible control lines that select the desired attenuation state, as shown in Table 7. es Parallel/Serial-Addressable Selection Either a parallel or serial-addressable interface can be used to control the PE43701. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the serial-addressable register is illustrated in Table 10. The serial-addressable timing diagram is illustrated in Fig. 20. D Programming Options rN For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). N ot fo Serial-Addressable Interface The serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 20 illustrates a example timing diagram for programming a state. It is recommended that all parallel control inputs be grounded when the DSA is used in Serial Mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the Attenuation Word. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Dynamic operation between serial-addressable and parallel programming modes is possible. If the DSA powers up in serial-addressable mode (P/ S = HIGH), all the parallel control inputs DI[6:0] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or directparallel mode, all parallel pins DI[6:0] must be set to logic low prior to toggling to serial-addressable mode (P/S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on powerup. Once completed, the DSA may be toggled between serial-addressable and parallel programming modes at will. Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 8 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Figure 20. Serial-Addressable Timing Diagram Bits can either be set to logic high or logic low *D[7] must be set to logic low DI[6:0] T DISU ADD[2:0] TDIH VALID T ASU TAIH P/S T PSSU TPSIH T SISU D[1] D[2] D[3] D[4] D[5] D[6] *D[7] A[0] A[1] A[2] ig n D[0] SI TSIH CLK TCLKL T CLKH TLESU LE T LEPW Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram P/S TPSH D TPSSU VALID DI[6:0] TDISU TDIH ew LE TLEPW DO[6:0] VALID TPD rN TDIPD T PD VALID es DO[6:0] Table 11. Serial-Addressable Interface AC Characteristics Table 12. Parallel and Direct Interface AC Characteristics VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified Parameter Min Max Unit fo Symbol Serial clock frequency - 10 MHz Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 Latch Enable min. pulse width 30 TLEPW ot FCLK TCLKH ns ns TDISU Parallel data setup time 100 - ns - ns TDIH Parallel data hold time 100 - ns - ns TPSSU Parallel/Serial setup time 100 - ns TPSIH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Digital register delay (internal, direct mode only) - 5 ns 10 - ns - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TASU Address setup time 100 - ns N Unit - 10 Address hold time 100 - ns Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Note: Max 30 Serial data hold time TAH Min Latch Enable minimum pulse width Serial data setup time TPSSU Parameter TLEPW TSIH TSISU Symbol TDIPD fClk is verified during the functional pattern test. SerialAddressable programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Document No. 70-0243-06 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Figure 22. Evaluation Board Layout ig n Note: Reference Fig. 23 for Evaluation Board Schematic Serial-Addressable Programming Procedure Position the Parallel/Serial (P/S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A0-A2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then 000 become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. ew Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J1 & Serial header pin and set the D0-D6 SP3T switches to the `MIDDLE' toggle position. Position the Parallel/ Serial (P/S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or SerialAddressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Peregrine Specification 101-0312 es The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE43701 Digital Step Attenuator. D Evaluation Kit ot fo rN For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J1 and Serial header pins. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to VDD. Switches D0-D6 are SP3T switches which enable the user to manually program the parallel bits. When any input D0-D6 is toggled `UP', logic high is presented to the parallel input. When toggled `DOWN', logic low is presented to the parallel input. Setting D0-D6 to the `MIDDLE' toggle position presents an OPEN, which forces an on-chip logic low. Table 9 depicts the parallel programming truth table and Fig. 21 illustrates the parallel programming timing diagram. N Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that Latched-Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from 0V to VDD and back to 0V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 10 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Figure 23. Evaluation Board Schematic ew D es ig n Peregrine Specification 102-0381 Note: Capacitors C1-C8, C13, & C14 may be omitted. On the PE43701 pin 20 (shown as VSS) must be grounded. N ot fo rN Figure 24. Package Drawing QFN 5x5 mm A MAX 0.900 NOM 0.850 MIN 0.800 Document No. 70-0243-06 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification D es ig n Figure 25. Tape and Reel Drawing rN ew Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape ot fo Figure 26. Marking Specifications 43701 YYWW ZZZZZ N YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 13. Ordering Information Order Code Part Marking Description Package Shipping Method PE43701MLI 43701 PE43701 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel PE43701MLI-Z 43701 PE43701 G - 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R EK43701-01 43701 PE43701 G - 32QFN 5x5mm-EK Evaluation Kit 1 / Box (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 UltraCMOSTM RFIC Solutions Page 12 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE43701 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 ig n Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe es Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan rN Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 D Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 ew High-Reliability and Defense Products Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 For a list of representatives in your area, please refer to our Web site at: www.psemi.com fo Data Sheet Identification Advance Information ot The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. N Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Document No. 70-0243-06 www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com