EK43705-11 - PEREGRINE SEMICONDUCTOR

Page 1 of 13

The PE 43 701 is a HaRP™-enhanced, high linearity, 7-bit RF

Digital Step Attenuator (DSA). This highly versatile DSA

covers a 31.75 dB attenuation ra nge in 0.25 dB steps. The

Peregri ne 50Ω RF D SA pr ov ides a parall el or s eri al -

addressable CMOS control interface. It maintains high

att en uation acc ur acy over frequ enc y and tem p er ature an d

exhibits very low insertion loss and low power consumption.

Performance does not change with Vdd due to on-board

regulator. This next generation Peregrine DSA is available in a

5x5 mm 32-lead QFN footprint.

The PE43701 is manufactured on Peregrine’s UltraCMOS™

pro cess, a patented variation of silicon-o n-insulator (SOI)

technology on a sapphire substrate, offering the performance

of GaAs with the econom y an d i nte gr ation of conventi on al

CMOS.

Pro duct Specificat ion

50 Ω RF Digital Atte nuator

7-bit, 31.75 dB, 9 kHz - 4.0 GHz

Product Description

Figure 2. Functional Schematic Diagram

PE43701

Features

• HaRP ™-enha nced UltraCMOS™ device

• Attenuation: 0.25 dB steps to 31.75 dB

• Hi gh Linearity : Ty pi c al + 5 9 dBm IIP3

• Excellent low-frequency performance

• 3.3 V or 5.0 V Power Supply Voltage

• Fast swit ch settling t ime

• Programming Modes:

• Direct Parallel

• Latched Par allel

• Serial-Addressable: Program up to

eight addresses 000 - 111

• High-attenuation state @ powe r-up (PUP)

• CMOS Compatible

• No DC b locking capacitors required

• Packaged in a 32-lead 5x5x0.85 mm QFN

Fig ur e 1. Pa ck ag e Typ e

32-l e ad 5x 5x 0. 85 mm QFN Packag e

Control Logic Interface

RF Input RF Output

Switched Attenuator Array

Serial In

CLK

A0 A1 A2

Parallel Control

P/S

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Product Specification

PE43701

Page 2 of 13

-0.25

0.00

0.25

0.50

0 4 8 12162024 2832

Attenuation Setting (dB)

Step Error (dB)

200 MHz 900 MHz 1800 MHz

2200 MHz 3000 MHz

Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V

Figure 5. 0.25 dB Major State Bit Error

Figure 3. 0.25 dB Step Error vs. Frequency*

Performance Plots

900 MHz

1800 MHz

2200 MHz

3800 MHz

5 1015202530035

Attenuation State

Attenuation dB

0.25-dB PE43701 Attenuation

Fig ur e 4. 0. 25d B Att enuatio n vs. At ten u at ion S t at e

Parameter Test Conditi ons Frequency Min Typical Max Units

Frequency Range 9 kHz 4.0 GHz

Attenuation Range 0.25 dB Step 0 – 31.75 dB

Insertion Lo ss 9 kH z ≤ 4 GHz 1.9 2.4 dB

Attenuation Error 0 dB - 7.75 dB Atten uatio n se tt i ngs

8 dB - 31.75 dB Attenuation settings

0 dB - 31.75 dB Attenuation settings

9 kH z < 3 GHz

3 GHz ≤ 4 GHz

±(0.2+1.5%)

±(0.15+4%)

±(0.25+4.5%)

Re turn Lo ss 9 kHz - 4 GHz 18 dB

Relative Phase All States 9 kHz - 4 GHz 44 deg

P1dB (note 1) Input 20 MHz - 4 GHz 30 32 dBm

IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 59 dBm

Typical Spurious Value 1MHz -110 dBm

Video Feed Through 10 mVpp

Switching Time 50% DC CTRL to 10% / 90% RF 650 ns

RF Trise/Tfall 10% / 90% RF 400 ns

Sett ling Time RF settled to within 0.05 dB of final value

RBW = 5 MHz, Averaging ON. 4 25 µs

*Monotonicity is held so long as Step-Error does not cross below -0.25

Figure 6. 0.25 dB Attenuati on Error vs. Frequency

Note 1. Please note Maximum Operating Pin (50Ω) of +2 3d Bm as sh ow n in Table 3.

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0 1000 2000 3000 4000

Frequency (MHz)

Attenuation Error (dB)

0.25dB State 0.5dB State 1dB State

2dB State 4dB State 8dB State

16dB State 31.75dB State

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0

Attenuation Setting (dB)

Attenuation Error (dB)

200 MHz 900 MHz 1800 MHz

2200 MHZ 3000 MHz 4000 MHz

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Product Specification

PE43701

Page 3 of 13

-70

-60

-50

-40

-30

-20

-10

01234567 89

Frequency (GHz)

Return Loss (dB)

0dB 0.25dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.75dB

-40

-35

-30

-25

-20

-15

-10

-5

0123456789

Frequency (GHz)

Return Loss (dB)

-40C 25C 85C

Figure 9. Output Return Loss vs. Attenuation:

T = +25C

Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenua tion:

T = +25C

Figure 10. Input Return Loss vs. Temperature:

16dB State

Figure 11. Output Return Loss vs . Temperature:

16dB St ate Figure 12. Relative Phase vs. Frequency

-5

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

Frequency (GHz)

Insertion Loss (dBm)

-40C +25C +85C

-60

-50

-40

-30

-20

-10

0123456789

Frequency (GHz)

Return Loss (dB)

0dB 0.25dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.75dB

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0123456789

Frequency (GHz)

Return Loss (dB)

-40C 25C 85C

100

120

012345678

Frequency (GHz)

Relative Phase Error (Deg)

0dB 0.25dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.75dB

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Product Specification

PE43701

Page 4 of 13

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Frequency (MHz)

Input IP3 (dBm

)

0dB 0.25dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.75dB

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0

Attenuation Setting (dB)

Attenuation Error (dB)

+25 C -40 C +85 C

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0

Attenuation Setting (dB)

Attenuation Error (dB)

+25 C -40 C +85 C

-40-200 20406080

Temperature (Deg. C)

Phase (deg)

900 MHz 1800 MHz 3000 MHz

Figure 15. Attenuation Error vs. Attenuati on

Se tting: 1800 MHz

Figure 13. Rela tive Phase vs. Temperature:

31.75dB State Figure 14. Attenuation Error vs. Attenuation

Figure 16. Attenuation Error vs. Attenuation

Setting: 3000 MHz

Figure 17. Input IP3 vs. Frequency

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0

Attenuation Setting (dB)

Attenuation Error (dB)

+25 C -40 C +85 C

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Product Specification

PE43701

Page 5 of 13

124

32 31 30 29 28 27 26 25

161514131211109

Exposed

Solder pad

VDD

P/S

GND

RF1

GND

CLK

GND

RF2

GND

C0.25

C0.5

C16

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ device, obser ve the

same pr ec autions t hat you would us e with other ESD-

sensit iv e devices. Although t his device contains

circ uitry to protect it from dam age due to ES D,

precautions should be taken to avoid exceeding t he

specif ied r ating.

Expose d Solder Pad Connection

The expos ed s older pad on the bott om of t he pac k age

must be grounded f or pr oper dev ic e oper ation.

Figure 18. Pin Configurati on (Top View)

Latc h-Up Avoidance

Unlike conventional CMO S dev ices, UltraCMOS™

devices are immune to latc h- up.

Swi tc hing Frequency

The PE 43701 has a maximum 25 kHz switc hing r ate.

Switc hing r ate is def ined to be the speed at which the

DSA can be toggled across attenuation states.

Pin No. Pi n Name Description

1 N/C No Connect

2 VDD Power supply pin

3 P/S Serial/ P aral le l mode sel ec t

4 A0 Address Bit A0 (LSB)

5, 6, 8-1 7,

19, 20 GND Ground

7 RF1 RF1 port

18 RF2 RF2 port

21 A2 Address Bit A2

22 A1 Address Bit A1

23 LE Latch Enable input

24 CLK Serial interface clock input

25 SI Seri al Inter f ac e in pu t

26 C16 Attenuation control bit, 16 dB

27 C8 Attenuation control bit, 8 dB

28 C4 Attenuation control bit, 4 dB

29 C2 Attenuation control bit, 2 dB

30 C1 Attenuation control bit, 1 dB

31 C0.5 Attenuation control bit, 0.5 dB

32 C0.25 Attenuation control bit, 0.25 dB

Pad dl e GN D Ground for pr op er operati on

Table 2 . Pin Descriptions

Moist u re Sensitivit y Lev el

The Mois ture Sensitiv ity Level r ating for the PE43701 in

the 5x5 QF N pac kage is MSL1.

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Product Specification

PE43701

Page 6 of 13

0.0

5.0

10.0

15.0

20.0

25.0

30.0

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

Pin dBm

Table 3. Opera ti ng Ranges Table 4. Absolute Maximum Ratings

Exceeding abs olute max im um r atings may cause

permanent damage. Operation should be res tricted to

the limits in t he Operating Ranges t able. Operation

between oper ating range max im um and abs olute

maximum for extended per iods m ay r educ e r eliability.

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 6.0 V

VI Voltage on any Digital input -0.3 5.8 V

TST Storage temperature range -65 150 °C

VESD ESD voltage (HBM)1

ESD volt age (Ma chine Model ) 500

100 V

PIN Input power (50Ω)

1 Hz ≤ 20 MHz

20 MHz ≤ 4 GH z

See fig. 19

+23

dBm

Parameter Min Typ Max Units

VDD Power Supply Voltage 3.0 3.3 V

IDD Power Supply Current 70 350 µA

Digital Input High 2.6 5.5 V

PIN Input power ( 50Ω):

1 Hz ≤ 20 MHz

20 MHz ≤ 4 GH z

See fi g. 19

+23

dBm

TOP Opera ti ng te m perat u re

range -40 25 85 °C

Digital Input Low 0 1 V

Digital Input Leakage1 15

µA

VDD Power Supply Voltage 5.0 5.5 V

Note 1. Input leakage current per Control pin

Note : 1. Hu ma n B ody M od el ( HBM, MIL_STD 88 3 Meth od 301 5. 7)

Figure 19. Maximum Power Ha ndling Capability: Z0 = 50 Ω

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Product Specification

PE43701

Page 7 of 13

Table 6. Latch and Clock Specifications

Table 5. Control Voltage

State Bias Condition

Low 0 to +1.0 Vdc at 2 µA (typ)

High +2.6 to +5 Vdc at 10 µA (typ)

Table 7. Parallel Truth Table

Table 10. Serial-Addressable Re gister Map

Latch Enable Function

0 Shift Regi st er Cl ocked

↑ Contents of shif t register

trans ferr ed t o attenuat or cor e

Shift Clock

↑

Parallel Control Setting Attenuation

Setting

RF1-RF2

D6 D5 D4 D3 D2 D1 D0

L L L L L L L Reference I.L.

L L L L L L H 0.25 dB

L L L L L H L 0.5 dB

L L L L H L L 1 dB

L L L H L L L 2 dB

L L H L L L L 4 dB

L H L L L L L 8 dB

H L L L L L L 16 dB

H H H H H H H 31.75 dB

Addres s Word Address

Setting

(MSB) A6 A5 A4 A3 A2 A1 A0

X X X X X L L L 000

X X X X X L L H 001

X X X X X L H L 010

X X X X X L H H 011

X X X X X H L L 100

X X X X X H L H 101

X X X X X H H L 110

X X X X X H H H 111

Table 8. Address Word Truth Table

Attenuation Wor d

D7 D6 D5 D4 D3 D2 D1 D0

(LSB)

L L L L L L L L Reference I.L.

L L L L L L L H 0.25 dB

L L L L L H L L 1 dB

L L L L H L L L 2 dB

L L L H L L L L 4 dB

L L H L L L L L 8 dB

L H L L L L L L 16 dB

L H H H H H H H 31.75 dB

Attenuation

Setting

RF1-RF2

L L L L L L H L 0.5 dB

Table 9 . Attenuation Word Truth Table

Q15 Q14 Q13 Q12 Q11 Q10

A7 A6 A5 A4 A3 A2

Q9 Q8 Q7 Q6 Q5 Q4

A1 A0 *D7 D6 D5 D4

Q3 Q2 Q1 Q0

D3 D2 D1 D0

Address Word Attenuation Word

LSB (first in)

MSB (last in)

Bits can either be set to logic high or logic low

Attenuation Word is derived directly from the attenuation value. For example, to prog ram the 18.25 dB state

at addr es s 3:

Address word: XXXXX011

Atte nuation Word: Multip ly by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001

Serial Input: XXXXX01101001001

*D 7 mus t be set to lo gic low

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Product Specification

PE43701

Page 8 of 13

Programming Options

Par all el/ Serial-Ad dressable Sele ct ion

Either a parallel or serial-addressable interface can

be used to control the PE43701. The P/S b it

provides this selectio n, with P/S=LOW selecting the

parallel interface and P/S=HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of seven CMOS-

compatible control lines that select the desired

attenuation state, as shown in T abl e 7.

The parallel interface timing requirements are

defined by Fig. 21 (Parallel Interface Timing

Diagram), Table 12 (Pa rallel In terface AC

Characteristics), and switching speed (Table 1).

For latched-parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Fig. 21) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

at tenuation stat e contro l v alues will c hange device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Serial-Addressable Interface

The serial-addressable interface is a 16-bit serial-in,

parallel-out shift register buffered by a transparent

latch. The 16-bits make up two words comprised of

8-bits each. The first word is the Attenuation Word,

which controls the state of the DSA. The second

word is the Address Word, which is compared to the

static (or programmed) logical states of the A0, A1

and A2 digital inputs. If there is an address match,

the DSA changes state; otherwise its current state

will rema in un ch anged. Fig. 20 illustrates a example

timing diagram for programming a state. It is

recommended that all parallel control inputs be

grounded when the DSA is used in Serial Mode.

The serial-addressable interface is controlled using

three CMOS-compatible signals: Serial-In (SI),

Clock (CLK), and Latch Enable (LE). The SI and

CLK inputs allow data to be serially entered into the

shift register. Serial data is clocked in LSB first,

beginning with the Attenuation Word.

The shift register must be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data into the DSA. Address word and

attenuation word truth tables are listed in Table 8 &

Table 9, respectively. A programming example of the

serial-addressable register is illustrated in T abl e 10.

The serial-addressable timing diagram is illustrated

in Fig. 20.

Power-up Control Setti ngs

The PE43701 will a lways initialize to the maximum

attenuation setting (31.75 dB) on power-up for both

the serial-addressable and latched-parallel modes of

operation and will remain in this sett ing until t he us er

latches in the next programming word. In direct-

parallel mode, the DSA can be preset to any state

within the 31.75 dB range by pre-setting the parallel

control pins prior to power-up. In this mode, there is

a 400-µs delay between the time the DSA is

powered-up to the time the desired state is

set. During this power-up delay, the device

attenuates to the maximum attenuation setting

(31.75 dB) before defaulting to the user defined

state. If the control pins are left floating in this mode

during power-up, the devic e will default to the

minimum attenuation setting (insertion loss state).

Dynamic operation between serial-addressable and

parallel programming modes is possible.

If the DSA powers up in serial-addressable mode (P/

S = HIGH), all the parallel control inputs DI[6:0] must

be set to logic low. Prior to toggling to parallel mode,

the DSA must be programmed serially to ensure

D[7 ] is set t o logic low.

If the DSA powers up in either latched or direct-

parallel mode, all parallel pins DI[6:0] must be set to

logic low prior to toggling to serial-addressable mode

(P/S = HIGH), and held low until the DSA has been

programmed serially to ensure bit D[7] is set to logic

low.

The sequencing is only required once on power-

up. Once completed, the DSA may be toggled

between serial-addressable and parallel

programming modes at will.

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Product Specification

PE43701

Page 9 of 13

Table 12. Paral lel and Di rect Inte rface

AC Characteristics

Table 11. Ser i al-A d dressable Interf a ce

AC Characteristics

Note: fClk is verified during the functional pattern test. Serial-

Addressable programming sections of the functional

pattern are clocked at 10 MHz to verify fclk specification.

VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified

Figure 20. Serial-Addressable Timing Diagram

Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram

Symbol Parameter Min Max Unit

FCLK Serial clock frequency - 10 MHz

TCLKH Serial clock HIGH time 30 - ns

TCLKL Serial clock LOW time 30 - ns

TLESU Last serial clock rising edge setup

time to Latch Enable rising edge 10 - ns

TLEPW Latch Ena bl e mi n. pu ls e width 30 - ns

TSISU Serial data setup time 10 - ns

TSIH Serial data hold time 10 - ns

TDISU Parallel da ta set up t i me 100 - ns

TDIH Parallel data hold time 100 - ns

TASU Address setup time 100 - ns

TAH Address hold time 100 - ns

TPSSU Parallel/Serial setup time 100 - ns

TPSH Parallel/Serial hold time 100 - ns

TPD Digital register delay (internal) - 10 ns

Symbol Parameter Min Max Unit

TLEPW Latch Enable minimum

pulse width 30 - ns

TDISU Para llel da ta setup time 100 - ns

TDIH Parallel data hold time 100 - ns

TPSSU Parallel/Serial setup time 100 - ns

TPSIH Parallel/Serial hold time 100 - ns

TPD Digital register delay

(internal) - 10 ns

TDIPD Digital register delay

(internal, direct mode only) - 5 ns

VALID

DISU

DIH

DI[6:0]

P/S

PSSU

PSH

LEPW

VALID

DO[6:0]

DIPD

A[2]A[1]A[0]

SISU

CLKL

LE PW

SIH

CLK H

CLK

P/S

LESU

PSSU

PSIH

VAL ID

ASU

ADD[2:0]

AIH

DO[6:0]

VALID

DI[6:0]

DIS U

DIH

D[6]D[5]D[4]D[3]D[2]D[1]D[0] *D[7]

*D[7] must be set to logic low

Bits can either be set to logic high or logic low

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Product Specification

PE43701

Page 10 of 13

Evaluation Kit

The Di gi tal Att en ua t or E val u ation Kit bo ard w as

designed to eas e c ustomer ev aluation of the

PE43701 Digital Step Attenuator.

Direct-Parallel Programming Procedure

For automated direct-parallel programming,

connect the test harness provided with the EVK

from the parallel port of the PC to the J1 & Serial

header pin and set the D0-D6 SP3T switches to the

‘MIDDL E’ toggle po s ition. Position the Para llel/

Serial (P/S) select switch to the Parallel (or left)

position. The evaluation software is written to

operate the DSA in either Parallel or Serial-

Addressable Mo de. Ensure that the software is set

to program in Direct-Parallel mode. Using the

software, enable or disable each setting to the

desired attenuation state. The software

automatically programs the DSA each time an

attenuation state is enabled or disabled.

For manual direct-parallel programming,

disconnect the test harness provided with the EVK

from the J1 and Serial header pins. Position the

Pa ralle l/Serial (P/S) select switch to the Para llel (or

left) positi o n. Th e LE pin on the Ser ial he ad er mu st

be tied to VDD. Switches D0-D6 are SP3T switches

whi ch en abl e t he user to m an ual l y pr ogram the

parallel bits. When any input D0-D6 is toggled

‘UP’, logic high is presented to the parallel input.

When toggled ‘DOWN’, logic low is presented to

the parallel input. Setting D0 -D6 to the ‘MIDDLE’

toggle position presents an OPEN, which forces an

on-chip logic low. Table 9 depicts the parallel

programming truth table and F i g. 21 illustrates the

parallel programming timing diagram.

Latc he d- P ar al l el Pr ogramm i ng Pr ocedur e

For automated latched-parallel programming , the

procedure is identical to the direct-parallel method.

The user only must ensure that Latched-Parallel is

selected in the software.

For manual latched-parallel programming, the

procedure is identical to direct-parallel except now

the LE pin on the Serial header must be logic low

as the parallel bits are applied. The user must then

pulse LE from 0V to V DD and back to 0V to latch the

programming word into the DSA. LE must be logic

low prior to pr ogrammi ng th e nex t wor d .

Figure 22. Evaluation Board Layout

Peregr ine S pec ificat ion 101- 0312

Seri al - A ddr es s able Programm i ng Pr oc edure

Po sition the Parallel/Serial (P/S) select switch to

the Serial (or right) position. Prior to

programming, the user must define an address

setting using the ADD header pin. Jump the

mi ddl e pins o n the AD D hea der A0-A2 (or lower )

row of pins to set logic high, or jump the middle

pins to the upper row of pins to set logic low. If

the ADD pi ns are l eft op e n, the n 000 become the

default address. The evaluation so ftware is

written to operate the DSA in either Parallel or

Serial-Addressable Mode. Ensure that the

software is set to program in Serial-Addressable

mode. Using the software, enable or disable each

setting to the desired attenuation state. The

software automatically programs the DSA each

time an attenuation state is enabled or disabled.

Not e : Refe rence Fig. 23 f or Evaluation Board Schematic

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Product Specification

PE43701

Page 11 of 13

Figure 24. Package Drawing

QFN 5x5 mm

A MAX 0.900

NOM 0.850

MIN 0.800

Figure 23. Evaluation Board Schematic

Peregr ine S pec ificat ion 102- 0381

Note: Capacitors C1-C8, C13, & C14 may be omitted.

On the PE43701 pin 20 (shown as VSS) must be grounded.

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Product Specification

PE43701

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Table 13. Ordering Information

Figure 26. Marking Specifi cations

43701

YYWW

ZZZZZ YYWW = Date Code

ZZZZZ = Last five digits of Lot Number

Figure 25. Tape and Reel Drawing

Order Code Pa rt Marki ng Description Package Shipping Method

PE43701MLI 43701 PE43701 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel

PE43701MLI-Z 43701 PE43701 G – 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R

EK43701-01 43701 PE43701 G – 32QFN 5x5mm-EK Evaluation Kit 1 / Box

Device Orientation in Tape

Top of

Device

Pin 1

Tape Feed Dire c tion

Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

Not for New Design

Product Specification

PE43701

Page 13 of 13

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vent s

F-92380 Garches , France

Tel: +33-1-4741-9173

Fax : +33-1 -4741 -917 3

For a list of represent at ives in your area, please r efer to our Web site at: www.psemi .com

Data Sheet Identification

Advance Information

The product is in a f ormative or design stage. The data

sheet contains design target specifications f or product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine r eserves the right

to change specifications at any time without notice in order

to supply t he best possible product.

Product Specification

The data sheet con tains final data. In the event Peregrine

dec ide s to cha nge the spe c ific ations, Pereg rine will not ify

customers of t he intended changes by issuing a CNF

(Customer Notification Form).

The information in t his data sheet is believed to be reliable.

Howeve r, Peregrine assume s no liabilit y for the use of this

information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this

data sheet are implied or gr anted to any third party.

Peregrine’s pr oducts are not designed or int ended for use in

devices or systems intended f or surgical implant, or in other

applications intended t o support or sustain life, or in any

application in which the failure of the Peregrine pr oduct could

create a situat ion in which personal injury or death m ight occur.

Peregr ine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The Peregrine name, logo, and UTSi are registered tr ademarks

and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks

of Peregrine Semiconduct or Corp.

High-Reliability and De fense Products

Americas

San Diego, CA, USA

Phone: 858- 731-9475

Fax: 848-731-9499

Europe/Asia-Pacific

Aix-En-Provence Cedex 3, France

Phone: +33- 4-4239-3361

Fax: +33-4-4239-7227

Peregri ne Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tr ipolis, 210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-943 Sout h Kor ea

Tel: +82-31-728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teiko k u Hote l Tower 10B-6

1- 1-1 Uchisa iwai-c h o, Ch iy oda- k u

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

Not for New Design